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path: root/src/cpu
AgeCommit message (Expand)Author
2015-12-17Drop src/cpu/ indirection for MIPSStefan Reinauer
2015-12-15src/console: Add x86 romstage spinlock option and printk spinlock supportTimothy Pearson
2015-12-08qemu-x86: Enable SMP supportPatrick Georgi
2015-12-06Remove #ifdef checks on Kconfig symbolsMartin Roth
2015-12-06fsp_model_406dx: use external microcode .h files for rangeleyMartin Roth
2015-12-02x86/smm: Initialize SMM on some CPUs one-by-oneDamien Zammit
2015-12-01cpu/amd/fam10h-15h: Enable DFE on Family 15h HT3 linksTimothy Pearson
2015-12-01cpu/amd/fam10h-15h: Fix link type detection and XCS buffer count setupTimothy Pearson
2015-12-01cpu/amd/fam10h-15h: Force iolink detect to either 1 or 0Timothy Pearson
2015-11-30cpu/amd/family_10h-family_15h: Apply missing Family 15h errata fixesTimothy Pearson
2015-11-26amd/car: don't apply Fam10h/Fam12h Errata 343 fix to Fam0FhJonathan A. Kollasch
2015-11-24FSP 1.0: Fix CAR issues - broken timestamps and consoleBen Gardner
2015-11-24northbridge/amd/amdht: Add isochronous setup supportTimothy Pearson
2015-11-24amd/amdfam10: Control Fam15h cache partitioning via nvramTimothy Pearson
2015-11-24Unify OBJCOPY arguments throughout various x86 stagesStefan Reinauer
2015-11-24cpu/intel/socket_FCBGA559: Add new socket for Atom D5xxDamien Zammit
2015-11-23cpu/amd/fam15h: Set up Link Base Channel Buffer Count registersTimothy Pearson
2015-11-23cpu/amd: de-duplicate MSR include filesStefan Reinauer
2015-11-22cpu/amd/fam10h15h: Set up SRI to XCS Token Count registers on Family 15hTimothy Pearson
2015-11-22cpu/amd/family_10h-family_15h: Set up cache controls on Family 15h to improve...Timothy Pearson
2015-11-22cpu/amd/family_10h-family_15h: Set up link XCS token counts on Family 15hTimothy Pearson
2015-11-22cpu/amd/family_10h-family_15h: Configure NB register 2Timothy Pearson
2015-11-21cpu/amd/car/post_cache_as_ram: Avoid trailing spacesPaul Menzel
2015-11-21amd/family_10h-family_15h: Fix poor performance on Family 15h CPUsTimothy Pearson
2015-11-20northbridge/amd/amdht: Add support for HT3 2.8GHz and up link frequenciesTimothy Pearson
2015-11-20cpu/amd/family_10h-family_15h: Fix incorrect revision detectionTimothy Pearson
2015-11-20nb/amd/amdfam10: Add HyperTransport probe filter supportTimothy Pearson
2015-11-20fsp1_0: Remove hardcoded microcode locationsMartin Roth
2015-11-20cpu/amd/fam10h-fam15h: Set northbridge throttle valuesTimothy Pearson
2015-11-19cpu/amd/fam10h-fam15h: Bring HT register configuration in line with BKDGTimothy Pearson
2015-11-19x86: Add Kconfig to disable early bootblock postcodesMartin Roth
2015-11-18cpu/amd/fam10h-fam15h: Update Fam15h APIC config and startup sequenceTimothy Pearson
2015-11-16intel/fsp_model_406dx: Load APs microcode in model_406dx_initDavid Guckian
2015-11-16intel/fsp_rangeley: Load BSP microcode in bootblockDavid Guckian
2015-11-16cpu/amd/fam10h-15h: Fix BSP stack corruption on 32-core Fam10 systemsTimothy Pearson
2015-11-15amd/model_fxx: Check FID&VID Support for the BSP (too)Urja Rannikko
2015-11-15cpu/amd: Fix AMD Family 15h ECC initialization reliability issuesTimothy Pearson
2015-11-14cpu/x86/lapic: Add stack overrun detectionTimothy Pearson
2015-11-11cpu/amd: Add CC6 supportTimothy Pearson
2015-11-10cpu/amd/car: Add romstage BSP stack overrun detectionTimothy Pearson
2015-11-10cpu: Add a way to use microcode .h files back to the buildMartin Roth
2015-11-10amd/model_fxx: fix code style in FID&VID support checkUrja Rannikko
2015-11-10cpu/intel: Add socket BGA1284Marc Jones
2015-11-08cpu/amd/family_10h-family_15h: Increase BSP stack sizeTimothy Pearson
2015-11-08cpu/amd/family_10h-family_15h: Add Family 15h microcode fileTimothy Pearson
2015-11-06amd/00730F01: Add correct CPU modelKyösti Mälkki
2015-11-06AMD binaryPI: Fix include pathsKyösti Mälkki
2015-11-05cpu/microcode: Remove EXTERNAL / ADDED_DURING_BUILD variablesTimothy Pearson
2015-11-03cpu/amd/model_fxx: Backport PowerNow! core count fix from Family 10hTimothy Pearson
2015-11-02cpu/amd: Add initial AMD Family 15h supportTimothy Pearson
2015-11-02cpu/amd/family_10h-family_15h: Use correct label for break stateTimothy Pearson
2015-11-02cpu/amd: Move model_10xxx to family_10h-family_15hTimothy Pearson
2015-10-31tree: drop last paragraph of GPL copyright headerPatrick Georgi
2015-10-31sandybridge: Disable parallel CPU initializationNico Huber
2015-10-30cpu: port amd/pi to 64bitStefan Reinauer
2015-10-30smm: 64bit fixesStefan Reinauer
2015-10-30AMD mainboards: Fix 64bit BiosCallOuts.cStefan Reinauer
2015-10-30cpu/amd/model_fxx: Clear out unused / stale MTRRs in ramstageTimothy Pearson
2015-10-30cpu/amd/model_fxx: Enable FIDVID code on Socket F K8Timothy Pearson
2015-10-30cpu/amd/model_fxx: Backport APIC code and debug aids from Family 10hTimothy Pearson
2015-10-30cpu/amd/car: Honor BKDG recommendations for DisFillP in CARTimothy Pearson
2015-10-30cpu/amd/model_fxx: Fix invalid P-state power valuesTimothy Pearson
2015-10-30cpu/amd/model_fxx: Add Socket F CPU ID mappingsTimothy Pearson
2015-10-29smmhandler: on i945..nehalem, crash if LAPIC overlaps with ASEGPatrick Georgi
2015-10-28cpu/intel/fsp_model_206ax: Load microcode in corebootMartin Roth
2015-10-27cpu/amd/car: Add initial Suspend to RAM (S3) supportTimothy Pearson
2015-10-27cpu: create an empty file when no microcode files are givenAlexander Couzens
2015-10-25cpu/amd/car: Use standard integer types in post_cache_as_ram.cTimothy Pearson
2015-10-25cpu/amd/car: remove PRINTK_IN_CAR #define that was hardcoded to 1Timothy Pearson
2015-10-24cpu/amd: Add initial support for AMD Socket G34 processorsTimothy Pearson
2015-10-23cpu/intel: Move Power notification ASL code into `common/acpi`Paul Menzel
2015-10-23cpu/amd/model_10xxx: Clean up debugging statementsTimothy Pearson
2015-10-22model_fxx/powernow: add dual core Socket F TDPsJonathan A. Kollasch
2015-10-22Revert "Remove sandybridge and ivybridge FSP code path"Martin Roth
2015-10-16cpu/amd/model_10xxx: Install AMD-provided microcode files in CBFSTimothy Pearson
2015-10-15cpu/x86/mtrr: Add MTRR index and total MTRRs to error messagePaul Menzel
2015-10-15cpu/mtrr.h: Fix macro names for MTRR registersAlexandru Gagniuc
2015-10-14Revert "Remove FSP Rangeley SOC and mohonpeak board support"Martin Roth
2015-10-14cpu/amd/microcode: Update parser to use stock microcode blobsAudrey Pearson
2015-10-14x86: add standalone verstage supportAaron Durbin
2015-10-08arch/x86/bootblock: Do not include non-code files in bootblock.SAlexandru Gagniuc
2015-10-07x86/bootblock: Use LDFLAGS_bootblock to enable garbage collectionAlexandru Gagniuc
2015-10-05cpu/Makefile.inc: Only inculde x86 subdir if ARCH_x86 is selectedAlexandru Gagniuc
2015-10-03Remove FSP Rangeley SOC and mohonpeak board supportAlexandru Gagniuc
2015-10-03Remove sandybridge and ivybridge FSP code pathAlexandru Gagniuc
2015-10-03sandybridge ivybridge: Treat native init as first class citizenAlexandru Gagniuc
2015-09-30cpu: microcode: Use microcode stored in binary formatAlexandru Gagniuc
2015-09-24coreboot: move TS_END_ROMSTAGE to one spotAaron Durbin
2015-09-14qemu: initialize lapicGerd Hoffmann
2015-09-09linking: add and use LDFLAGS_commonAaron Durbin
2015-09-09rmodule: use program.ld for linkingAaron Durbin
2015-09-09x86: link romstage like the other architecturesAaron Durbin
2015-09-09intel/model_2065x/Kconfig: Don't use LAPIC_MONOTONIC_TIMERMartin Roth
2015-09-09x86: bootblock: remove linking and program flow from build systemAaron Durbin
2015-09-08cpu: fix cpu_microcode classAaron Durbin
2015-09-07microcode: Unify rules to add microcode to CBFS once againAlexandru Gagniuc
2015-09-05amd/geode_lx: make done_cache_as_ram_main globalAaron Durbin
2015-09-04x86: remove cpu_incs as romstage Make variableAaron Durbin
2015-08-25Intel: Remove CACHE_MRC_BIN - 'selected' everywhere in KconfigMartin Roth
2015-08-14cpu/amd/model_10xxx: Do not initialize SMM memory if SMM is disabledTimothy Pearson
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