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path: root/src/cpu
AgeCommit message (Expand)Author
2016-05-06{cpu,soc}/intel: remove unused smm_init() functionAaron Durbin
2016-05-06cpu/x86/mp_init: reduce exposure of internal implementationAaron Durbin
2016-05-06cpu/intel/haswell: convert to using common MP and SMM initAaron Durbin
2016-05-04cpu/x86: combine multiprocessor and SMM initializationAaron Durbin
2016-05-04cpu/x86: remove BACKUP_DEFAULT_SMM_REGION optionAaron Durbin
2016-05-04cpu/x86/smm_module_loader: always build with SMM module supportAaron Durbin
2016-05-02cpu/x86/mp_init: remove unused callback argumentsAaron Durbin
2016-04-28soc/intel/apollolake: Add cache for BIOS ROMAndrey Petrov
2016-04-11cpu/x86/tsc: Compile TSC timer for postcar as wellAndrey Petrov
2016-04-11cpu/x86/tsc: remove conditional compilationAaron Durbin
2016-04-11cpu/x86/tsc: compile same code for all stagesAaron Durbin
2016-04-11cpu/x86/tsc: prepare for CAR_GLOBAL in delay_tsc.cAaron Durbin
2016-04-11src/cpu/x86: remove TSC_CALIBRATE_WITH_IOAaron Durbin
2016-04-10am335x: Add some code for manipulating GPIOsGabe Black
2016-04-10am335x: Add data structures for the clock module registersGabe Black
2016-03-31src/: Fix lint style-labels warningsMartin Roth
2016-03-23arch/x86: introduce postcar stage/phaseAaron Durbin
2016-03-18mtrr: Define a function for obtaining free var mtrrFurquan Shaikh
2016-03-16cpu/x86: compile earlymtrr.c code for romstage as wellAndrey Petrov
2016-03-16cpu/x86/mtrr: remove early_mtrr_* functionsAaron Durbin
2016-03-16cpu/x86/mtrr: move cache_ramstage() to its only userAaron Durbin
2016-03-10cpu/via/c7: Don't manually include udelay_io.cStefan Reinauer
2016-03-10northbridge/intel/i440bx: Unify UDELAY selectionStefan Reinauer
2016-03-08x86 chipsets: utilize x86_setup_mtrrs_with_detect()Aaron Durbin
2016-03-08Kconfig: Remove unneeded UDELAY_IO redeclarationStefan Reinauer
2016-03-08cpu/x86/mtrr: add helper function to detect variable MTRRsAaron Durbin
2016-03-08cpu/x86: Sort some Kconfig optionsStefan Reinauer
2016-03-05arch/x86: document CAR symbols and expose them in symbols.hAndrey Petrov
2016-03-04arch/x86: always use _start as entry symbol for all stagesAaron Durbin
2016-03-04arch/x86: rename reset_vector -> _startAaron Durbin
2016-03-03cpu/x86/16bit: rename _start -> _start16bitAaron Durbin
2016-03-03cpu/x86/16bit/reset16: mark reset vector executableAaron Durbin
2016-03-03cpu/x86/16bit/reset16: remove stale 32-bit jumpAaron Durbin
2016-02-26tree wide: Convert "if (CONFIG_.*_TPM.*)" to "if (IS_ENABLED(...))"Denis 'GNUtoo' Carikli
2016-02-19cpu/qemu-power8: don't enable it for qemu-x86Patrick Georgi
2016-02-19power8: qemu "cpu"Ronald G. Minnich
2016-02-18cpu/amd: Add socket FM2Damien Zammit
2016-02-14cpu/amd: Update/Add license headersDamien Roth
2016-02-14CPU/intel: Add missing license headersDamien Roth
2016-02-13cpu/allwinner: Update license headersDamien Roth
2016-02-12Make MRC vs native a config rather than making a separate chipset for it.Vladimir Serbinenko
2016-02-11cpu/x86/tsc: Compile delay_tsc.c for the bootblock as wellAlexandru Gagniuc
2016-02-10cpu/intel/microcode: allow microcode to be loaded in romstageAaron Durbin
2016-02-05cpu/amd/fam10h-fam15h: Honor CMOS option to disable CPB (core boost)Timothy Pearson
2016-02-05cpu/amd/fam10h-15h: Set PowerStepUp/PowerStepDown on Fam15hTimothy Pearson
2016-02-02src: Fix various spelling and whitespace issues.Martin Roth
2016-02-02amd/agesa/family15tn: Add Richland CPU IDLoic
2016-02-02src/: Fix Kcofig symbols missing CONFIG_ prefixMartin Roth
2016-02-01cpu/amd/fam10h-15h: Add workaround for AMD Erratum 600Timothy Pearson
2016-02-01cpu/amd/fam10h-fam15h: Add new wait_ap_stopped functionTimothy Pearson
2016-02-01cpu/amd/fam10h-15h: Fix Family 15h boot hang when BSP lift enabledTimothy Pearson
2016-01-29cpu/amd/fam10h-fam15h: Correctly create APIC ID on single node systemsTimothy Pearson
2016-01-28Move object files to $(obj)/<class>/Nico Huber
2016-01-28Makefile: Make full use of src-to-obj macroNico Huber
2016-01-24cpu/amd/family_10h-family_15h: Move CBMEM storage out of CC6 save regionTimothy Pearson
2016-01-24cpu/amd/family_10h-family_15h: Set LDT tristate correctly on C32 socketsTimothy Pearson
2016-01-23cpu/amd: remove .intel_syntaxPatrick Georgi
2016-01-21*/Makefile.inc: Compile files needed by uart8250 in x86 bootblockAlexandru Gagniuc
2016-01-20Kconfig: Remove selects that enable 'choice' symbolsMartin Roth
2016-01-20cpu: Fix typo that spelled "allocate" as "allocte."Jacob Laska
2016-01-07cpu/amd/microcode: Introduce CBFS access spinlock to avoid IOMMU failureTimothy Pearson
2016-01-06cpu/amd/fam10h-15h: Add tsc_freq_mhz() functionTimothy Pearson
2015-12-30x86 chipsets: Link non-code flow CHIPSET_BOOTBLOCK_INCLUDE filesAlexandru Gagniuc
2015-12-25cpu/allwinner/a10: Fix I2c speed calculationMartin Roth
2015-12-18drivers/pc80: Add optional spinlock for nvram CBFS accessTimothy Pearson
2015-12-18cpu/samsung/exynos5250: Move update-bl1.sh to 3rdparty/blobs/Stefan Reinauer
2015-12-17Drop src/cpu/ indirection for MIPSStefan Reinauer
2015-12-15src/console: Add x86 romstage spinlock option and printk spinlock supportTimothy Pearson
2015-12-08qemu-x86: Enable SMP supportPatrick Georgi
2015-12-06Remove #ifdef checks on Kconfig symbolsMartin Roth
2015-12-06fsp_model_406dx: use external microcode .h files for rangeleyMartin Roth
2015-12-02x86/smm: Initialize SMM on some CPUs one-by-oneDamien Zammit
2015-12-01cpu/amd/fam10h-15h: Enable DFE on Family 15h HT3 linksTimothy Pearson
2015-12-01cpu/amd/fam10h-15h: Fix link type detection and XCS buffer count setupTimothy Pearson
2015-12-01cpu/amd/fam10h-15h: Force iolink detect to either 1 or 0Timothy Pearson
2015-11-30cpu/amd/family_10h-family_15h: Apply missing Family 15h errata fixesTimothy Pearson
2015-11-26amd/car: don't apply Fam10h/Fam12h Errata 343 fix to Fam0FhJonathan A. Kollasch
2015-11-24FSP 1.0: Fix CAR issues - broken timestamps and consoleBen Gardner
2015-11-24northbridge/amd/amdht: Add isochronous setup supportTimothy Pearson
2015-11-24amd/amdfam10: Control Fam15h cache partitioning via nvramTimothy Pearson
2015-11-24Unify OBJCOPY arguments throughout various x86 stagesStefan Reinauer
2015-11-24cpu/intel/socket_FCBGA559: Add new socket for Atom D5xxDamien Zammit
2015-11-23cpu/amd/fam15h: Set up Link Base Channel Buffer Count registersTimothy Pearson
2015-11-23cpu/amd: de-duplicate MSR include filesStefan Reinauer
2015-11-22cpu/amd/fam10h15h: Set up SRI to XCS Token Count registers on Family 15hTimothy Pearson
2015-11-22cpu/amd/family_10h-family_15h: Set up cache controls on Family 15h to improve...Timothy Pearson
2015-11-22cpu/amd/family_10h-family_15h: Set up link XCS token counts on Family 15hTimothy Pearson
2015-11-22cpu/amd/family_10h-family_15h: Configure NB register 2Timothy Pearson
2015-11-21cpu/amd/car/post_cache_as_ram: Avoid trailing spacesPaul Menzel
2015-11-21amd/family_10h-family_15h: Fix poor performance on Family 15h CPUsTimothy Pearson
2015-11-20northbridge/amd/amdht: Add support for HT3 2.8GHz and up link frequenciesTimothy Pearson
2015-11-20cpu/amd/family_10h-family_15h: Fix incorrect revision detectionTimothy Pearson
2015-11-20nb/amd/amdfam10: Add HyperTransport probe filter supportTimothy Pearson
2015-11-20fsp1_0: Remove hardcoded microcode locationsMartin Roth
2015-11-20cpu/amd/fam10h-fam15h: Set northbridge throttle valuesTimothy Pearson
2015-11-19cpu/amd/fam10h-fam15h: Bring HT register configuration in line with BKDGTimothy Pearson
2015-11-19x86: Add Kconfig to disable early bootblock postcodesMartin Roth
2015-11-18cpu/amd/fam10h-fam15h: Update Fam15h APIC config and startup sequenceTimothy Pearson
2015-11-16intel/fsp_model_406dx: Load APs microcode in model_406dx_initDavid Guckian
2015-11-16intel/fsp_rangeley: Load BSP microcode in bootblockDavid Guckian
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