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2011-07-04Small SMM fixupsRudolf Marek
Align the spinlock to the 4 byte boundary (CPU will guarantee atomicity of XCHG). While at it add the PAUSE instruction to spinlock loop to hint the CPU we are just spinlocking. The rep nop could not be used because "as" complains that rep is used without string instructions. Change-Id: I325cd83de3a6557b1bee6758bc151bc81e874f8c Signed-off-by: Rudolf Marek <r.marek@assembler.cz> Reviewed-on: http://review.coreboot.org/81 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-06-28Addition of Family12/SB900 wrapper codeefdesign98
This change adds the wrapper code for the AMD Family12 cpus and the AMD Hudson-2 (SB900) southbridge to the cpu, northbridge and southbridge folders respectively. Change-Id: I22b6efe0017d0af03eaa36a1db1615e5f38da06c Signed-off-by: Frank Vibrans <frank.vibrans@amd.com> Signed-off-by: efdesign98 <efdesign98@gmail.com> Reviewed-on: http://review.coreboot.org/53 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-06-22Move existing AMD Ffamily14 code to f14 folderefdesign98
This change moves the AMD Family14 cpu Agesa code to the vendorcode/amd/agesa/f14 folder to complete the transition to the family oriented folder structure. Change-Id: I211e80ee04574cc713f38b4cc1b767dbb2bfaa59 Signed-off-by: Frank Vibrans <frank.vibrans@amd.com> Signed-off-by: efdesign98 <efdesign98@gmail.com> Reviewed-on: http://review.coreboot.org/52 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-06-22Rename {CPU|NB|SB}/amd/*_wrapper foldersefdesign98
This change renames the cpu/amd/agesa_wrapper, northbridge/ amd/agesa_wrapper, and southbridge/amd/cimx_wrapper folders to {cpu|NB}/amd/agesa and {SB}/amd/agesa to shorten and simplify the folder names. There is also a fix to vendorcode/amd/agesa/lib/amdlib.c to append "ull" to a trio of 64-bit hexadecimal constants to allow abuild to run successfully. Change-Id: I2455e0afb0361ad2e11da2b869ffacbd552cb715 Signed-off-by: Frank Vibrans <frank.vibrans@amd.com> Signed-off-by: efdesign98 <efdesign98@gmail.com> Reviewed-on: http://review.coreboot.org/51 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-06-18SMM: flush caches after disabling cachingSven Schnelle
Fixes spurious SMI crashes i've seen, and ACPI/SMM interaction. For reference, the mail i've sent to ML with the bugreport: whenever i've docked/undocked the thinkpad from the docking station, i had to do that twice to get the action actually to happen. First i thought that would be some error in the ACPI code. Here's a short explanation how docking/undocking works: 1) ACPI EC Event 0x37 Handler is executed (EC sends event 0x37 on dock) 2) _Q37 does a Trap(SMI_DOCK_CONNECT). Trap is declared as follows: a) Store(Arg0, SMIF) // SMIF is in the GNVS Memory Range b) Store(0, 0x808) // Generates I/O Trap to SMM c) // SMM is executed d) Return (SMIF) // Return Result in SMIF I've verified that a) is really executed with ACPI debugging in the Linux Kernel. It writes the correct value to GNVS Memory. After that, i've logged the SMIF value in SMM, which contains some random (or former) value of SMIF. So i've added the GNVS area to /proc/mtrr which made things work. I've also tried a wbinvd() in SMM code, with the same result. After reading the src/cpu/x86/smm/smmhandler.S code, i've recognized that it starts with: movw $(smm_gdtptr16 - smm_handler_start + SMM_HANDLER_OFFSET), %bx data32 lgdt %cs:(%bx) movl %cr0, %eax andl $0x7FFAFFD1, %eax /* PG,AM,WP,NE,TS,EM,MP = 0 */ orl $0x60000001, %eax /* CD, NW, PE = 1 */ movl %eax, %cr0 /* Enable protected mode */ data32 ljmp $0x08, $1f ...which disables caching in SMM code, but doesn't flush the cache. So the problem is: - the linux axpi write to the SMIF GNVS Area will be written to Cache, because GNVS is WB - the SMM code runs with cache disabled, and fetches SMIF directly from Memory, which is some other value Possible Solutions: - enable cache in SMM (yeah, cache poisoning...) - flush caches in SMM (really expensive) - mark GNVS as UC in Memory Map (will only work if OS really marks that Area as UC. Checked various vendor BIOSes, none of them are marking NVS as UC. So this seems rather uncommon.) - flush only the cache line which contains GNVS. Would fix this particular problem, but users/developers could see other Bugs like this. And not everyone likes to debug such problems. So i won't like this solution. Change-Id: Ie60bf91c5fd1491bc3452d5d9b7fc8eae39fd77a Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/39 Tested-by: build bot (Jenkins)
2011-06-15SMM: don't overwrite SMM memory on resumeSven Schnelle
Overwriting the SMM Area on resume leaves us with all variables cleared out, i.e., the GNVS pointer is no longer available, which makes SMIF function calls impossible. Change-Id: I08ab4ffd41df0922d63c017822de1f89a3ff254d Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/34 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-05-15Cosmetic cleanup.Scott Duplichan
Signed-off-by: Scott Duplichan <scott@notabs.org> Acked-by: Marc Jones <marcj303@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6594 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-05-15Correct the number of MCA error reporting banks cleared.Scott Duplichan
Signed-off-by: Scott Duplichan <scott@notabs.org> Acked-by: Marc Jones <marcj303@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6571 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-05-151) Initialize BSP fixed MTRRs to match AP fixed MTRR initialization.Scott Duplichan
2) Remove coreboot variable MTRR initialization because AMD reference code handles it. Signed-off-by: Scott Duplichan <scott@notabs.org> Acked-by: Marc Jones <marcj303@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6570 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-05-10Change read_option() to a macro that wraps some API uglynessPatrick Georgi
Simplify read_option(CMOS_VSTART_foo, CMOS_VLEN_foo, somedefault) to read_option(foo, somedefault) Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6565 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-05-10This replaces the fixed shift values in the apic timer init with macros.Vikram Narayanan
Signed-off-by: Vikram Narayanan <vikram186@gmail.com> Acked-by: Patrick Georgi <patrick@georgi-clan.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6564 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-05-03Enable caching for ROM area in model_6ex/cache_as_ram.incSven Schnelle
Signed-off-by: Sven Schnelle <svens@stackframe.org> Acked-by: Sven Schnelle <svens@stackframe.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6554 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-04-26Add support for memory mapped UARTs to coreboot and add the OXPCIe952 as anStefan Reinauer
example. This newer version reflects the recent changes to further simplify the console code and partly gets rid of some hacks in the previous version. Signed-off-by: Stefan Reinauer <reinauer@google.com> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6544 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-04-21more ifdef -> if fixes.Stefan Reinauer
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6537 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-04-21more ifdef -> if fixesStefan Reinauer
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6536 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-04-19Fix some more misuses of ifdef/if definedStefan Reinauer
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6515 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-04-14drop half an uart8250 implementation from smiutil and use the common code Stefan Reinauer
for that instead. This also allows using non-uart8250 consoles for smi debugging. Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6501 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-04-14earlymtrr.c: wipe some dead code, use names instead of numbers and someStefan Reinauer
cosmetics. Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6499 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-04-14drop incorrectly used CONFIG_ROM_IMAGE_SIZE and unused CONFIG_ARCHStefan Reinauer
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6496 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-04-14Use symbolic names for some MTRR bits instead of numbers in CAR codeStefan Reinauer
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6493 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-04-11Unify use of post_codeAlexandru Gagniuc
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6487 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-03-28Add AMD C32 support.Zheng Bao
It is based on other existing Fam10 code. Signed-off-by: Zheng Bao <zheng.bao@amd.com> Acked-by: Marc Jones <marcj303@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6464 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-03-17Fix breaking the build after removing files in tthe previous checkin. Marc Jones
Signed-off-by: Marc Jones <marcj303@gmail.com> Acked-by: Marc Jones <marcj303@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6453 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-03-04Add P-states for select Socket 754 processors.Jonathan Kollasch
States for AMA3000BEX5AR, SDA3100AIO3BX, and SDA3400AIO3BX are from AMD document 30430 3.51. States for ADA3200AIO4BX derived from SSDT of a MS-7135. States for TMDML34BKX5LD derived from legacy PowerNow! table of a MS-7135, and therefore lack accurate TDP information. Signed-off-by: Jonathan Kollasch <jakllsch@kollasch.net> Acked-by: Marc Jones <marcj303@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6432 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-03-03Correct off-by-one problem in AMD pre-rev-F model-F PowerNow code.Jonathan Kollasch
With this change the last P-state entry of the last CPU in the table is successfully conveyed into the SSDT. Signed-off-by: Jonathan Kollasch <jakllsch@kollasch.net> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6430 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-02-28Improving BKDG implementation of P-states,Xavi Drudis Ferran
CPU and northbridge frequency and voltage handling for Fam 10 in SVI mode. I don't understand what this was doing nor find docs for these regs Maybe it was left over from some copy & paste ? Signed-off-by: Xavi Drudis Ferran <xdrudis@tinet.cat> Acked-by: Marc Jones <marcj303@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6411 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-02-28Improving BKDG implementation of P-states,Xavi Drudis Ferran
CPU and northbridge frequency and voltage handling for Fam 10 in SVI mode. I don't understand what this was doing nor find docs for these regs Maybe it was left over from some copy & paste ? Signed-off-by: Xavi Drudis Ferran <xdrudis@tinet.cat> Acked-by: Marc Jones <marcj303@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6410 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-02-28Improving BKDG implementation of P-states,Xavi Drudis Ferran
CPU and northbridge frequency and voltage handling for Fam 10 in SVI mode. I don't understand what this was doing nor find docs for these regs Maybe it was left over from some copy & paste ? Signed-off-by: Xavi Drudis Ferran <xdrudis@tinet.cat> Acked-by: Marc Jones <marcj303@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6409 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-02-28Improving BKDG implementation of P-states,Xavi Drudis Ferran
CPU and northbridge frequency and voltage handling for Fam 10 in SVI mode. In fact I changed coreDelay before deleting the code in fidvid that called it. But there're still a couple of calls from src/northbridge/amd/amdmct/wrappers/mcti_d.c Since the comment encouraged fixing something, I parametrized it with the delay time in microseconds and paranoically tried to avoid an overflow at pathological moments. Signed-off-by: Xavi Drudis Ferran <xdrudis@tinet.cat> Acked-by: Marc Jones <marcj303@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6408 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-02-28Improving BKDG implementation of P-states,Xavi Drudis Ferran
CPU and northbridge frequency and voltage handling for Fam 10 in SVI mode. Well, I understand it better like this, but maybe it's only me, part of the changes are paranoic, and the only effective change is for a factor depending on mobile or not that I can't test. Signed-off-by: Xavi Drudis Ferran <xdrudis@tinet.cat> Acked-by: Marc Jones <marcj303@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6406 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-02-28Improving BKDG implementation of P-states,Xavi Drudis Ferran
CPU and northbridge frequency and voltage handling for Fam 10 in SVI mode. Add an untested step in BKDG 2.4.2.8. I don't have the hardware with Core Performance Boost and I think it's only available in revision E that does not even have a constant yet. Signed-off-by: Xavi Drudis Ferran <xdrudis@tinet.cat> Acked-by: Marc Jones <marcj303@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6405 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-02-28Improving BKDG implementation of P-states,Xavi Drudis Ferran
CPU and northbridge frequency and voltage handling for Fam 10 in SVI mode. Add to init_fidvid_stage2 some step mentioned in BKDG 2.4.2.7 that was missing . Some lines are dead code now, but may handy if one day we support revison E CPUs. Signed-off-by: Xavi Drudis Ferran <xdrudis@tinet.cat> Acked-by: Marc Jones <marcj303@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6404 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-02-28Improving BKDG implementation of P-states,Xavi Drudis Ferran
CPU and northbridge frequency and voltage handling for Fam 10 in SVI mode. Add to init_fidvid_stage2 some step for my CPU (rev C3) mentioned in BKDG 2.4.2.6 (5) that was missing Signed-off-by: Xavi Drudis Ferran <xdrudis@tinet.cat> Acked-by: Marc Jones <marcj303@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6403 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-02-28Improving BKDG implementation of P-states,Xavi Drudis Ferran
CPU and northbridge frequency and voltage handling for Fam 10 in SVI mode. Looking at BKDG the process for updating Pstate Nb vid after warn reset seemed more similar to the codethat was there fo pvi than the one for svi, so I called the pvi function passing a pvi/svi flag. I don't find documentation on why should UpdateSinglePlaneNbVid() be called in PVI, but since I can't test it, I leave it as it was. This patch showed some progress beyond fidvid in my boar,d but only sometimes, most times it just didn't work. Signed-off-by: Xavi Drudis Ferran <xdrudis@tinet.cat> Acked-by: Marc Jones <marcj303@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6402 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-02-28Improving BKDG implementation of P-states,Xavi Drudis Ferran
CPU and northbridge frequency and voltage handling for Fam 10 in SVI mode. Factor out some common expressions. Add an error message when coreboots hangs waiting for a pstate that never comes (it happened to me), and throw some paranoia at it for good mesure. If I understood BKDG fam10 CPUs never need a software initiated vid transition, because the hardware knows what to do when you just request a Pstate change if the cpu is properly configured. In fact unifying a little what PVI and SVI do was better for my board (SVI). So I drop transitionVid, which I didn't understand either (why did it have a case for PVI if it is never called for PVI ? Why did the PVI case distinguigh cpu or nb when PVI is theoretically single voltage plane ? ). Signed-off-by: Xavi Drudis Ferran <xdrudis@tinet.cat> Acked-by: Marc Jones <marcj303@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6401 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-02-28Improving BKDG implementation of P-states,Xavi Drudis Ferran
CPU and northbridge frequency and voltage handling for Fam 10 in SVI mode. Contemplate the possibility of nbCofVidUpdate not being defined, trying to get closer to BKDG Signed-off-by: Xavi Drudis Ferran <xdrudis@tinet.cat> Acked-by: Marc Jones <marcj303@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6399 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-02-28Improving BKDG implementation of P-states,Xavi Drudis Ferran
CPU and northbridge frequency and voltage handling for Fam 10 in SVI mode. Configuration of F3x[84:80] was hardcoded for rev B. I change that for some code that checks for revision and configures according to BKDG. Unfinished but hopefully better than it was. Signed-off-by: Xavi Drudis Ferran <xdrudis@tinet.cat> Acked-by: Marc Jones <marcj303@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6398 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-02-28Improving BKDG implementation of P-states,Xavi Drudis Ferran
CPU and northbridge frequency and voltage handling for Fam 10 in SVI mode. BKDG says nbSynPtrAdj may also be 6 sometimes. Signed-off-by: Xavi Drudis Ferran <xdrudis@tinet.cat> Acked-by: Marc Jones <marcj303@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6397 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-02-28Improving BKDG implementation of P-states,Xavi Drudis Ferran
CPU and northbridge frequency and voltage handling for Fam 10 in SVI mode. I didn't understand quite why it did that iwth F3xA0 (Power Control Misc Register) so I moved Pll Lock time to rules in defaults.h and reimplemented F3xA0 programming. A later patch will remove a part I don't know what's mean to do. Signed-off-by: Xavi Drudis Ferran <xdrudis@tinet.cat> Acked-by: Marc Jones <marcj303@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6396 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-02-28Improving BKDG implementation of P-states,Xavi Drudis Ferran
CPU and northbridge frequency and voltage handling for Fam 10 in SVI mode. Bring F3xD4 (Clock/Power Control Register 0) more in line with BKDG i more cases. It requires looking at the CPU package type so I add a function for that (in the wrong place?) and some new constants Signed-off-by: Xavi Drudis Ferran <xdrudis@tinet.cat> Acked-by: Marc Jones <marcj303@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6395 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-02-28Prepare for next patches (Improving BKDG implementation of P-states,Xavi Drudis Ferran
CPU and northbridge frequency and voltage handling for Fam 10 in SVI mode). No change of behaviour intended. Refactor FAM10 fidvid . Factor out the decision whether to update northbridge frequency and voltage because there was the same code in 3 places and so we can later modify it in one place. Signed-off-by: Xavi Drudis Ferran <xdrudis@tinet.cat> Acked-by: Marc Jones <marcj303@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6394 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-02-27Prepare for next patches (Improving BKDG implementation of P-states,Xavi Drudis Ferran
CPU and northbridge frequency and voltage handling for Fam 10 in SVI mode). No change of behaviour intended. Refactor FAM10 fidvid . Factor out the decision whether to update northbridge frequency and voltage because there was the same code in 3 places and so we can later modify it in one place. Signed-off-by: Xavi Drudis Ferran <xdrudis@tinet.cat> Acked-by: Marc Jones <marcj303@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6393 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-02-27Prepare for next patches (Improving BKDG implementation of P-states,Xavi Drudis Ferran
CPU and northbridge frequency and voltage handling for Fam 10 in SVI mode). No change of behaviour intended. Refactor FAM10 fidvid. Factor out a little common code. Also, our earlier config_clk_power_ctrl_reg0 was still too long and it'd get longer with forthcoming patches. We now take apart F3xD4[PowerStepUp,PowerStepDown] to its own function. Signed-off-by: Xavi Drudis Ferran <xdrudis@tinet.cat> Acked-by: Marc Jones <marcj303@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6392 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-02-27Prepare for next patches (Improving BKDG implementation of P-states,Xavi Drudis Ferran
CPU and northbridge frequency and voltage handling for Fam 10 in SVI mode). No change of behaviour intended. Refactor FAM10 fidvid . prep_fid_change was already long and it'd get longer with forthcoming patches. We now take apart F3x[84:80], ACPI Power State Control Registers, to its own function. Signed-off-by: Xavi Drudis Ferran <xdrudis@tinet.cat> Acked-by: Marc Jones <marcj303@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6391 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-02-27Prepare for next patches (Improving BKDG implementation of P-states,Xavi Drudis Ferran
CPU and northbridge frequency and voltage handling for Fam 10 in SVI mode). No change of behaviour intended. Refactor FAM10 fidvid . prep_fid_change was already long and it'd get longer with forthcoming patches. We now take apart F3xDC[NbsynPtrAdj], Northbridge/core synchronization FIFO pointer adjust, to its own function. Signed-off-by: Xavi Drudis Ferran <xdrudis@tinet.cat> Acked-by: Marc Jones <marcj303@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6390 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-02-27Prepare for next patches (Improving BKDG implementation of P-states,Xavi Drudis Ferran
CPU and northbridge frequency and voltage handling for Fam 10 in SVI mode). No change of behaviour intended. Refactor FAM10 fidvid . prep_fid_change was already long and it'd get longer with forthcoming patches. We now take apart F3xA0, Power Control Misc Register to its own function. Signed-off-by: Xavi Drudis Ferran <xdrudis@tinet.cat> Acked-by: Marc Jones <marcj303@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6389 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-02-27Prepare for next patches (Improving BKDG implementation of P-states,Xavi Drudis Ferran
CPU and northbridge frequency and voltage handling for Fam 10 in SVI mode). No change of behaviour intended. Refactor FAM10 fidvid . prep_fid_change was already long and it'd get longer with forthcoming patches. We now take apart F3xD4, Clock Power/Timing Control 0 to its own function. Signed-off-by: Xavi Drudis Ferran <xdrudis@tinet.cat> Acked-by: Marc Jones <marcj303@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6388 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-02-27Prepare for next patches (Improving BKDG implementation of P-states,Xavi Drudis Ferran
CPU and northbridge frequency and voltage handling for Fam 10 in SVI mode). No change of behaviour intended. Refactor FAM10 fidvid . prep_fid_change was already long and it'd get longer with forthcoming patches. We now take apart VSRamp in step b of 2.4.1.7 BKDG to its own function. Signed-off-by: Xavi Drudis Ferran <xdrudis@tinet.cat> Acked-by: Marc Jones <marcj303@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6387 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-02-26Make AMD Fam10h CPU microcode updates optional in Expert modeXavi Drudis Ferran
Signed-off-by: Xavi Drudis Ferran <xdrudis@tinet.cat> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6385 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-02-26It adds support for automatic PSS object generation for AMD pre fam Fh CPU. ↵Rudolf Marek
Those CPUs require a hardcoded table, which I managed to rewrite during one particularly boring flight. Too pity it is only for Opteron CPUs. Someone needs to finish the second PDF for All others Athlons and Semprons. Also it enables the FID/VID changes in SB. Jakllsch had some troubles with that too but on am2 CPU. Those bits are only documented in SB600. They arent in RRG RPR and BDG. Signed-off-by: Rudolf Marek <r.marek@asssembler.cz> Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6381 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-02-24Add compile-time defaults to some K8 CMOS options in case they're absent in CMOSJosef Kellermann
This affects the CMOS options iommu, ECC_memory, max_mem_clock, hw_scrubber, interleave_chip_selects. If they're absent in cmos.layout, a Kconfig value is used if it exists, or a hardcoded default otherwise. [Patrick: I changed the ramstage CMOS handling a bit, and dropped the reliance of hw_scrubber on ECC RAM, as it has nothing to do with it - it's the cache that's being scrubbed here.] Signed-off-by: Josef Kellermann <seppk@arcor.de> Acked-by: Patrick Georgi <patrick.georgi@secunet.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6380 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-02-14Add AMD cpu wrapper code. Patch 4 of 8.Frank Vibrans
This code provides cpu early initialization for Family 14h cpus. It is dependent on the AMD Agesa code. Signed-off-by: Frank Vibrans <frank.vibrans@amd.com> Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Acked-by: Marc Jones <marcj303@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6347 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-02-10According to AMD documentation, cache type WP should be used forScott Duplichan
execution from flash memory. Coreboot uses WB. While there is no noticeable performance difference between the two settings, use of WB can cause a problem for a jtag debugger. The attached patch changes AMD cache as ram setting for flash execution from WB to WP. Signed-off-by: Scott Duplichan <scott@notabs.org> Acked-by: Marc Jones <marcj303@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6342 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-02-10Implemented workaround for erratum 169, obsoleting erratum 131.Alexandru Gagniuc
Workaround for 131 removed. Changed workaround for erratum 110 to only include pre-revision-F processors. For details, check AMD publications: #25759 (Errata for Fam F pre-revision F processors) #33610 (Errata for Fam F revision F and later processor) Based on work and previous patches by: Rudolf Marek <r.marek@assembler.cz> Josef Kellermann <seppk@arcor.de> Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Acked-by: Patrick Georgi <patrick.georgi@secunet.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6340 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-02-10Fix a potential system hang by handling AMD Model F Erratum 89Josef Kellermann
a bit later. Signed-off-by: Josef Kellermann <seppk@arcor.de> Acked-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6339 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-01-27oops. this is weird. CAR addresses should be specified in the socket and not inStefan Reinauer
the board. I thought we did this ages ago. Also push CAR BASE further down so it won't conflict with a 32mbit flash part. Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6299 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-01-19Revert r5902 to make code more readable again. At least three people like toStefan Reinauer
have this go away again. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Rudolf Marek <r.marek@assembler.cz> Acked-by: Kevin O'Connor <kevin@koconnor.net> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6273 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-01-19Now that the VIA code is run above 1Meg (like other boards), it shouldKevin O'Connor
cache that range instead of the first 1Meg. This reduces boot time by about 1 second on epia-cn. This patch also adds a MTRRphysMaskValid bit definition. Signed-off-by: Kevin O'Connor <kevin@koconnor.net> Acked-by: Stefan Reinauer <stepan@coreboot.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6272 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-01-12drop unused filesStefan Reinauer
Signed-off-by: Stefan Reinauer <stepan@coreboot.org> Acked-by: Stefan Reinauer <stepan@coreboot.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6249 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-01-01Add AMD SB800 southbridge CIMx code.Kerry She
The main CIMx code is in a src/vendorcode directory and should not be changed with regard to coding style etc. in order to remain easily syncable with the "upstream" AMD code. Signed-off-by: Kerry She <Kerry.she@amd.com> Acked-by: Stefan Reinauer <stepan@coreboot.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6229 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-30Remove duplicated GX2 processor IIOC mode setting on CS5535 southbridge codeNils Jacobs
and fix CIS mode comments. Signed-off-by: Nils Jacobs <njacobs8@hetnet.nl> Acked-by: Stefan Reinauer <stepan@coreboot.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6225 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-26Remove dead and unused Geode GX2 codeNils Jacobs
Signed-off-by: Nils Jacobs <njacobs8@hetnet.nl> Acked-by: Patrick Georgi <patrick@georgi-clan.de> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6210 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-26Replace Geode GX2 MSR addresses for GLCP on GLIU1 with namesNils Jacobs
Signed-off-by: Nils Jacobs <njacobs8@hetnet.nl> Acked-by: Patrick Georgi <patrick@georgi-clan.de> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6209 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-26Clean up Geode GX2 comments, whitespace and coding style. Trivial.Nils Jacobs
Signed-off-by: Nils Jacobs <njacobs8@hetnet.nl> Acked-by: Patrick Georgi <patrick@georgi-clan.de> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6208 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-18SMM on AMD K8 Part 2/2Rudolf Marek
Signed-off-by: Rudolf Marek <r.marek@assembler.cz> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6202 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-18SMM for AMD K8 Part 1/2Stefan Reinauer
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6201 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-18Support Intel SCH (Poulsbo) and add iwave/iWRainbowG6 boardPatrick Georgi
which uses it. Compiles, but not boot tested lately. Many things missing (eg. SMM support, proper ACPI, ...) Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6198 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-16- Fix shortcoming in Kconfig when handling multiple "choice"sStefan Reinauer
- move some variables where they belong Signed-off-by: Stefan Reinauer <stepan@coreboot.org> Acked-by: Stefan Reinauer <stepan@coreboot.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6186 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-12fix model 106cxStefan Reinauer
Signed-off-by: Stefan Reinauer <stepan@coreboot.org> Acked-by: Stefan Reinauer <stepan@coreboot.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6168 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-11factor out cpu power management base into a separate file. And fix a bug inStefan Reinauer
model_1067x Signed-off-by: Stefan Reinauer <stepan@coreboot.org> Acked-by: Stefan Reinauer <stepan@coreboot.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6164 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-11After this has been brought up many times before, rename src/arch/i386 toStefan Reinauer
src/arch/x86. Signed-off-by: Stefan Reinauer <stepan@coreboot.org> Acked-by: Patrick Georgi <patrick@georgi-clan.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6161 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-08These empty files sneaked in from another patch and shouldn't have been ↵Tobias Diedrich
included in r6153, remove them. Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de> Acked-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6154 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-08Tobias Diedrich wrote:Tobias Diedrich
> Definitively a iasl problem, it can't even disassemble it's own > output back to something equivalent to the input file. > It seems to be generating Bytecode for the Add where it shouldn't. Here is a solution using the SSDT. Unfortunately iasl does not resolve simple arithmetic at compile time, so we can not use Add(DEFAULT_PMBASE, PCNTRL) in the Processor statement. This patch instead dynamically generates the processor statement. I can't use the speedstep generate_cpu_entries() directly since the cpu doesn't support speedstep. For now the code is in the southbridge directory, but maybe it should go into cpu/intel/ somewhere. IIRC notebook cpus of the era can already have speedstep, so it would probably be possible to pair the i82371eb with a speedstep-capable cpu... Also, I don't know if multiprocessor boards (abit bp6?) would need to be handled differently. Abuild-tested. Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6153 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-08Move "select CACHE_AS_RAM" lines from boards into CPU socket.Uwe Hermann
All K8/Fam10h boards use CAR, so move the "select CACHE_AS_RAM" into the socket directories, and remove it from the individual boards. Do the same for Intel CPUs/sockets where all boards use CAR. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Stefan Reinauer <stepan@coreboot.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6151 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-221) wraps the s3 parts of chipset code/memory init code with if ↵Rudolf Marek
CONFIG_HAVE_ACPI_RESUME == 1 getting rid of ugly define in romstage.c 2) the patch implements get_cbmem_toc in chipset specific way if defined. On Intel targets it should be unchanged. On K8T890 the the cbmem_toc is read from NVRAM. Why you ask? Because we cannot do it as on intel, because the framebuffer might be there making it hard to look for it in memory (and remember we need it so early that everying is uncached) 3) The patch removes hardcoded limits for suspend/resume save area (it was 1MB) on intel. Now it computes right numbers itself. 4) it impelements saving the memory during CAR to reserved range in sane way. First the sysinfo area (CAR data) is copied, then the rest after car is disabled (cached copy is used). I changed bit also the the copy of CAR area is now done uncached for target which I feel is more right. I think I did not change the Intel suspend/resume behaviour but best would be if someone can test it. Please note this patch was unfinished on my drive since ages and it would be very nice to get it in to prevent bit rotten it again. Now I feel it is done good way and should not break anything. I did a test with abuild and it seems fine. Signed-off-by: Rudolf Marek <r.marek@assembler.cz> Acked-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de> Acked-by: Stefan Reinauer <stepan@coreboot.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6117 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-22Printing coreboot debug messages on VGA console is pretty much useless, sinceStefan Reinauer
initializing VGA happens pretty much as the last thing before starting the payload. Hence, drop VGA console support, as we did in coreboot v3. - Drop VGA and BTEXT console support. Console is meant to be debugging only, and by the time graphics comes up 99% of the risky stuff has already happened. Note: This patch does not remove hardware init but only the actual output functionality. The ragexl driver needs some extra love, but that's for another day - factor out die() and post() - drop some leftover RAMBASE < 0x100000 checks. Signed-off-by: Stefan Reinauer <stepan@coreboot.org> Acked-by: QingPei Wang<wangqingpei@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6111 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-18Eliminate SET_NB_CFG_54 option. There was no board thatPatrick Georgi
deselected it, and very likely there won't ever be any hardware that requires it deselected. Keep the "selected" code path around, leading to no functional change. Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Acked-by: Scott Duplichan <scott@notabs.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6086 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-17Move Intel power management related defines to some central location.Patrick Georgi
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Acked-by: Patrick Georgi <patrick@georgi-clan.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6085 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-16Move the SET_FIDVID* family of configuration options to Kconfig andPatrick Georgi
make their defaults more obvious. Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Acked-by: Stefan Reinauer <stepan@coreboot.org> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6077 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-13MTRR related improvements for AMD family 10h and family 0Fh systemsScott Duplichan
-- When building for UMA, reduce the limit for DRAM below 4GB from E0000000 to C0000000. This is needed to accomodate the UMA frame buffer. -- Correct problem where msr C0010010 bits 21 and 22 (MtrrTom2En and Tom2ForceMemTypeWB) are not set consistently across cores. -- Enable TOM2 only if DRAM is present above 4GB. -- Use AMD Tom2ForceMemTypeWB feature to avoid the need for variable MTRR ranges above 4GB. -- Add above4gb flag argument to function x86_setup_var_mtrrs. Clearing this flag causes x86_setup_var_mtrrs() to omit MTRR ranges for DRAM above 4GB. AMD systems use this option to conserve MTRRs. -- Northbridge.c change to deduct UMA memory from DRAM size reported by ram_resource. This corrects a problem where mtrr.c generates an unexpected variable MTRR range. -- Correct problem causing build failure when CONFIG_GFXUMA=1 and CONFIG_VAR_MTRR_HOLE=0. -- Reserve the UMA DRAM range for AMD K8 as is already done for AMD family 10h. Tested with mahogany on ECS A780G-GM with 2GB and 4GB. Tested with mahogany_fam10 on ECS A780G-GM with 2GB and 4GB. Signed-off-by: Scott Duplichan <scott@notabs.org> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6067 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-09This fixes a FIXME in src/cpu/amd/mtrr/amd_mtrr.c and shuts up theTobias Diedrich
Linux kernel, which was previously complaining that the MTRR setup is wrong, if the cpu supports more than CONFIG_CPU_ADDR_BITS bits of address space. Shamelessly copied from Linux arch/x86/kernel/cpu/mtrr/main.c Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de> Acked-by: Scott Duplichan <scott@notabs.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6052 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-03Clean up some more comments and white space in model_gx2/cpureginit.c.Nils Jacobs
This is Abuild and boot tested. Signed-off-by: Nils Jacobs <njacobs8@hetnet.nl> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6015 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-31Fix AMD family 10h engineering sample is reported as 'thermal test kit'.Scott Duplichan
Signed-off-by: Scott Duplichan <scott@notabs.org> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6005 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-26reg is only used inside the #if clause, so declare it there. trivial.Patrick Georgi
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de> Acked-by: Patrick Georgi <patrick.georgi@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5989 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-20Now that no boards set RAMBASE < 1M, get rid of some dead code. Trivial.Myles Watson
It's probably time to reconsider moving all fam10 boards to RAMBASE = 1M. Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5977 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-19For AMD family 10h processors, msr c0010058 is always programmedScott Duplichan
for 256 buses, even if fewer are configured. This patch lets msr c0010058 programming use the configured bus count, CONFIG_MMCONF_BUS_NUMBER. Signed-off-by: Scott Duplichan <scott@notabs.org> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5976 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-19Modernize socket_754 Kconfig with CAR and address bits information.Jonathan Kollasch
Also, update the board that uses this socket to match. Signed-off-by: Jonathan Kollasch <jakllsch@kollasch.net> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5969 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-19Revision 5966 changed the end of line style of the 3 modified files. This ↵Scott Duplichan
change restores the original end of line style. Signed-off-by: Scott Duplichan <scott@notabs.org> Acked-by: Scott Duplichan <scott@notabs.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5968 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-19To reduce boot time, remove the double startup IPI and 10 ms delay from ↵Scott Duplichan
lapic_cpu_init.c. The change is currently restricted to recent model AMD processors, though it could be applied to others after successful testing. Signed-off-by: Scott Duplichan <scott@notabs.org> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5967 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-19When debug logging is enabled, a message such as '* AP 02 timed out:02010501'Scott Duplichan
is sometimes logged. The reason is that the AP first sets a completion value such as 0x13, which is what function wait_cpu_state() is waiting for. Then a short time later, the AP calls function init_fidvid_ap(). This function sets a completion value of 01. When logging is off, wait_cpu_state is fast enough to see the initial completion value for each of the APs. But with logging enabled, one or more APs may go on to complete function init_fidvid_ap, which sets the completion value to 01. While mostly harmless, the timeout does increase boot time. This patch eliminates the timeout by making function wait_cpu_state recognize 01 as an additional valid AP completion value. Signed-off-by: Scott Duplichan <scott@notabs.org> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5966 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-18update intel microcode files.Stefan Reinauer
Signed-off-by: Stefan Reinauer <stepan@coreboot.org> Acked-by: Stefan Reinauer <stepan@coreboot.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5964 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-18Make update-microcodes.sh executable.Uwe Hermann
This also has an additional benefit: I was running "sh update-microcodes.sh" previously which broke with update-microcodes.sh: 102: Bad substitution due to the script requiring /bin/bash instead of /bin/sh (uses bash-specific stuff). Running "bash update-microcodes.sh" works fine. Making the script executable in svn reduces the likelyhood of people running the script with differing shells that may not work. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5963 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-17update intel microcode update scriptStefan Reinauer
Signed-off-by: Stefan Reinauer <stepan@coreboot.org> Acked-by: Stefan Reinauer <stepan@coreboot.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5961 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-17Removes model_65x CPUIDs from model_6xx code.Keith Hui
They now have their own home at cpu/intel/model_65x. Signed-off-by: Keith Hui <buurin@gmail.com> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5960 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-16Move support for Deschutes Slot 1 CPUs (model_65x) into its own directory.Keith Hui
abuild-tested. I have no Deschutes CPUs to boot test this with. Signed-off-by: Keith Hui <buurin@gmail.com> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5954 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-15Drop unused DCACHE_RAM_BASE from intel/car/cache_as_ram.inc-using sockets.Uwe Hermann
This CAR implementation hardcodes the Cache-as-RAM base address to: 0xd0000 - CacheSize so the DCACHE_RAM_BASE is never actually used for this implementation and these sockets. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5953 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-13Move out Katmai Slot 1 CPUs (model_67x) from model_6xx to model_67x.Keith Hui
abuild-tested. Boot tested on P2B-LS. Signed-off-by: Keith Hui <buurin@gmail.com> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5950 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-13Convert all Intel i810 boards to CAR.Uwe Hermann
- Drop "select ROMCC" from the boards, as well as early_mtrr stuff. - Add "select CACHE_AS_RAM" to socket_PGA370/Kconfig, as well as the usual DCACHE_RAM_BASE and DCACHE_RAM_SIZE variables. - In socket_PGA370/Makefile.inc add: cpu_incs += $(src)/cpu/intel/car/cache_as_ram.inc - Other smaller related fixes. Abuild-tested and boot-tested on MSI MS-6178. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5949 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-12Add missing include of model_6bx for slot_1.Keith Hui
I could no longer boot my P3B-F with my Tualeron and r5938. Dies with "unknown CPU". I believe it will happen with any Slot 1 440BX boards that supports model_6bx CPUs. I need to make the change below to make it work. abuild tested. Boot tested on P2B-LS and P3B-F. Signed-off-by: Keith Hui <buurin@gmail.com> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5945 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-12We define IO_APIC_ADDR in <arch/ioapic.h>, let's use it.Uwe Hermann
As both ioapic.h and acpi.h define a macro named "NMI", rename one of them (NMI -> NMIType in acpi.h). Abuild-tested. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5943 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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