Age | Commit message (Collapse) | Author |
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The microcode is from Intel's Linux microcode file, so it's unproblematic.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3983 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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* move mainboard dependent code into a mainboard SMI handler.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3982 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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doesn't make no sense. (trivial)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3977 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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triggered by the AMD 690/SB600 targets.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3970 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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a long time ago. This will make it easier to port v2 boards forward to v3 at
some point (and other things)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3964 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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similar to what v3 does. This is required to have two source files with
the same name but in different directories. (As in, two different SuperIOs on
board, with a superio.c each)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3961 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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table to read. Otherwise you never know what you'll get from the factory BIOS. There are probably more, but these are the ones compiled into the s2895.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3959 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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K8 and Fam10+ CPUs.
What this patch does:
1. Enable SSE (to get some more registers to play with)
2. Determine CPUID, and stash it in an XMM register, and reference
value for comparison in another XMM register (mangled somewhat to
simplify inequality comparisons)
3. Add a macro jmp_if_k8, which jumps if the CPU is K8
(using an SSE compare)
4. Replace #if CAR_FAM10 sections with runtime checks using jmp_if_k8.
This is pretty mechanical work. The macro uses local labels
(1: and 2:) to prevent namespace issues
5. At one time, CPU_ADDR_BITS is used to fill a register. This is
replaced with hardcoded values for both cases, and switched
appropriately.
6. Disable SSE
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3951 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Following patch adds dynamically generated P-States infrastructure as well as
M2V-MX SE as example how to do that. It is based on AMD code and mine code for
ACPI generation.
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3947 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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M2V-MX SE as example how to do that. It is based on AMD code and mine code for
ACPI generation.
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3946 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3943 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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If high SMM memory is used (and needs to be uncached for whatever reason; it
shouldn't in my opinion), we should do it the same way.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3942 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3937 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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arguments.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3931 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/33610.pdf
if I did not made any mistake.
Works for mine CPU ;)
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3928 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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This bug was reported a long time ago by Thomas Jourdan. Thanks a lot Thomas.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3879 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3878 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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parts.
This should help to reduce the code duplication for Rudolf's K8/VIA SMM
implementation...
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Joseph Smith <joe@settoplinux.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3870 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Corey Osgood <corey.osgood@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3822 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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except get_nodes.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3818 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Corey Osgood <corey.osgood@gmail.com>
Acked-by: Corey Osgood <corey.osgood@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3817 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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duplicate strings to save some space.
Signed-off-by: Marc Jones <marcj303@yahoo.com>
Acked-by: Chris Lingard <chris@stockwith.co.uk>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3751 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3726 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3702 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Also use different console messages for copying and uncompressing, like
it's already done in similar code in other places.
Signed-off-by: Jens Rottmann <JRottmann@LiPPERTEmbedded.de>
Acked-by: Marc Jones <marc.jones@amd.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3688 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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to clean it up a bit and find justifications for every difference from
x86 and AMD CAR code. I believe this is mostly merge-ready. Although I'd
have preferred to do this for v3 first, we can fix v2 boards with this
change and then move them to v3.
Thanks to Bari Ari for getting the code to me for rewrite/review.
CONFIG_CARTEST shall not be enabled (breaks the build).
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Signed-off-by: Jason Zhao <jasonzhao@viatech.com.cn>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3634 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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code to use it. That makes the code more readable and also less
error-prone.
Abuild tested.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3624 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Michael Xie Michael.Xie@amd.com
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3585 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Integrated Processor.
Signed-off-by: Ed Swierk <eswierk@arastra.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3534 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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in a couple of occurences)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3509 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Marc Jones <marc.jones@amd.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3480 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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in a number of places.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3466 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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CONFIG_AP_IN_SIPI_WAIT flag. Newer Intel CPUs need this to operate with
multiple cores.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3465 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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* fixes a warning
* puts some debug messages to spew because they're only useful to debug CAR
* print an explicit message "Uncompressing..." instad of "Copying..." when
coreboot_ram.rom is compressed.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3463 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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(trivial)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3455 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3453 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3452 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Includes setting for most recent errata.
Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3435 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Add platform option for patch file name.
Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3434 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Peter Stuge <peter@stuge.se>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3424 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Tested by me on actual hardware.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3422 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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This doesn't save any space for me but it is the right thing to allow GCC to
optimize.
Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3266 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Peter did a nice job cleaning up my initial patch. Thanks!
Signed-off-by: Marc Jones <marc.jones@amd.com>
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Marc Jones <marc.jones@amd.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3263 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Disabling it should help performance.
Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3262 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Pstate intialization has moved to early init because it requires a warm reset.
Add CPUID setup and disable SMM access to late initialization.
Much of this code is leftover from porting from K8.
Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3252 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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initialize them.
Supports single and split plane systems. Set P0 on all cores for best performance.
All APs will be in hlt(C1).
The platform warm rest logic has been updated to alway reset for HT and FID/VID setup. It is not optional anymore.
Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3251 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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In addition, AP microcode is now updated in early initialization to support errata settings that require it.
Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3250 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Add early MSR and PCI register initialization.
This fixes many default setting as well as erratas.
Some CPU core functions were moved from the HT init and platform specific code
to the generic Fam10 CPU code.
Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3249 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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This fixes many default setting as well as erratas.
Some CPU core functions were moved from the HT init and platform specific code to the generic Fam10 CPU code.
Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3248 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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patch.
Signed-off-by: Marc Jones (marc.jones@amd.com)
Acked-by: Marc Jones (marc.jones@amd.com)
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3220 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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This field is rarely used (and not used in the LX tables).
There is not a good reason to mask off non-exclusive IRQs.
Signed-off-by: Marc Jones(marc.jones@amd.com)
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3219 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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interpret whitespace as macro argument delimiter. Since the code is
preprocessed by gcc and the tokenizer may insert whitespace, that can
fail. http://sourceware.org/bugzilla/show_bug.cgi?id=669
The same change was committed in r3044 to the AMD CAR code.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Jordan Crouse <jordan.crouse@amd.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3215 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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* simplify and improve cpuid table
* add speedstep support for VIA C7 based CPUs
* also included as many of Uwe's suggestions as possible
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3168 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Publication #33610, Revision: 3.30, February 2008.
http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/33610.pdf
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3136 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3135 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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The patch was followed by these svn commands:
svn mv targets/emulation/qemu-i386/ targets/emulation/qemu-x86
svn mv --force targets/emulation/qemu-i386/ targets/emulation/qemu-x86
svn mv --force src/mainboard/emulation/qemu-i386/
src/mainboard/emulation/qemu-x86
svn mv --force src/cpu/emulation/qemu-i386/ src/cpu/emulation/qemu-x86
Signed-off-by: Myles Watson <myles@pel.cs.byu.edu>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3093 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Due to the automatic nature of this update, I am self-acking. It worked in
abuild.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3053 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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code is changed.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3052 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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C7 bios programmer's guide explicitly states they're not necessary, and
leaves it at that. Even if they are possible and exist, we don't have
any info on it, nor any updates, so drop these unneeded references.
Signed-off-by: Corey Osgood <corey.osgood@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3048 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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interpret whitespace as macro argument delimiter. Since the code is
preprocessed by gcc and the tokenizer may insert whitespace, that can
fail. http://sourceware.org/bugzilla/show_bug.cgi?id=669
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Jordan Crouse <jordan.crouse@amd.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3044 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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For the old supported CAR sizes, the newly generated code is
equivalent, so it should be a no-brainer.
Benefits:
* a nice code size reduction
* less #ifdef clutter for Family 10h
* paranoid checks for CAR size
* clear abstractions
This has been tested by Marc Jones and Jordan Crouse.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Marc Jones <marc.jones@amd.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3043 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3040 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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No code lines affected, so svn blame will not be messed up.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3039 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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generic x86 CAR code. For the old supported CAR sizes, the newly
generated code is equivalent, so it should be a no-brainer.
Add a copyright header to the code, the header is derived from the one
found in the same piece of code in v3.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Marc Jones <marc.jones@amd.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3038 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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These are the core files for HyperTransport, DDR2 Memory, and multi-core initialization.
Signed-off-by: Marc Jones <marc.jones@amd.com>
Reviewed-by: Jordan Crouse <jordan.crouse@amd.com>
Acked-by: Myles Watson <myles@pel.cs.byu.edu>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3014 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Marc Jones <marc.jones@amd.com>
Reviewed-by: Jordan Crouse <jordan.crouse@amd.com>
Acked-by: Myles Watson <myles@pel.cs.byu.edu>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3013 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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the latest version (Rev. 3.73, October 2007) of the 'Revision Guide for
AMD Athlon 64 and AMD Opteron Processors' datasheet.
Also, add information about the CPU socket for each ID (as per datasheet).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Jordan Crouse <jordan.crouse@amd.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2989 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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and c7 init are identical, according to the datasheets, so there's no
need for another folder. As the comment says, some of these model IDs
may never be produced, but they are reserved by Via for the c7.
Signed-off-by: Corey Osgood <corey.osgood@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2948 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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This is the common style in both Linux as well as in LinuxBIOS.
Self-ack as this is pretty trivial and a similar patch was already acked.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2923 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Ethernet yet. The fixes are a board-specific fake spd_read_byte, cleaning up
comments, and just in general customizing for the 1c.
The lxraminit
change fixes a bug (&& used instead of ||), adds some debug prints which were
VERY useful debugging the alix1c, changes fatal error messages from print_debug
to print_emerg, and adds two functions:
banner, which just prints out a string with a banner, and
hcf, which print an emergency message and then pushes null bytes
into the uart forever, just to make sure that no bytes get lost
for any reason.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2899 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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make them const before putting them into the read-only segment...
(trivial)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2892 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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rodata.pci_driver" warnings are coming from? We were packing those
structures into a read-only segment, but forgot to mark them const.
Despite its size, this is a fairly trivial patch created by a simple
search/replace
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2891 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2890 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2888 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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serious issue, so I am self-acking.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2879 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Joseph Smith <joe@smittys.pointclark.net>
Acked-by: Corey Osgood <corey.osgood@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2856 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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A trivial one-liner for the CPU I happen to have. The sales docs said it's
a "G1 revision", but the Rev F code works just fine.
Signed-off-by: Torsten Duwe <duwe@lst.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2754 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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southbridges, along with the Asus MEW-VM. With this, my machine attempts to
boot linux, but does so very slowly and fails during the boot process, probably
because of the irq tables.
Signed-off-by: Corey Osgood <corey.osgood@gmail.com>
Acked-by: Joseph Smith <joe@smittys.pointclark.net>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2719 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Sven Kapferer <skapfere@rumms.uni-mannheim.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2704 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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It moves the complete naming functionality to
src/cpu/amd/model_fxx/processor_name.c.
The current code sets the processor name string twice for Rev. F CPUs.
In src/cpu/amd/model_fxx/model_fxx_init.c the function
amd_set_name_string_f is called first. Several lines later
init_processor_name is called which doesn't recognize newer CPUs and
actually programs incorrect values, thus overwriting the previously set
CPU name. For example, this resulted in identifying an Opteron 2218 as a
Turion processor.
This patch removes the amd_set_name_string_f function from
src/cpu/amd/model_fxx/model_fxx_init.c and adds support for Rev. F CPUs
to src/cpu/amd/model_fxx/processor_name.c as described in the Revision
Guide for AMD NPT Family 0Fh Processors, AMD Document ID 33610 Rev 3.00,
October 2006.
Signed-off-by: Sven Kapferer <skapfere@rumms.uni-mannheim.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2699 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Marc Jones <marc.jones@amd.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2687 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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CPU: vendor AMD device
30ff2
CPU: family 0f, model 3f, stepping 02
All I know is this makes it boot when it didn't before, YMMV.
Signed-off-by: Jeremy Jackson <jerj@coplanar.net>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2678 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2658 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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trivial fix.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2654 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Jordan Crouse <jordan.crouse@amd.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2650 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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adds a symbol to the model_lx/cache_as_ram.inc, and modifies some
files in the mainboard directory. This patch has been tested but there
is a remaining problem which I am tracking down. Expect one more patch
to "get it all working".
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2638 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2628 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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The following original authors agreed to the license:
- Ronald G. Minnich <rminnich@gmail.com>
- Indrek Kruusa <indrek.kruusa@artecdesign.ee>
- Stefan Reinauer <stepan@coresystems.de>
- Andrei Birjukov <andrei.birjukov@artecdesign.ee>
Signed-off-by: Jordan Crouse <jordan.crouse@amd.com>
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2625 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2616 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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likely break the build, since it is only a small part, but it needs to
go in at some point and doing it directory by directory makes things
easier.
Signed-off-by: Yinghai Lu <yinghai.lu at amd.com>
Signed-off-by: Ed Swierk <eswierk at arastra.com>
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ward Vandewege <ward at gnu.org>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2588 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Uwe's version of yh_rest_of_patch.patch (13.02.07 - [PATCH]
Rest of huge MCP55 patch).
I dropped a lot of stuff, like broken indenting, removed copyright messages,
and this printk_ram_* stuff (what the heck is this supposed to be)
This codebase is really a mess. Further tarball contributions without a
_CLEANED UP_ patch will be denied, especially if they are not from an up to
date svn tree.
Signed-off-by: Yinghai Lu <yinghai.lu@amd.com>
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2563 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2535 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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For cache to work the x86_setup_mtrrs() must be called.
Closes #61
Signed-off-by: Jon Dufresne <jon.dufresne@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2522 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2520 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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same format for all CHIP_NAME() entries in LinuxBIOS (Closes #20).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@linuxbios.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2490 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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serengeti_cheeatah
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2439 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2437 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2435 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Indrek Kruusa
Approved-by: Ronald G. Minnich
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2412 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Ronald G. Minnich
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2405 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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