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2009-04-13Following patch adds resume (exit from self refresh) support for AMD K8 revFRudolf Marek
CPUs. It handles both type of erratas on those CPUs. Signed-off-by: Rudolf Marek <r.marek@assembler.cz> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4102 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-13Following patch adds necessary hooks and as well the compile time checks forRudolf Marek
ACPI suspend/resume. The memory cleared now is just the coreboot memory not the low memory. Signed-off-by: Rudolf Marek <r.marek@assembler.cz> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4099 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-03drop unused variables in generic smm handler. (trivial)Stefan Reinauer
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4057 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-03drop another shadow variable (trivial)Stefan Reinauer
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4056 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-01Fix typo.Marc Jones
trivial. Signed-off-by: Marc Jones <marcj303@gmail.com> Acked-by: Marc Jones <marcj303@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4046 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-01Updated microcode for for AMD Fam10 DR-B2 and B3.Zheng Bao
Signed-off-by: Zheng Bao <zheng.bao@amd.com> Acked-by: Marc Jones <marcj303@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4045 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-01Drop CONFIG_CHIP_NAME. Those config statements in Config.lb shouldStefan Reinauer
be used unconditionally, and the names don't hurt. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4042 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-03-31fix typoStefan Reinauer
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4037 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-03-25The latest ucode patches for Family 10h:Zeng Bao
9fh for RB/BL/DA Rev C; 96h for DR Rev B. Signed-off-by: Zeng Bao <zheng.bao@amd.com> Acked-by: Marc Jones <marcj303@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4028 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-03-19fix totalimpact briq compilation. the target had a cpu specific and a mainboardStefan Reinauer
specific clock.c. Since no other target uses the same cpu, I commented out the CPU's clock.c. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4018 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-03-06Some updates for core/core duo/core2/core2 duo cpus.Stefan Reinauer
The microcode is from Intel's Linux microcode file, so it's unproblematic. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3983 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-03-06* fix a minor power state issue in the ich7 smm handlerStefan Reinauer
* move mainboard dependent code into a mainboard SMI handler. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3982 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-03-06fix a bunch of cast and type warnings and don't call the apic "nvram", thatStefan Reinauer
doesn't make no sense. (trivial) Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3977 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-03-04I just went on a bugfix frenzy and fixed all printk format warningsCarl-Daniel Hailfinger
triggered by the AMD 690/SB600 targets. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3970 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-02-28coreboot-v2: drop this ugly historic union name in v2 that was dropped in v3Stefan Reinauer
a long time ago. This will make it easier to port v2 boards forward to v3 at some point (and other things) Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3964 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-02-28With this patch the v2 build system will create a directory hierarchyStefan Reinauer
similar to what v3 does. This is required to have two source files with the same name but in different directories. (As in, two different SuperIOs on board, with a superio.c each) Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3961 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-02-27This patch makes several CMOS/NVRAM reads dependent on whether there's a ↵Myles Watson
table to read. Otherwise you never know what you'll get from the factory BIOS. There are probably more, but these are the ones compiled into the s2895. Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3959 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-02-17Unify CAR so the same compiled code does the right thing on bothPatrick Georgi
K8 and Fam10+ CPUs. What this patch does: 1. Enable SSE (to get some more registers to play with) 2. Determine CPUID, and stash it in an XMM register, and reference value for comparison in another XMM register (mangled somewhat to simplify inequality comparisons) 3. Add a macro jmp_if_k8, which jumps if the CPU is K8 (using an SSE compare) 4. Replace #if CAR_FAM10 sections with runtime checks using jmp_if_k8. This is pretty mechanical work. The macro uses local labels (1: and 2:) to prevent namespace issues 5. At one time, CPU_ADDR_BITS is used to fill a register. This is replaced with hardcoded values for both cases, and switched appropriately. 6. Disable SSE Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de> Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3951 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-02-14Bellongs to r3946 Rudolf Marek
Following patch adds dynamically generated P-States infrastructure as well as M2V-MX SE as example how to do that. It is based on AMD code and mine code for ACPI generation. Signed-off-by: Rudolf Marek <r.marek@assembler.cz> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3947 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-02-14Following patch adds dynamically generated P-States infrastructure as well asRudolf Marek
M2V-MX SE as example how to do that. It is based on AMD code and mine code for ACPI generation. Signed-off-by: Rudolf Marek <r.marek@assembler.cz> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3946 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-02-12This patch converts __FUNCTION__ to __func__, since __func__ is standard.Myles Watson
Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3943 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-02-12Fix mtrr setup for UMA architectures.Stefan Reinauer
If high SMM memory is used (and needs to be uncached for whatever reason; it shouldn't in my opinion), we should do it the same way. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3942 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-02-11Print a loud warning message if we run out of MTRRs.Carl-Daniel Hailfinger
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3937 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-02-09Remove some warnings, mainly from format strings which didn't match theMyles Watson
arguments. Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3931 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-02-03Following patch adds missing CPU names. Please checkRudolf Marek
http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/33610.pdf if I did not made any mistake. Works for mine CPU ;) Signed-off-by: Rudolf Marek <r.marek@assembler.cz> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3928 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-01-20Fix register typo for core 2 cpus (trivial)Stefan Reinauer
This bug was reported a long time ago by Thomas Jourdan. Thanks a lot Thomas. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3879 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-01-20fix compiler warnings (trivial)Stefan Reinauer
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3878 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-01-19First shot at factoring SMM code into generic parts and southbridge specificStefan Reinauer
parts. This should help to reduce the code duplication for Rudolf's K8/VIA SMM implementation... Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Joseph Smith <joe@settoplinux.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3870 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-12-19Fix a LOT of implicit function declarations before they become errors.Corey Osgood
Signed-off-by: Corey Osgood <corey.osgood@gmail.com> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3822 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-12-18This patch gets rid of all the implicit definition warnings for serengeti ↵Myles Watson
except get_nodes. Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Marc Jones <marcj303@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3818 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-12-18Add another CPUID to the Via C7's table, the one on my Jetway J7F2.Corey Osgood
Signed-off-by: Corey Osgood <corey.osgood@gmail.com> Acked-by: Corey Osgood <corey.osgood@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3817 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-11-12Add another AM2 cpuid to the name string. Also, colapse the cases for ↵Marc Jones
duplicate strings to save some space. Signed-off-by: Marc Jones <marcj303@yahoo.com> Acked-by: Chris Lingard <chris@stockwith.co.uk> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3751 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-11-03Update K8 FID/VID setup. Add support for 100MHz FIDs (revG).Marc Jones
Signed-off-by: Marc Jones <marc.jones@amd.com> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3726 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-10-29Support for Intel Core Duo and Core 2 Duo (tm) CPUs.Stefan Reinauer
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3702 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-10-22Speed up copying coreboot to ram by using "movsl" instead of "movsb".Jens Rottmann
Also use different console messages for copying and uncompressing, like it's already done in similar code in other places. Signed-off-by: Jens Rottmann <JRottmann@LiPPERTEmbedded.de> Acked-by: Marc Jones <marc.jones@amd.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3688 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-10-03Thanks to Jason Zhao we got a skeleton CAR code for VIA C7. I have triedCarl-Daniel Hailfinger
to clean it up a bit and find justifications for every difference from x86 and AMD CAR code. I believe this is mostly merge-ready. Although I'd have preferred to do this for v3 first, we can fix v2 boards with this change and then move them to v3. Thanks to Bari Ari for getting the code to me for rewrite/review. CONFIG_CARTEST shall not be enabled (breaks the build). Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Signed-off-by: Jason Zhao <jasonzhao@viatech.com.cn> Acked-by: Ronald G. Minnich <rminnich@gmail.com> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3634 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-10-01The ARRAY_SIZE macro is convenient, yet mostly unused. Switch lots ofCarl-Daniel Hailfinger
code to use it. That makes the code more readable and also less error-prone. Abuild tested. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3624 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-09-19Add AMD K8 S1G1 socket support.Michael Xie Michael.Xie
Signed-off-by: Michael Xie Michael.Xie@amd.com Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3585 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-25This patch implements support for the CPU core of the Intel EP80579Ed Swierk
Integrated Processor. Signed-off-by: Ed Swierk <eswierk@arastra.com> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3534 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-13Fix outb to 0x80 delay functions to use inb instead (fixes excessive post codesStefan Reinauer
in a couple of occurences) Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3509 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-07Clean up whitespace and comments style. (trivial)Marc Jones
Signed-off-by: Marc Jones <marc.jones@amd.com> Acked-by: Marc Jones <marc.jones@amd.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3480 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-02adapt Uncompressing.. patch for AMD code. Also replace "linxbios" by "coreboot"Stefan Reinauer
in a number of places. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3466 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-02Go back to SIPI WAIT state for those CPUS defining the newly introducedStefan Reinauer
CONFIG_AP_IN_SIPI_WAIT flag. Newer Intel CPUs need this to operate with multiple cores. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3465 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-02This patch Stefan Reinauer
* fixes a warning * puts some debug messages to spew because they're only useful to debug CAR * print an explicit message "Uncompressing..." instad of "Copying..." when coreboot_ram.rom is compressed. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3463 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-01match against all steppings of a CPU model, because these are _model_ drivers.Stefan Reinauer
(trivial) Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3455 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-01same spelling in all mtrr output.. (trivial)Stefan Reinauer
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3453 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-01drop unused code (trivial)Stefan Reinauer
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3452 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-07-23Add AMD Fam10 B3 default settings to match AMD example code.Marc Jones
Includes setting for most recent errata. Signed-off-by: Marc Jones <marc.jones@amd.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3435 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-07-23Update to the latest AMD Fam10 microcode patches.Marc Jones
Add platform option for patch file name. Signed-off-by: Marc Jones <marc.jones@amd.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3434 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-07-17Add Fam10 Gart table walk enable for MCA reporting to match AMD example code.Marc Jones
Signed-off-by: Marc Jones <marc.jones@amd.com> Acked-by: Peter Stuge <peter@stuge.se> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3424 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-07-15Add missing Intel CPU (trivial).Uwe Hermann
Tested by me on actual hardware. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3422 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-04-25Remove inline from FAM10 CPU initialization functions.Marc Jones
This doesn't save any space for me but it is the right thing to allow GCC to optimize. Signed-off-by: Marc Jones <marc.jones@amd.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3266 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-04-24Add CPUID processor name string support for Fam10 CPUs.Marc Jones
Peter did a nice job cleaning up my initial patch. Thanks! Signed-off-by: Marc Jones <marc.jones@amd.com> Signed-off-by: Peter Stuge <peter@stuge.se> Acked-by: Marc Jones <marc.jones@amd.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3263 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-04-24On APs the ClLinesToNbDis was being left enabled from CAR setup.Marc Jones
Disabling it should help performance. Signed-off-by: Marc Jones <marc.jones@amd.com> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3262 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-04-22Clean up and remove late initialization code that is no longer needed.Marc Jones
Pstate intialization has moved to early init because it requires a warm reset. Add CPUID setup and disable SMM access to late initialization. Much of this code is leftover from porting from K8. Signed-off-by: Marc Jones <marc.jones@amd.com> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3252 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-04-22Find matching settings for each CPUs FID, VID, and P-state registers and ↵Marc Jones
initialize them. Supports single and split plane systems. Set P0 on all cores for best performance. All APs will be in hlt(C1). The platform warm rest logic has been updated to alway reset for HT and FID/VID setup. It is not optional anymore. Signed-off-by: Marc Jones <marc.jones@amd.com> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3251 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-04-22Update the FAM10 microcode to current versions.Marc Jones
In addition, AP microcode is now updated in early initialization to support errata settings that require it. Signed-off-by: Marc Jones <marc.jones@amd.com> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3250 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-04-22Missed this file in the previous check-in, r3248.Marc Jones
Add early MSR and PCI register initialization. This fixes many default setting as well as erratas. Some CPU core functions were moved from the HT init and platform specific code to the generic Fam10 CPU code. Signed-off-by: Marc Jones <marc.jones@amd.com> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3249 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-04-22Add early MSR and PCI register initialization. Marc Jones
This fixes many default setting as well as erratas. Some CPU core functions were moved from the HT init and platform specific code to the generic Fam10 CPU code. Signed-off-by: Marc Jones <marc.jones@amd.com> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3248 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-04-07Re-add files I deleted by mistake in r3219. They are meant for a differentMarc Jones (marc.jones
patch. Signed-off-by: Marc Jones (marc.jones@amd.com) Acked-by: Marc Jones (marc.jones@amd.com) git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3220 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-04-07Don't check exclusive IRQ fieldin the PIR table.Marc Jones(marc.jones
This field is rarely used (and not used in the LX tables). There is not a good reason to mask off non-exclusive IRQs. Signed-off-by: Marc Jones(marc.jones@amd.com) Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3219 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-04-04Add a workaround for a bug in some binutils version which strictlyCarl-Daniel Hailfinger
interpret whitespace as macro argument delimiter. Since the code is preprocessed by gcc and the tokenizer may insert whitespace, that can fail. http://sourceware.org/bugzilla/show_bug.cgi?id=669 The same change was committed in r3044 to the AMD CAR code. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Jordan Crouse <jordan.crouse@amd.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3215 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-03-18* split model_centaur into model_c3 and model_c7Stefan Reinauer
* simplify and improve cpuid table * add speedstep support for VIA C7 based CPUs * also included as many of Uwe's suggestions as possible Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3168 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-03-13Update AMD CPU list based on Revision Guide for AMD NPT Family 0Fh Processors,Uwe Hermann
Publication #33610, Revision: 3.30, February 2008. http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/33610.pdf Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3136 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-03-12Formatting fixes, no content changes (trivial).Uwe Hermann
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3135 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-02-07Change references to qemu in Coreboot-v2 calls to qemu-x86.Myles Watson
The patch was followed by these svn commands: svn mv targets/emulation/qemu-i386/ targets/emulation/qemu-x86 svn mv --force targets/emulation/qemu-i386/ targets/emulation/qemu-x86 svn mv --force src/mainboard/emulation/qemu-i386/ src/mainboard/emulation/qemu-x86 svn mv --force src/cpu/emulation/qemu-i386/ src/cpu/emulation/qemu-x86 Signed-off-by: Myles Watson <myles@pel.cs.byu.edu> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3093 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-01-18Rename almost all occurences of LinuxBIOS to coreboot. Stefan Reinauer
Due to the automatic nature of this update, I am self-acking. It worked in abuild. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3053 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-01-18Please bear with me - another rename checkin. This qualifies as trivial, noStefan Reinauer
code is changed. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3052 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-01-12Via C3 datasheets don't make any mention of microcode updates, and theCorey Osgood
C7 bios programmer's guide explicitly states they're not necessary, and leaves it at that. Even if they are possible and exist, we don't have any info on it, nor any updates, so drop these unneeded references. Signed-off-by: Corey Osgood <corey.osgood@gmail.com> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3048 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-01-10Add a workaround for a bug in some binutils version which strictlyCarl-Daniel Hailfinger
interpret whitespace as macro argument delimiter. Since the code is preprocessed by gcc and the tokenizer may insert whitespace, that can fail. http://sourceware.org/bugzilla/show_bug.cgi?id=669 Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Jordan Crouse <jordan.crouse@amd.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3044 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-01-10This patch introduces 4k CAR size granularity for the AMD x86 CAR code.Carl-Daniel Hailfinger
For the old supported CAR sizes, the newly generated code is equivalent, so it should be a no-brainer. Benefits: * a nice code size reduction * less #ifdef clutter for Family 10h * paranoid checks for CAR size * clear abstractions This has been tested by Marc Jones and Jordan Crouse. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Marc Jones <marc.jones@amd.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3043 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-01-08Fix compilation of Tyan S2735 which was broken by accident in r3038.Carl-Daniel Hailfinger
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3040 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-01-08Remove some DOS line endings accidentially introduced in r3014.Carl-Daniel Hailfinger
No code lines affected, so svn blame will not be messed up. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3039 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-01-08This patch is an attempt at introducing 4k CAR size granularity for theCarl-Daniel Hailfinger
generic x86 CAR code. For the old supported CAR sizes, the newly generated code is equivalent, so it should be a no-brainer. Add a copyright header to the code, the header is derived from the one found in the same piece of code in v3. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Marc Jones <marc.jones@amd.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3038 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-12-19Initial AMD Barcelona support for rev Bx.Marc Jones
These are the core files for HyperTransport, DDR2 Memory, and multi-core initialization. Signed-off-by: Marc Jones <marc.jones@amd.com> Reviewed-by: Jordan Crouse <jordan.crouse@amd.com> Acked-by: Myles Watson <myles@pel.cs.byu.edu> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3014 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-12-19Whitespace and other code cleanup in peperation for AMD Barcelona support.Marc Jones
Signed-off-by: Marc Jones <marc.jones@amd.com> Reviewed-by: Jordan Crouse <jordan.crouse@amd.com> Acked-by: Myles Watson <myles@pel.cs.byu.edu> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3013 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-11-29Update AMD CPU IDs in model_fxx_init.c with information fromUwe Hermann
the latest version (Rev. 3.73, October 2007) of the 'Revision Guide for AMD Athlon 64 and AMD Opteron Processors' datasheet. Also, add information about the CPU socket for each ID (as per datasheet). Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Jordan Crouse <jordan.crouse@amd.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2989 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-11-07This patch adds the pci ids of c7 cpus to the existing model_centaur. c3 Corey Osgood
and c7 init are identical, according to the datasheets, so there's no need for another folder. As the comment says, some of these model IDs may never be produced, but they are reserved by Via for the c7. Signed-off-by: Corey Osgood <corey.osgood@gmail.com> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2948 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-10-31Use the preferred order of 'static const' instead of 'const static'.Uwe Hermann
This is the common style in both Linux as well as in LinuxBIOS. Self-ack as this is pretty trivial and a similar patch was already acked. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2923 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-10-26This code gets us to a working linux boot on the alix1c. I have not tested Ronald G. Minnich
Ethernet yet. The fixes are a board-specific fake spd_read_byte, cleaning up comments, and just in general customizing for the 1c. The lxraminit change fixes a bug (&& used instead of ||), adds some debug prints which were VERY useful debugging the alix1c, changes fatal error messages from print_debug to print_emerg, and adds two functions: banner, which just prints out a string with a banner, and hcf, which print an emergency message and then pushes null bytes into the uart forever, just to make sure that no bytes get lost for any reason. Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2899 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-10-24analog changes for the cpu_driver structures...Stefan Reinauer
make them const before putting them into the read-only segment... (trivial) Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2892 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-10-24Ever wondered where those "setting incorrect section attributes forStefan Reinauer
rodata.pci_driver" warnings are coming from? We were packing those structures into a read-only segment, but forgot to mark them const. Despite its size, this is a fairly trivial patch created by a simple search/replace Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2891 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-10-23fix a whole bunch of warnings. (trivial)Stefan Reinauer
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2890 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-10-23Add support for the Intel mFCPGA 478 socket. (trivial)Stefan Reinauer
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2888 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-10-21Put the print in the right place. This is trivial patch but a veryRonald G. Minnich
serious issue, so I am self-acking. Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2879 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-10-15This patch adds support for the Mobile Intel Celeron CPU (Micro-FC-BGA)Joseph Smith
Signed-off-by: Joseph Smith <joe@smittys.pointclark.net> Acked-by: Corey Osgood <corey.osgood@gmail.com> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2856 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-08-30Add support for the Athlon64 x2 5000+ CPU.Torsten Duwe
A trivial one-liner for the CPU I happen to have. The sales docs said it's a "G1 revision", but the Rev F code works just fine. Signed-off-by: Torsten Duwe <duwe@lst.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2754 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-06-14This patch adds support for the Intel i82810 northbridge and various i82801xxCorey Osgood
southbridges, along with the Asus MEW-VM. With this, my machine attempts to boot linux, but does so very slowly and fails during the boot process, probably because of the irq tables. Signed-off-by: Corey Osgood <corey.osgood@gmail.com> Acked-by: Joseph Smith <joe@smittys.pointclark.net> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2719 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-05-29Use the common LinuxBIOS license header format.Uwe Hermann
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Sven Kapferer <skapfere@rumms.uni-mannheim.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2704 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-05-26This patch fixes the processor name string for Rev F. CPUs.Sven Kapferer
It moves the complete naming functionality to src/cpu/amd/model_fxx/processor_name.c. The current code sets the processor name string twice for Rev. F CPUs. In src/cpu/amd/model_fxx/model_fxx_init.c the function amd_set_name_string_f is called first. Several lines later init_processor_name is called which doesn't recognize newer CPUs and actually programs incorrect values, thus overwriting the previously set CPU name. For example, this resulted in identifying an Opteron 2218 as a Turion processor. This patch removes the amd_set_name_string_f function from src/cpu/amd/model_fxx/model_fxx_init.c and adds support for Rev. F CPUs to src/cpu/amd/model_fxx/processor_name.c as described in the Revision Guide for AMD NPT Family 0Fh Processors, AMD Document ID 33610 Rev 3.00, October 2006. Signed-off-by: Sven Kapferer <skapfere@rumms.uni-mannheim.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2699 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-05-22Add missing license headers, minor cosmetic fixes in existing headers.Uwe Hermann
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Marc Jones <marc.jones@amd.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2687 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-05-20Add additional CPU device ID:Jeremy Jackson
CPU: vendor AMD device 30ff2 CPU: family 0f, model 3f, stepping 02 All I know is this makes it boot when it didn't before, YMMV. Signed-off-by: Jeremy Jackson <jerj@coplanar.net> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2678 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-05-10This patch cleans up and clarifies Geode source code comments.Marc Jones
Signed-off-by: Marc Jones <marc.jones@amd.com> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2658 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-05-10indent is by no means as harmless as one might think ;-)Stefan Reinauer
trivial fix. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2654 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-05-10Fix the indent and whitespace to match LinuxBIOS standardsJordan Crouse
Signed-off-by: Jordan Crouse <jordan.crouse@amd.com> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2650 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-05-05This is the final patch to enable the msm800sev to build. This patchRonald G. Minnich
adds a symbol to the model_lx/cache_as_ram.inc, and modifies some files in the mainboard directory. This patch has been tested but there is a remaining problem which I am tracking down. Expect one more patch to "get it all working". Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2638 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-05-04This patch adds support for the AMD Geode LX CPU. (rediffed)Marc Jones
Signed-off-by: Marc Jones <marc.jones@amd.com> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2628 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-05-03Add missing license headers to some Geode LX related files.Jordan Crouse
The following original authors agreed to the license: - Ronald G. Minnich <rminnich@gmail.com> - Indrek Kruusa <indrek.kruusa@artecdesign.ee> - Stefan Reinauer <stepan@coresystems.de> - Andrei Birjukov <andrei.birjukov@artecdesign.ee> Signed-off-by: Jordan Crouse <jordan.crouse@amd.com> Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2625 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-04-24trivial: fix filename in comment. Stefan Reinauer
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2616 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-04-06This is part of the outstanding mcp55 commit from January 18th. It willYinghai Lu
likely break the build, since it is only a small part, but it needs to go in at some point and doing it directory by directory makes things easier. Signed-off-by: Yinghai Lu <yinghai.lu at amd.com> Signed-off-by: Ed Swierk <eswierk at arastra.com> Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Ward Vandewege <ward at gnu.org> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2588 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
generated by cgit v1.2.3 (git 2.39.1) at 2024-07-18 08:04:26 +0000