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2021-03-18cpu/x86/mp_init.c: Calculate perm_smbase from ramstage dataArthur Heymans
The data needed to compute the permanent smbase for a core, when relocating, is present in the ramstage data which the stub located at DEFAULT_SMBASE (0x30000) calls back to. There is no need to fetch this from via the stub params. Change-Id: I3894c39ec8cae3ecc46b469a0fdddcad2a8f26c4 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50763 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-18cpu/x86/smm: Move apic_id_to_cpu map to smm_stub paramsArthur Heymans
This is only consumed by the stub and not by the relocation handler or the permanent handler, so move it out of the runtime struct. Change-Id: I01ed0a412c23c8a82d88408be058a27e55d0dc4d Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50762 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-03-18cpu/x86/smm_stub.S: Drop unused module_handler parameterArthur Heymans
Change-Id: I15b433483c36cce04816e8895789997d91702484 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51530 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2021-03-18cpu/x86/smm: Move relocatable stub paramsArthur Heymans
These stub params need to be synced with the code in smm_stub.S and are consumed by both the smmloader and smmloader_v2. So it is better to have the definition located in one place. Change-Id: Ide3e0cb6dea3359fa9ae660eab627499832817c9 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50761 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-17cbfs: Replace more instances of cbfs_boot_locate() with newer APIsJulius Werner
In pursuit of the eventual goal of removing cbfs_boot_locate() (and direct rdev access) from CBFS APIs, this patch replaces all remaining "simple" uses of the function call that can easily be replaced by the newer APIs (like cbfs_load() or cbfs_map()). Some cases of cbfs_boot_locate() remain that will be more complicated to solve. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: Icd0f21e2fa49c7cc834523578b7b45b5482cb1a8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50348 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2021-03-17program_loading: Replace prog_rdev() with raw start pointer and sizeJulius Werner
Since prog_locate() was eliminated, prog_rdev() only ever represents the loaded program in memory now. Using the rdev API for this is unnecessary if we know that the "device" is always just memory. This patch changes it to be represented by a simple pointer and size. Since some code still really wants this to be an rdev, introduce a prog_chain_rdev() helper to translate back to that if necessary. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: If7c0f1c5698fa0c326e23c553ea0fe928b25d202 Reviewed-on: https://review.coreboot.org/c/coreboot/+/46483 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2021-03-11src/cpu/x86: Add helper mp_run_on_all_apsAamir Bohra
Add a helper function mp_run_on_all_aps, it allows running a given func on all APs excluding the BSP, with an added provision to run func in serial manner per AP. BUG=b:169114674 Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Change-Id: I74ee8168eb6380e346590f2575350e0a6b73856e Reviewed-on: https://review.coreboot.org/c/coreboot/+/51271 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-15src: use ARRAY_SIZE where possiblePatrick Georgi
Generated with a variant of https://coccinelle.gitlabpages.inria.fr/website/rules/array.cocci Change-Id: I083704fd48faeb6c67bba3367fbcfe554a9f7c66 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50594 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-01cpu/x86/name/name.c: Clean up includesElyes HAOUAS
Also sort includes alphabetically. Change-Id: I49615434b140601ce599b4a63aa42c82874bd0f7 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44315 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-01cpu/x86/mp_init.c: Print out the microcode revision of APsArthur Heymans
It is useful to know if MCU have been applied successfully. On the start of MP init lines similar to: "AP: slot 1 apic_id 1, MCU rev: 0x0700001d" will be printed. The example is taken from the log of an ocp/deltalake. Change-Id: Ia0a6428b41d07f87943f3aa7736b8cb457fdd15a Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49840 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-28arch/x86: Top-align .init in bootblockKyösti Mälkki
Link .init section near the end of bootblock program. It contains _start16bit, gdtptr and gdt that must be addressable from realmode, thus within top 64 KiB. Change-Id: If7b9737650362ac7cd82685cfdfaf18bd2429238 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47970 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-01-28cpu/x86: Rename __protected_start symbolKyösti Mälkki
It was confusing to have this defined while there was another symbol bootblock_protected_mode_entry that was not really used as an entry point. Change-Id: I3da07ba9c0a9fc15b1515452adfb27f963659951 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48404 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-28cpu/x86: Link entry32.incKyösti Mälkki
Change-Id: Ib475f40f950f8cc54f0e3c50a80970ba3d2b628f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47969 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-01-28cpu/x86: Link reset16.incKyösti Mälkki
Change-Id: If2caab67286cf77e37928e03be4f581070e771d8 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47968 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-28cpu/x86: Link entry16.incKyösti Mälkki
Change-Id: I78ecd15716169b58cf6696ff8c5069ac2d5038ef Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47967 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-26cpu/x86/smm: Remove unused APMC for C-state and P-stateKyösti Mälkki
Change-Id: I7a3a1b63c0ef14b1e24ecce2df66f7970e5eb669 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49892 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-01-25cpu/x86/smm: Use common APMC loggingKyösti Mälkki
Unify the debug messages on raised SMIs. Change-Id: I34eeb41d929bfb18730ac821a63bde95ef9a0b3e Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49248 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-19cpu/x86/sipi_vector.S: Fix reading MCU revisionArthur Heymans
Writing 0 to MSR IA32_BIOS_SIGN_ID before fetching this MSRs content is required. This is how things are done in cpu/intel/microcode/microcode.c. The "Intel® 64 and IA-32 Architectures Software Developer’s Manual" also recommends this: "It is recommended that this field be preloaded with 0 prior to executing CPUID" (this field being %edx). Change-Id: I24a87aff9a699ed8ab2598007c8b8562d0555ac5 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49670 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Zhang <jonzhang@fb.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2021-01-18cpu/x86/smm/smm_module_loaderv2.c: Remove repeated wordElyes HAOUAS
Change-Id: I712fca09b1618017412a3d91f81627ec876f2894 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49511 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jacob Garber <jgarber1@ualberta.ca>
2021-01-18cpu/x86/mtrr/earlymtrr.c: Remove repeated wordElyes HAOUAS
Change-Id: I7e7570ff6a4319a0cf583ae5b76e7c24f0241509 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49510 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jacob Garber <jgarber1@ualberta.ca>
2021-01-15cpu/mp_init: Fix microcode lockPatrick Rudolph
Fix C code to match comment and assembly implementation. Tested on Prodrive hermes: The microcode spinlock is no longer used. Change-Id: I21441299f538783551d4d5ba2b2e7567e152d718 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49304 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-15cpu/x86/mpinit: Serialize microcode updates for HT threadsPatrick Rudolph
This change affects Intel CPUs only. As most platforms are doing uCode update using FIT, they aren't affected by this code either. Update microcode in MP-init using a single spinlock when running on a Hyper-Threading enabled CPU on pre FIT platforms. This will slow down the MP-init boot flow. Intel SDM and various BWGs specify to use a semaphore to update microcode on one thread per core on Hyper-Threading enabled CPUs. Due to this complex code would be necessary to determine the core #ID, initializing and picking the right semaphore out of CONFIG_MAX_CPUS / 2. Instead use the existing global spinlock already present in MPinit code. Assuming that only pre-FIT platforms with Hyper-Threading enabled and at most 8 threads will ever run into this condition, the boot delay is negligible. This change is a counterproposal to the previous published patch series being much more unsophisticated. Change-Id: I27bf5177859c12e92d6ce7a2966c965d7262b472 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49303 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-01-13cpu/x86/smm: Pass GNVS with smm_module_loader v2Kyösti Mälkki
Change-Id: I9971069803a7cd1b9be0ac0cfa410b6e1fdc3eeb Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49342 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-01-12cpu/x86/sipi_vector: Simplify loop getting unique CPU numberPatrick Rudolph
Get rid of using eax and reload counter on race condition. Change-Id: Ie4b9957d8aa1f272ff1db5caf2c69d1e1f086a03 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47714 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Christian Walter <christian.walter@9elements.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-08cpu/x86/smm: Use append instead of assign for smm-c-depsFurquan Shaikh
This change uses append operation (+=) instead of assignment (:=) for smm-c-deps to ensure that any earlier assignment is not overwritten. Change-Id: Ic1d62b414cfe3f61ee2b80b026b7338faa186904 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49208 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-01-04ACPI: Final APM_CNT_GNVS_UPDATE cleanupKyösti Mälkki
All platforms moved to initialise GNVS at the time of SMM module loading. Change-Id: I31b5652a946b0d9bd1909ff8bde53b43e06e2cd9 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48699 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-04arch/x86: Pass GNVS as parameter to SMM moduleKyösti Mälkki
Change-Id: I9d7417462830443f9c96273d2cc326cbcc3b17dd Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48698 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-16arch/x86: Link gdt_init.S into bootblockKyösti Mälkki
Followup work forces gdtptr and gdt towards the top of bootblock. They need to be realmode-addressable, i.e. within top 64 KiB or same segment with .reset. Change-Id: Ib6f23b2808d0a7e0d277d00a9b0f30c49fdefdd5 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47965 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-12-16arch/x86: Clean up bootblock assemblyKyösti Mälkki
We have identical gdtptr16 and gdtptr. The reference in gdtptr_offset calculation is not accounted for when considering --gc-sections, so to support linking gdt_init.S separately add dummy use of gdtptr symbol. Realmode execution already accessed gdt that was located outside [_start16bit,_estart16bit] region. Remove latter symbol as the former was not really a start of region, but entry point symbol. With the romcc bootblock solution, entry32.inc may have been linked into romstage before, but the !ENV_BOOTBLOCK case seems obsolete now. Change-Id: I0a3f6aeb217ca4e38b936b8c9ec8b0b69732cbb9 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47964 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-12-14arch/x86: Combine bootblock linker scriptsKyösti Mälkki
Packing bootblock sections is somewhat easier to understand when these all appear in one .ld file. Change-Id: Ie8629a89fa47a28db63ecc33c631b29ac5a77448 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47597 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-12-10cpu/x86/64bit/exit32.inc: Don't invalidate cache in CARPatrick Rudolph
Change-Id: I4a4e988d38b548e1c88ffcc5f5ada2e91ff6ba91 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48178 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-12-05cpu/x86/64bit: Add code to call function in protected modePatrick Rudolph
This adds a helper function for long mode to call some code in protected mode and return back to long mode. The primary use case is to run binaries that have been compiled for protected mode, like the FSP or MRC binaries. Tested on Intel Skylake. The FSP-M runs and returns without error while coreboot runs in long mode. Change-Id: I22af2d224b546c0be9e7295330b4b6602df106d6 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48175 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-12-04cpu/x86/smm_module_loaderv2: Fix compiling for x86_64Arthur Heymans
Change-Id: I9288ede88f822ff78dd9cb91020451dc935203a0 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48263 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Christian Walter <christian.walter@9elements.com>
2020-12-04cpu/x86/lapic/secondary.S: Adapt for x86_64Arthur Heymans
Adapt the old lapic init code for x86_64. Change-Id: I5128ed574323025e927137870fb10b23d06bc01d Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48221 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-12-02cpu/x86/smm/smm_stub: Fix stack canary on x86_64Patrick Rudolph
On x86_64 the cannary is 8 bytes in size, so write the additional 4 bytes to make SMM handler happy. Tested on Intel Skylake in long mode. No longer dies in SMM. Change-Id: Id805c65717ec22f413803c21928d070602522b2c Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48215 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-02cpu/x86/smm/smm_stub: Fix GDT for x86_64Patrick Rudolph
The previous code was crashing when jumping back to ramstage, now it works. The GDT is now using the same values as the other ones in coreboot. Change-Id: Id00467d9d8a4138ddea73adbda4b39f12def583f Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48214 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-01cpu/x86/early_reset: Mark assemblycode as 32bitPatrick Rudolph
Allows to compile the file under x86_64 without errors. The caller has to make sure to call the functions while in protected mode, which is usually the case in early bootblock. Change-Id: Ic6601e2af57e0acc6474fc3a4297e3d2281decd6 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48165 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-12-01cpu/x86/sipi: Add x86_64 supportPatrick Rudolph
Enter long mode on secondary APs. Tested on Lenovo T410 with additional x86_64 patches. Tested on HP Z220 with additional x86_64 patches. Still boots on x86_32. Change-Id: I53eae082123d1a12cfa97ead1d87d84db4a334c0 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45187 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-11-17Revert "arch|cpu/x86: Add Kconfig option for x86 reset vector"Kyösti Mälkki
This partially reverts commit 67910db907fb3d5feacdbfaa40952a88f673795a. The symbol X86_RESET_VECTOR continues to live, for the time being, under soc/amd/picasso. Change-Id: Ib6b2cc2b17133b3207758c72a54abe80fc6356b5 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47596 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-11-16cpu/x86/smm/smm_module_loaderv2: Properly print stack_endArthur Heymans
Change-Id: I2b8c54fd3851d1c2a9f4c3c36828922067bec79f Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47071 Reviewed-by: David Hendricks <david.hendricks@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-16cpu/x86/smm/smm_module_loaderv2.c: Use more variablesArthur Heymans
Reusing the 'size' variable for a different purpose later on in the function makes the code harder to read. Change-Id: Iceb10aa40ad473b41b7da0310554725585e3c2c2 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47070 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-11-16cpu/x86/smm: Check that the stub size is < save state sizeArthur Heymans
If the stub size would be larger than the save state size, the stagger points would overlap with the stub. The check is placed in the stub placement code. The stub placement code is called twice. Once for the initial SMM relocatation and for the permanent handler in TSEG. So the check is done twice, which is not really needed. Change-Id: I253e1a7112cd8f7496cb1a826311f4dd5ccfc73a Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47069 Reviewed-by: David Hendricks <david.hendricks@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-09cpu/x86/smm: Add a common save state handlingArthur Heymans
Currently coreboot has limited use for the SMM save state. Typically the only thing needed is to get or set a few registers and to know which CPU triggered the SMI (typically via an IO write). Abstracting away different SMM save states would allow to put some SMM functionality like the SMMSTORE entry in common places. To save place platforms can select different SMM save sate ops that should be implemented. For instance AMD platforms don't need Intel SMM save state handling. Some platforms can encounter CPUs with different save states, which the code then handles at runtime by comparing the SMM save state revision which is located at the same offset for all SMM save state types. Change-Id: I4a31d05c09065543424a9010ac434dde0dfb5836 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44323 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-09cpu/x86/smm/smm.ld: Assert that CONFIG_MAX_CPUS <= 4Arthur Heymans
The SMM_ASEG code only supports up to 4 CPUs, so assert this at buildtime. Change-Id: I8ec803cd1b76f17f4dccd5c573179d542d54c277 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44322 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-11-09cpu/x86/smm/smihandler.c: Simplify smm revision handlingArthur Heymans
The ASEG smihandler bails out if an unsupported SMM save state revision is detected. Now we have code to find the SMM save state depending on the SMM save state revision so reuse this to do the same. This also increases the loglevel when bailing out of SMM due to unsupported SMM save state revision from BIOS_DEBUG to BIOS_WARNING, given that the system likely still boots but won't have a functioning smihandler. Change-Id: I57198f0c85c0f7a1fa363d3bd236c3d41b68d2f0 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45471 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-11-03cpu/x86/mp_init: Add support for x86_64Patrick Rudolph
Fix compilation on x86_64. Tested on HP Z220: * Still boots on x86_32. Change-Id: Id7190d24172803e40acaf1495ce20f3ea38016b0 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44675 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-02cpu/x86/smm: Pass smm.ld through src-to-objArthur Heymans
This allows for ccopts symbols and preprocessor to be used inside the smm.ld linker script. Change-Id: I4262c09ca52c1fca43c1c115530efe489a722c32 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44321 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-31cpu/x86/lapic: rename virtual wire mode initialization functionFelix Held
Clarify what the function does by renaming it from do_lapic_init() to lapic_virtual_wire_mode_init(). Change-Id: Ie4430bf0f6c6bf0081b6aaeace351092bcf7f4ac Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47020 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-10-30cpu/x86/sipi_vector.S: Use correct suffix for btsJacob Garber
The assembler is warning that the bts instruction is ambiguous, so use the correct suffix btsl. See also commit 693315160e (cpu/x86/sipi_vector.S: Use correct op suffix) Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Change-Id: I2eded0af1258e90926009544683b23961d99887b Reviewed-on: https://review.coreboot.org/c/coreboot/+/46928 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-10-30cpu/x86: increase timeout for CPUs to check in after 2nd SIPIJonathan Zhang
Increase timeout for CPUs to check in after 2nd SIPI completion from 10ms to 100ms. Update logging level for mp init failure cases from BIOS_DEBUG to BIOS_ERR. Without this patch, "mp initialization failure" happens on some reboots on DeltaLake server. As consequence, not all 52 cpus come up in Linux: [root@localhost ~]# lscpu ... CPU(s): 40 Also following Hardware Errors are seen: [ 4.365762] mce: [Hardware Error]: Machine check events logged [ 4.366565] mce: [Hardware Error]: CPU 0: Machine Check: 0 Bank 9: ee2000000003110a [ 4.367561] mce: [Hardware Error]: TSC 0 ADDR fe9e0000 MISC 228aa040101086 [ 4.368563] mce: [Hardware Error]: PROCESSOR 0:5065b TIME 948438164 SOCKET 0 APIC 0 microcode 700001d With this patch, no such failure is observed with 370 reboots. Signed-off-by: Tim Chu <Tim.Chu@quantatw.com> Signed-off-by: Jonathan Zhang <jonzhang@fb.com> Change-Id: Iab10f116dd4af152c24d5d8f999928c038a5b208 Reviewed-on: https://review.coreboot.org/c/coreboot/+/46898 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-27cpu/x86/mtrr: fix OVERFLOW_BEFORE_WIDENJonathan Zhang
Integer handling issues: Potentially overflowing expression "1 << size_msb" with type "int" (32 bits, signed) is evaluated using 32-bit arithmetic, and then used in a context that expects an expression of type "uint64_t" (64 bits, unsigned). Fixes: CID 1435825 and 1435826 Signed-off-by: Jonathan Zhang <jonzhang@fb.com> Change-Id: If859521b44d9ec3ea744c751501b75d24e3b69e8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/46711 Reviewed-by: Marc Jones <marc@marcjonesconsulting.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-20cpu/x86/mtrr: add support for address space higher than 16TiBJonathan Zhang
On DeltaLake server, there are following entry in MTRR address space: 0x0000201000000000 - 0x0000201000400000 size 0x00400000 type 0 In this case, the base address (with 4k granularity) cannot be held in uint32_t. This results incorrect MTRR register setup. As the consequence UEFI forum FWTS reports following critical error: Memory range 0x100000000 to 0x183fffffff (System RAM) has incorrect attribute Uncached. Change appropriate variables' data type from uint32_t to uint64_t. Add fls64() to find least significant bit set in a 64-bit word. Add fms64() to find most significant bit set in a 64-bit word. Signed-off-by: Jonathan Zhang <jonzhang@fb.com> Signed-off-by: Marc Jones <marcjones@sysproconsulting.com> Change-Id: I41bc5befcc1374c838c91b9f7c5279ea76dd67c7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/46435 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-09-29cpu/x86/smm/smihandler.c: Implement smm_get_save_state()Arthur Heymans
This will be used in common save_state handling code. Change-Id: I4cb3180ec565cee931606e8a8f55b78fdb8932ae Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44320 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-29cpu/x86/smm/smmhandler.c: Get revision using C codeArthur Heymans
This allows to remove some assembly code. Tested with QEMU Q35 to still print the revision correctly. Change-Id: I36fb0e8bb1f46806b11ef8102ce74c0d10fd3927 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44319 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-09-21src/cpu: Drop unneeded empty linesElyes HAOUAS
Change-Id: I116b15c83fcc5d69d3f80a2e6cf0fb085064d9a6 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44604 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-09-21cpu/x86/smm.h: Add function to return the SMM save state revisionArthur Heymans
Change-Id: I3e4450088adbb654050e7420956cf58ee1170a98 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44318 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-30cpu/x86/smm/smmhandler: Fix x86_64 assembly exitPatrick Rudolph
Fix an issue the assembler didn't warn about to fix a crash on real hardware. qemu didn't catch this issue either. The linker uses the same address for variables in BSS if they aren't initialized in the code. This results in %edx being set to the value of %eax, which causes an exception restoring IA32_EFER on real hardware. Tested on qemu with KVM enabled. Change-Id: Ie36a88a2a11a6d755f06eff9b119e5b9398c6dec Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44780 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-08-24Revert "cpu/x86/sipi: Add x86_64 support"Patrick Rudolph
This reverts commit 18ad7fa51f5c6560c9d7a9bcf68e9e277e37cd49. Breaks Mpinit. The log shows: SIPI module has no parameters. MP initialization failure. Change-Id: Ideed19437667124a02c0f03aa7be8dec042d0f44 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44734 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-24cpu/x86/smm/smm_module_handler: Add x86_64 supportPatrick Rudolph
Fix compilation under x86_64. Tested on HP Z220: * Still boots on x86_32. Change-Id: I2a3ac3e44a77792eabb6843673fc6d2e14fda846 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44676 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-08-24cpu/x86/sipi: Add x86_64 supportPatrick Rudolph
Enter long mode on secondary APs. Tested on Lenovo T410 with additional x86_64 patches. Tested on HP Z220 with additional x86_64 patches. Still boots on x86_32. Change-Id: I916dd8482d56c7509af9ad0d3b9c28bdc48fd0b1 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37395 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-08-19cpu/x86/64bit/exit32: Add support for ramstagePatrick Rudolph
When compiled in RAMSTAGE use the segments for ramstage. Allows to call this assembly code in ramstage to exit long mode. The next commit makes use of this. Tested on qemu: Still boots on x86_64. Change-Id: I8beb31866bd15afc206b480b1ba05df995adc402 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44504 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-08-18cpu/x86/smm/smm_stub: Add x86_64 supportPatrick Rudolph
Enable long mode in SMM handler. x86_32 isn't affected by this change. * Enter long mode * Add 64bit entry to GDT * Use x86_64 SysV ABI calling conventions for C code entry * Change smm_module_params' cpu to size_t as 'push' is native integer * Drop to protected mode after c handler NOTE: This commit does NOT introduce a new security model. It uses the same page tables as the remaining firmware does. This can be a security risk if someone is able to manipulate the page tables stored in ROM at runtime. USE FOR TESTING ONLY! Tested on Lenovo T410 with additional x86_64 patches. Change-Id: I26300492e4be62ddd5d80525022c758a019d63a1 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37392 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Eugene Myers <cedarhouse1@comcast.net>
2020-08-15cpu/x86/smm: Introduce SMM module loader version 2Rocky Phagura
Xeon-SP Skylake Scalable Processor can have 36 CPU threads (18 cores). Current coreboot SMM is unable to handle more than ~32 CPU threads. This patch introduces a version 2 of the SMM module loader which addresses this problem. Having two versions of the SMM module loader prevents any issues to current projects. Future Xeon-SP products will be using this version of the SMM loader. Subsequent patches will enable board specific functionality for Xeon-SP. The reason for moving to version 2 is the state save area begins to encroach upon the SMI handling code when more than 32 CPU threads are in the system. This can cause system hangs, reboots, etc. The second change is related to staggered entry points with simple near jumps. In the current loader, near jumps will not work because the CPU is jumping within the same code segment. In version 2, "far" address jumps are necessary therefore protected mode must be enabled first. The SMM layout and how the CPUs are staggered are documented in the code. By making the modifications above, this allows the smm module loader to expand easily as more CPU threads are added. TEST=build for Tiogapass platform under OCP mainboard. Enable the following in Kconfig. select CPU_INTEL_COMMON_SMM select SOC_INTEL_COMMON_BLOCK_SMM select SMM_TSEG select HAVE_SMI_HANDLER select ACPI_INTEL_HARDWARE_SLEEP_VALUES Debug console will show all 36 cores relocated. Further tested by generating SMI's to port 0xb2 using XDP/ITP HW debugger and ensured all cores entering and exiting SMM properly. In addition, booted to Linux 5.4 kernel and observed no issues during mp init. Change-Id: I00a23a5f2a46110536c344254868390dbb71854c Signed-off-by: Rocky Phagura <rphagura@fb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43684 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-26arch/x86: Move cpu_relax()Kyösti Mälkki
It's not related to spinlocks and the actual implementation was also guarded by CONFIG(SMP). With a single call-site in x86-specific code, empty stubs for other arch are currently not necessary. Also drop an unused included on a nearby line. Change-Id: I00439e9c1d10c943ab5e404f5d687d316768fa16 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43808 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-14src: Remove unused 'include <cpu/x86/msr.h>'Elyes HAOUAS
Found using: diff <(git grep -l '#include <cpu/x86/msr.h>' -- src/) <(git grep -l 'IA32_EFER\|EFER_\|TSC_MSR\|IA32_\|FEATURE_CONTROL_LOCK_BIT\|FEATURE_ENABLE_VMX\|SMRR_ENABLE\|CPUID_\|SGX_GLOBAL_ENABLE\|PLATFORM_INFO_SET_TDP\|SMBASE_RO_MSR\|MCG_CTL_P\|MCA_BANKS_MASK\|FAST_STRINGS_ENABLE_BIT\|SPEED_STEP_ENABLE_BIT\|ENERGY_POLICY_\|SMRR_PHYSMASK_\|MCA_STATUS_\|VMX_BASIC_HI_DUAL_MONITOR\|MC0_ADDR\|MC0_MISC\|MC0_CTL_MASK\|msr_struct\|msrinit_struct\|soc_msr_read\|soc_msr_write\|rdmsr\|wrmsr\|mca_valid\|mca_over\|mca_uc\|mca_en\|mca_miscv\|mca_addrv\|mca_pcc\|mca_idv\|mca_cecc\|mca_uecc\|mca_defd\|mca_poison\|mca_sublink\|mca_err_code\|mca_err_extcode\|MCA_ERRCODE_\|MCA_BANK_\|MCA_ERRTYPE_\|mca_err_type\|msr_set_bit\|msr_t\|msrinit_t' -- src/) |grep '<' Change-Id: I45a41e77e5269969280e9f95cfc0effe7f117a40 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41969 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-08ACPI: Add and fill gnvs_ptr for smm_runtimeKyösti Mälkki
Change-Id: I823d04a4851437b4267a60886e5ab205bb2e1b10 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42464 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-07-08cpu/x86/smm: Add support for long modePatrick Rudolph
Enable long mode in SMM handler. x86_32 isn't affected by this change. As the rsm instruction used to leave SMM doesn't restore MSR registers, drop back to protected mode after running the smi_handler and restore IA32_EFER MSR (which enables long mode support) to previous value. NOTE: This commit does NOT introduce a new security model. It uses the same page tables as the remaining firmware does. This can be a security risk if someone is able to manipulate the page tables stored in ROM at runtime. USE FOR TESTING ONLY! Tested on Qemu Q35. Change-Id: I8bba4af4688c723fc079ae905dac95f57ea956f8 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35681 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-01ACPI GNVS: Replace uses of smm_get_gnvs()Kyösti Mälkki
Change-Id: I7b657750b10f98524f011f5254e533217fe94fd8 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42849 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-06-24ACPI: Replace smm_setup_structures()Kyösti Mälkki
Except for whitespace and varying casts the codes were the same when implemented. Platforms that did not implement this are tagged with ACPI_NO_SMI_GNVS. Change-Id: I31ec85ebce03d0d472403806969f863e4ca03b6b Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42362 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-06-23src/*: Update makefiles to exclude x86 code from psp-verstageMartin Roth
The assumption up to this point was that if the system had an x86 processor, verstage would be running on the x86 processor. With running verstage on the PSP, that assumption no longer holds true, so exclude pieces of code that cause problems for verstage on the PSP. This change will add these files to verstage only if the verstage architecture is X86 - either 32 or 64 bit. BUG=b:158124527 TEST=Build and boot on Trembyle Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: I797b67394825172bd44ad1ee693a0c509289486b Reviewed-on: https://review.coreboot.org/c/coreboot/+/42062 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Eric Peers <epeers@google.com> Reviewed-by: Rob Barnes <robbarnes@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-22cpu/x86/lapic: Support x86_64 and clean up codePatrick Rudolph
Most LAPIC registers are 32bit, and thus the use of long is valid on x86_32, however it doesn't work on x86_64. * Don't use long as it is 64bit on x86_64, which breaks interrupts in QEMU and thus SeaBIOS wouldn't time out the boot menu * Get rid of unused defines * Get rid of unused atomic xchg code Tested on QEMU Q35 with x86_64 enabled: Interrupts work again. Tested on QEMU Q35 with x86_32 enabled: Interrupts are still working. Tested on Lenovo T410 with x86_64 enabled. Change-Id: Iaed1ad956d090625c7bb5cd9cf55cbae16dd82bd Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36777 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-17cpu/x86/smm: Add helper functions to verify SMM accessPatrick Rudolph
* Add a function to check if a region overlaps with SMM. * Add a function to check if a pointer points to SMM. * Document functions in Documentation/security/smm To be used to verify data accesses in SMM. Change-Id: Ia525d2bc685377f50ecf3bdcf337a4c885488213 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Signed-off-by: Christian Walter <christian.walter@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41084 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-16Revert "x86/lapic: Set EXTINT on BSP only"Angel Pons
This reverts commit aac79e0b8f4777f8a912ccdfc483755b7a4da52c. Reason for revert: This massively slows down the boot process because the LAPIC delivery mode for the APs is not set anymore. Plus, not all review comments were fully addressed, yet this got merged in anyway. Change-Id: If9bae6aae0d4d1f21b067a7d970975193c2b16d5 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42166 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-06-16x86/lapic: Set EXTINT on BSP onlyZheng Bao
When Linux is booted, the kernel reports "do_IRQ: 1.55 No irq handler for vector" So far it comes with payloads SeaBIOS and depthcharge, not with Grub. We assume Grub does something to avoid this problem. AMD bug tracker system (JIRA PLAT-21393) says the APs can not be set EXTINT delivery mode. In Intel 64 and IA-32 Architectures Software Developer’s Manual volume 3A, see chapter 10.5.1 Local Vector Table, it says: "The APIC architecture supports only one ExtINT source in a system, usually contained in the compatibility bridge. Only one processor in the system should have an LVT entry configured to use the ExtINT delivery mode." Tested on mandolin (Picasso) board, the error in dmesg is gone. The bug 153677727 has two parts. 1. Soft lockup 2. do_IRQ 1.55. The soft lockup issued has been fixed by https://review.coreboot.org/c/coreboot/+/41128 BUG=b:153677727 TEST=mandolin Change-Id: I2956dcaad87cc1466deeca703748de33390b7603 Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42219 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-16cpu/x86: Define MTRR_CAP_PRMRRKyösti Mälkki
Followups will remove remaining cases of PRMRR_SUPPORTED and SMRR_SUPPORTED in the tree. Change-Id: I7f8c7d98f5e83a45cc0787c245cdcaf8fab176d5 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42358 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-06-16arch/x86: Create helper for APM_CNT SMI triggersKyösti Mälkki
Attempts to write to APM_CNT IO port should always be guarded with a test to verify SMI handler has been installed. Immediate followup removes redundant HAVE_SMI_HANDLER tests. Change-Id: If3fb0f1a8b32076f1d9f3fea9f817dd4b093ad98 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41971 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-15arch/x86: Remove NO_FIXED_XIP_ROM_SIZEKyösti Mälkki
The variable SETUP_XIP_CACHE provides us a working alternative. Change-Id: I6e3befedbbc7967b71409640dc81a0c2a9b3e511 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41821 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-06-15arch/x86: Remove XIP_ROM_SIZEKyösti Mälkki
When adding XIP stages on x86, the -P parameter was used to pass a page size that covers the entire file to add. The same can now be achieved with --pow2page and we no longer need to define a static Konfig for the purpose. TEST: Build asus/p2b and lenovo/x60 with "--pow2page -v -v" and inspect the generated make.log files. The effective pagesize is reduced from 64kB to 16kB for asus/p2b giving more freedom for the stage placement inside CBFS. Pagesize remained at 64kB for lenovo/x60. Change-Id: I5891fa2c2bb2d44077f745619162b143d083a6d1 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41820 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Keith Hui <buurin@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-06-06src: Remove unused 'include <cpu/x86/mtrr.h>'Elyes HAOUAS
Change-Id: I3f08b9cc34582165785063580b3356135030f63e Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41782 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: David Guckian
2020-06-02cpu/x86/mtrr: add x86_setup_mtrrs_with_detect_no_above_4gb()Aaron Durbin
There's not a function that is the equivalent to x86_setup_mtrrs_with_detect() but not solving for above 4GiB. Provide x86_setup_mtrrs_with_detect_no_above_4gb() which is the equivalent to x86_setup_mtrrs_with_detect() but instructs the MTRR solver to not take into account memory above 4GiB. BUG=b:155426691 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Change-Id: Ia1b5d67d6f139aaa929e03ddbc394d57dfb949e0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41897 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-02cpu/x86/mtrr: add helper for setting multiple MTRRsAaron Durbin
Introduce concept of var_mtrr_context object for tracking and assigning MTRR values. The algorithm is lifted from postcar_loader code, but it's generalized for different type of users: setting MSRs explicitly or deferring to a particular caller's desired actions. BUG=b:155426691,b:155322763 Change-Id: Ic03b4b617196f04071093bbba4cf28d23fa482d8 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41849 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-06-02src: Remove unused '#include <cpu/x86/lapic.h>'Elyes HAOUAS
Also, replace 'lapic.h' by 'lapic_def.h' in 'soc/intel/braswell/northcluster.c'. Change-Id: I71cff43d53660dc1e5a760ac3034bcf75f93c6e7 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41489 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-28arch/x86: Remove more romcc leftoversKyösti Mälkki
The sections .rom.* were for romcc and no longer used. Some romcc comments were left behind when guards were removed. Change-Id: I060ad7af2f03c67946f9796e625c072b887280c1 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37955 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-05-18src: Remove leading blank lines from SPDX headerElyes HAOUAS
Change-Id: I8a207e30a73d10fe67c0474ff11324ae99e2cec6 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41360 Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-11treewide: Remove "this file is part of" linesPatrick Georgi
Stefan thinks they don't add value. Command used: sed -i -e '/file is part of /d' $(git grep "file is part of " |egrep ":( */\*.*\*/\$|#|;#|-- | *\* )" | cut -d: -f1 |grep -v crossgcc |grep -v gcov | grep -v /elf.h |grep -v nvramtool) The exceptions are for: - crossgcc (patch file) - gcov (imported from gcc) - elf.h (imported from GNU's libc) - nvramtool (more complicated header) The removed lines are: - fmt.Fprintln(f, "/* This file is part of the coreboot project. */") -# This file is part of a set of unofficial pre-commit hooks available -/* This file is part of coreboot */ -# This file is part of msrtool. -/* This file is part of msrtool. */ - * This file is part of ncurses, designed to be appended after curses.h.in -/* This file is part of pgtblgen. */ - * This file is part of the coreboot project. - /* This file is part of the coreboot project. */ -# This file is part of the coreboot project. -# This file is part of the coreboot project. -## This file is part of the coreboot project. --- This file is part of the coreboot project. -/* This file is part of the coreboot project */ -/* This file is part of the coreboot project. */ -;## This file is part of the coreboot project. -# This file is part of the coreboot project. It originated in the - * This file is part of the coreinfo project. -## This file is part of the coreinfo project. - * This file is part of the depthcharge project. -/* This file is part of the depthcharge project. */ -/* This file is part of the ectool project. */ - * This file is part of the GNU C Library. - * This file is part of the libpayload project. -## This file is part of the libpayload project. -/* This file is part of the Linux kernel. */ -## This file is part of the superiotool project. -/* This file is part of the superiotool project */ -/* This file is part of uio_usbdebug */ Change-Id: I82d872b3b337388c93d5f5bf704e9ee9e53ab3a9 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41194 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-09src/: Replace GPL boilerplate with SPDX headersPatrick Georgi
Used commands: perl -i -p0e 's|\/\*[\s*]*.*is free software[:;][\s*]*you[\s*]*can[\s*]*redistribute[\s*]*it[\s*]*and\/or[\s*]*modify[\s*]*it[\s*]*under[\s*]*the[\s*]*terms[\s*]*of[\s*]*the[\s*]*GNU[\s*]*General[\s*]*Public[\s*]*License[\s*]*as[\s*]*published[\s*]*by[\s*]*the[\s*]*Free[\s*]*Software[\s*]*Foundation[;,][\s*]*version[\s*]*2[\s*]*of[\s*]*the[\s*]*License.[\s*]*This[\s*]*program[\s*]*is[\s*]*distributed[\s*]*in[\s*]*the[\s*]*hope[\s*]*that[\s*]*it[\s*]*will[\s*]*be[\s*]*useful,[\s*]*but[\s*]*WITHOUT[\s*]*ANY[\s*]*WARRANTY;[\s*]*without[\s*]*even[\s*]*the[\s*]*implied[\s*]*warranty[\s*]*of[\s*]*MERCHANTABILITY[\s*]*or[\s*]*FITNESS[\s*]*FOR[\s*]*A[\s*]*PARTICULAR[\s*]*PURPOSE.[\s*]*See[\s*]*the[\s*]*GNU[\s*]*General[\s*]*Public[\s*]*License[\s*]*for[\s*]*more[\s*]*details.[\s*]*\*\/|/* SPDX-License-Identifier: GPL-2.0-only */|' $(cat filelist) perl -i -p0e 's|\/\*[\s*]*.*is[\s*]*free[\s*]*software[:;][\s*]*you[\s*]*can[\s*]*redistribute[\s*]*it[\s*]*and/or[\s*]*modify[\s*]*it[\s*]*under[\s*]*the[\s*]*terms[\s*]*of[\s*]*the[\s*]*GNU[\s*]*General[\s*]*Public[\s*]*License[\s*]*as[\s*]*published[\s*]*by[\s*]*the[\s*]*Free[\s*]*Software[\s*]*Foundation[;,][\s*]*either[\s*]*version[\s*]*2[\s*]*of[\s*]*the[\s*]*License,[\s*]*or[\s*]*.at[\s*]*your[\s*]*option.[\s*]*any[\s*]*later[\s*]*version.[\s*]*This[\s*]*program[\s*]*is[\s*]*distributed[\s*]*in[\s*]*the[\s*]*hope[\s*]*that[\s*]*it[\s*]*will[\s*]*be[\s*]*useful,[\s*]*but[\s*]*WITHOUT[\s*]*ANY[\s*]*WARRANTY;[\s*]*without[\s*]*even[\s*]*the[\s*]*implied[\s*]*warranty[\s*]*of[\s*]*MERCHANTABILITY[\s*]*or[\s*]*FITNESS[\s*]*FOR[\s*]*A[\s*]*PARTICULAR[\s*]*PURPOSE.[\s*]*See[\s*]*the[\s*]*GNU[\s*]*General[\s*]*Public[\s*]*License[\s*]*for[\s*]*more[\s*]*details.[\s*]*\*\/|/* SPDX-License-Identifier: GPL-2.0-or-later */|' $(cat filelist) perl -i -p0e 's|\/\*[\s*]*.*is[\s*#]*free[\s*#]*software[;:,][\s*#]*you[\s*#]*can[\s*#]*redistribute[\s*#]*it[\s*#]*and/or[\s*#]*modify[\s*#]*it[\s*#]*under[\s*#]*the[\s*#]*terms[\s*#]*of[\s*#]*the[\s*#]*GNU[\s*#]*General[\s*#]*Public[\s*#]*License[\s*#]*as[\s*#]*published[\s*#]*by[\s*#]*the[\s*#]*Free[\s*#]*Software[\s*#]*Foundation[;:,][\s*#]*either[\s*#]*version[\s*#]*3[\s*#]*of[\s*#]*the[\s*#]*License[;:,][\s*#]*or[\s*#]*.at[\s*#]*your[\s*#]*option.[\s*#]*any[\s*#]*later[\s*#]*version.[\s*#]*This[\s*#]*program[\s*#]*is[\s*#]*distributed[\s*#]*in[\s*#]*the[\s*#]*hope[\s*#]*that[\s*#]*it[\s*#]*will[\s*#]*be[\s*#]*useful[;:,][\s*#]*but[\s*#]*WITHOUT[\s*#]*ANY[\s*#]*WARRANTY[;:,][\s*#]*without[\s*#]*even[\s*#]*the[\s*#]*implied[\s*#]*warranty[\s*#]*of[\s*#]*MERCHANTABILITY[\s*#]*or[\s*#]*FITNESS[\s*#]*FOR[\s*#]*A[\s*#]*PARTICULAR[\s*#]*PURPOSE.[\s*#]*See[\s*#]*the[\s*#]*GNU[\s*#]*General[\s*#]*Public[\s*#]*License[\s*#]*for[\s*#]*more[\s*#]*details.[\s*]*\*\/|/* SPDX-License-Identifier: GPL-3.0-or-later */|' $(cat filelist) perl -i -p0e 's|(\#\#*)[\w]*.*is free software[:;][\#\s]*you[\#\s]*can[\#\s]*redistribute[\#\s]*it[\#\s]*and\/or[\#\s]*modify[\#\s]*it[\s\#]*under[\s \#]*the[\s\#]*terms[\s\#]*of[\s\#]*the[\s\#]*GNU[\s\#]*General[\s\#]*Public[\s\#]*License[\s\#]*as[\s\#]*published[\s\#]*by[\s\#]*the[\s\#]*Free[\s\#]*Software[\s\#]*Foundation[;,][\s\#]*version[\s\#]*2[\s\#]*of[\s\#]*the[\s\#]*License.*[\s\#]*This[\s\#]*program[\s\#]*is[\s\#]*distributed[\s\#]*in[\s\#]*the[\s\#]*hope[\s\#]*that[\s\#]*it[\s\#]*will[\#\s]*be[\#\s]*useful,[\#\s]*but[\#\s]*WITHOUT[\#\s]*ANY[\#\s]*WARRANTY;[\#\s]*without[\#\s]*even[\#\s]*the[\#\s]*implied[\#\s]*warranty[\#\s]*of[\#\s]*MERCHANTABILITY[\#\s]*or[\#\s]*FITNESS[\#\s]*FOR[\#\s]*A[\#\s]*PARTICULAR[\#\s]*PURPOSE.[\#\s]*See[\#\s]*the[\#\s]*GNU[\#\s]*General[\#\s]*Public[\#\s]*License[\#\s]*for[\#\s]*more[\#\s]*details.\s(#* *\n)*|\1 SPDX-License-Identifier: GPL-2.0-only\n\n|' $(cat filelist) perl -i -p0e 's|(\#\#*)[\w*]*.*is free software[:;][\s*]*you[\s*]*can[\s*]*redistribute[\s*]*it[\s*]*and\/or[\s*]*modify[\s*]*it[\s*]*under[\s*]*the[\s*]*terms[\s*]*of[\s*]*the[\s*]*GNU[\s*]*General[\s*]*Public[\s*]*License[\s*]*as[\s*]*published[\s*]*by[\s*]*the[\s*]*Free[\s*]*Software[\s*]*Foundation[;,][\s*]*version[\s*]*2[\s*]*of[\s*]*the[\s*]*License.[\s*]*This[\s*]*program[\s*]*is[\s*]*distributed[\s*]*in[\s*]*the[\s*]*hope[\s*]*that[\s*]*it[\s*]*will[\s*]*be[\s*]*useful,[\s*]*but[\s*]*WITHOUT[\s*]*ANY[\s*]*WARRANTY;[\s*]*without[\s*]*even[\s*]*the[\s*]*implied[\s*]*warranty[\s*]*of[\s*]*MERCHANTABILITY[\s*]*or[\s*]*FITNESS[\s*]*FOR[\s*]*A[\s*]*PARTICULAR[\s*]*PURPOSE.[\s*]*See[\s*]*the[\s*]*GNU[\s*]*General[\s*]*Public[\s*]*License[\s*]*for[\s*]*more[\s*]*details.\s(#* *\n)*|\1 SPDX-License-Identifier: GPL-2.0-only\n\n|' $(cat filelist) Change-Id: Ia01908544f4b92a2e06ea621eca548e582728280 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41178 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-08cpu/x86/mtrr: Replace GPLv2 long form headers with SPDX headerElyes HAOUAS
Change-Id: I9d97cac214f04604f956cd9eee1e281b75c93645 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41134 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-05-06treewide: replace GPLv2 long form headers with SPDX headerPatrick Georgi
This replaces GPLv2-or-later and GPLv2-only long form text with the short SPDX identifiers. Commands used: perl -i -p0e 's|/\*[*\n\t ]*This program is free software[:;].*you.*can.*redistribute.*it.*and/or.*modify.*it.*under.*the.*terms.*of.*the.*GNU.*General.*Public.*License.*as.*published.*by.*the.*Free.*Software.*Foundation[;,].*version.*2.*of.*the.*License.*or.*(at.*your.*option).*any.*later.*version.+This.*program.*is.*distributed.*in.*the.*hope.*that.*it.*will.*be.*useful,.*but.*;.*without.*even.*the.*implied.*warranty.*of.*MERCHANTABILITY.*or.*FITNESS.*FOR.*A.*PARTICULAR.*PURPOSE..*.*See.*the.*GNU.*General.*Public.*License for more details.[\n\t ]*\*/|/* SPDX-License-Identifier: GPL-2.0-or-later */|s' $(cat filelist) perl -i -p0e 's|/\*[*\n\t ]*This program is free software[:;].*you.*can.*redistribute.*it.*and/or.*modify.*it.*under.*the.*terms.*of.*the.*GNU.*General.*Public.*License.*as.*published.*by.*the.*Free.*Software.*Foundation[;,].*version.*2.+This.*program.*is.*distributed.*in.*the.*hope.*that.*it.*will.*be.*useful,.*but.*;.*without.*even.*the.*implied.*warranty.*of.*MERCHANTABILITY.*or.*FITNESS.*FOR.*A.*PARTICULAR.*PURPOSE..*.*See.*the.*GNU.*General.*Public.*License for more details.[\n\t ]*\*/|/* SPDX-License-Identifier: GPL-2.0-only */|s' $(cat filelist) perl -i -p0e 's|/\*[*\n\t ]*This program is free software[:;].*you.*can.*redistribute.*it.*and/or.*modify.*it.*under.*the.*terms.*of.*the.*GNU.*General.*Public.*License.*version.*2.*as.*published.*by.*the.*Free.*Software.*Foundation[.;,].+This.*program.*is.*distributed.*in.*the.*hope.*that.*it.*will.*be.*useful,.*but.*;.*without.*even.*the.*implied.*warranty.*of.*MERCHANTABILITY.*or.*FITNESS.*FOR.*A.*PARTICULAR.*PURPOSE..*.*See.*the.*GNU.*General.*Public.*License for more details.[\n\t ]*\*/|/* SPDX-License-Identifier: GPL-2.0-only */|s' $(cat filelist) perl -i -p0e 's|/\*[*\n\t ]*This software is licensed under.*the.*terms.*of.*the.*GNU.*General.*Public.*License.*version.*2.*as.*published.*by.*the.*Free.*Software.*Foundation,.+This.*program.*is.*distributed.*in.*the.*hope.*that.*it.*will.*be.*useful,.*but.*;.*without.*even.*the.*implied.*warranty.*of.*MERCHANTABILITY.*or.*FITNESS.*FOR.*A.*PARTICULAR.*PURPOSE..*.*See.*the.*GNU.*General.*Public.*License for more details.[\n\t ]*\*/|/* SPDX-License-Identifier: GPL-2.0-only */|s' $(cat filelist) Change-Id: I7a746088a35633c11fc7ebe86006e96458a1abf8 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41066 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2020-05-06treewide: Move "is part of the coreboot project" line in its own commentPatrick Georgi
That makes it easier to identify "license only" headers (because they are now license only) Script line used for that: perl -i -p0e 's|/\*.*\n.*This file is part of the coreboot project.*\n.*\*|/* This file is part of the coreboot project. */\n/*|' # ...filelist... Change-Id: I2280b19972e37c36d8c67a67e0320296567fa4f6 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41065 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-05-02acpi: Move ACPI table support out of arch/x86 (3/5)Furquan Shaikh
This change moves all ACPI table support in coreboot currently living under arch/x86 into common code to make it architecture independent. ACPI table generation is not really tied to any architecture and hence it makes sense to move this to its own directory. In order to make it easier to review, this change is being split into multiple CLs. This is change 3/5 which basically is generated by running the following command: $ git grep -iIl "arch/acpi" | xargs sed -i 's/arch\/acpi/acpi\/acpi/g' BUG=b:155428745 Change-Id: I16b1c45d954d6440fb9db1d3710063a47b582eae Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40938 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2020-05-02intel/stm: Drop now unneeded `num_cpus` paramEugene D Myers
Suggested by Nico Huber in CB:38766 Change-Id: Ib8a340f17a12951bc6bc67e3093046575e7b0e46 Signed-off-by: Eugene D Myers <cedarhouse@comcast.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40438 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-05-02intel/stm: Place resource list right below MSEGEugene D Myers
Suggested by Nico Huber in CB:38765. This placement makes the address calculation simpler and makes its location indepedent of the number of CPUs. As part of the change in the BIOS resource list address calculation, the `size` variable was factored out of the conditional in line 361, thus eliminating the else. Change-Id: I9ee2747474df02b0306530048bdec75e95413b5d Signed-off-by: Eugene D Myers <cedarhouse@comcast.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40437 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-01cpu/x86/mtrr/earlymtrr: Validate MTRR argumentsRaul E Rangel
The AMD64 Architecture Programmer's Manual, Volume 2: Systems Programming says the following about variable MTRRs: Variable Range Size and Alignment. The size and alignment of variable memory-ranges (MTRRs) and I/O ranges (IORRs) are restricted as follows: * The boundary on which a variable range is aligned must be equal to the range size. For example, a memory range of 16 Mbytes must be aligned on a 16-Mbyte boundary (i.e., naturally aligned). * The range size must be a power of 2 (2^n , 52 > n > 11), with a minimum allowable size of 4 Kbytes. For example, 4 Mbytes and 8 Mbytes are allowable memory range sizes, but 6 Mbytes is not allowable. Print out errors if these conditions are violated. I didn't assert since `set_var_mtrr` can be used in boot block before the serial console is enabled. BUG=b:147042464 TEST=Boot trembyle and see MTRR errors: MTRR Error: base 0xcc800000 must be aligned to size 0x1000000 Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I8b8c734c7599bd89cf9f212ed43c2dd5b2c8ba7b Reviewed-on: https://review.coreboot.org/c/coreboot/+/40762 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-01src: Remove unused 'include <cpu/x86/cache.h>'Elyes HAOUAS
Change-Id: I2bf1eb87bb5476dd77b5a56dfe8846e82d414523 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40666 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-29src/cpu/x86/mtrr/earlymtrr: Add clear_all_var_mtrrRaul E Rangel
Picasso does not define the state of variable MTRRs on boot. Add a helper function to clear all MTRRs. BUG=b:147042464 TEST=Build trembyle Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I21b887ce12849a95ddd8f1698028fb6bbfb4a7f6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40764 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-29cpu/x86/16bit/entry16.inc: Fix typos in commentRaul E Rangel
Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I89d4d9d3a4a8a7545921dabb50f33035a090ecda Reviewed-on: https://review.coreboot.org/c/coreboot/+/40696 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-04src/cpu: Use SPDX for GPL-2.0-only filesAngel Pons
Done with sed and God Lines. Only done for C-like code for now. Change-Id: I2adf28d805fe248d55a9514f74c38280c0ad9a78 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40049 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2020-03-29cpu/x86/Makefile.inc: Fix external toolchain buildArthur Heymans
The sipi_vector.S just needs to be linked as relocatable so there is no need to invoke the compiler. TEST: BUILD_TIMELESS=1 has the same hashes Change-Id: I0370f1590a70cffb48c7930f6ae85956b506b09c Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37193 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-21cpu/x86: Fix typoSubrata Banik
CIRTICAL -> CRITICAL Change-Id: Ie2c1427b197dbfebdc7f0c6ffd85f768845ff1bd Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39671 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2020-03-17src (minus soc and mainboard): Remove copyright noticesPatrick Georgi
They're listed in AUTHORS and often incorrect anyway, for example: - What's a "Copyright $year-present"? - Which incarnation of Google (Inc, LLC, ...) is the current copyright holder? - People sometimes have their editor auto-add themselves to files even though they only deleted stuff - Or they let the editor automatically update the copyright year, because why not? - Who is the copyright holder "The coreboot project Authors"? - Or "Generated Code"? Sidestep all these issues by simply not putting these notices in individual files, let's list all copyright holders in AUTHORS instead and use the git history to deal with the rest. Change-Id: I89b10076e0f4a4b3acd59160fb7abe349b228321 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39611 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-15 14:20:38 +0000