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2022-02-03cpu/x86/smm: Retype variablesArthur Heymans
Change-Id: I85750282ab274f52bc176a1ac151ef2f9e0dd15d Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58697 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2022-02-01cpu/x86/smm: Add SMM_LEGACY_ASEGKyösti Mälkki
Followup will allow use of PARALLEL_MP with SMM_ASEG so some guards need to be adjusted. Change-Id: If032ce2be4749559db0d46ab5ae422afa7666785 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61480 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-02-01cpu/x86/lapic: Drop SMM_SERIALIZED_INITIALIZATIONKyösti Mälkki
It was only evaluated on LEGACY_SMP_INIT path while model_106cx has used PARALLEL_MP for a long time. Change-Id: I90ce838f1041d55a7c77ca80e563e413ef3ff88d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61479 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-01-26src: Add missing 'void' in function definitionElyes HAOUAS
Change-Id: I7fa1f9402b177a036f08bf99c98a6191c35fa0b5 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61371 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-12-10cpu/x86/mp_init.c: Make it work for !CONFIG_SMPArthur Heymans
With very little changes this code can be used to initialize systems without SMP. The linker will remove most of the code. Change-Id: Ia0e8fdf8ed7bc2e0e4ff01be8d3e3c3cb837e6c7 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59692 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-12-06x86_64 assembly: Don't touch %gsPatrick Rudolph
With CPU_INFO_V2 enabled %gs holds the pointer to the cpu_info struct, so don't clobber it. Backup and restore %gs where possible. Fixes a crash in MPinit seen after calling FSP-S. Change-Id: If9fc999b34530de5d8b6ad27b9af25fc552e9420 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59764 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-12-06cpu/x86/mp_init.c: Fix HAVE_SMI_HANDLERArthur Heymans
Fixes commit 29c7622 ("cpu/x86/mp_init.c: Fix building with no smihandler") broke SMM init because is_smm_enable() was called before smm_enable. Rework the code a little to make it clear what codepaths are used with CONFIG_HAVE_SMI_HANDLER. TESTED: now prodrive/hermes boots again. Change-Id: If4ce0dca2f29754d131dacf2da63e946be9a7b6d Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59912 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-12-03cpu/x86/mp_init.c: Fix building with no smihandlerArthur Heymans
The build fails because smm_stub_size() tries to find a symbol that won't be present. Change-Id: I73fee3cf26c0e37cca03299c6730f7b4f1ef6685 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54754 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2021-12-01cpu/x86/mp_init.c: Fix building without an SMI_HANDLERArthur Heymans
Tested on Qemu/i440fx. The follow-up commit adds a config file to buildtest it. Change-Id: Ieeaa85691e4c4516bb51df0e87c4ecaa940810f0 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59694 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-11-29cpu/x86: Rename X86_AMD_INIT_SIPI to X86_INIT_NEED_1_SIPISubrata Banik
This patch renames X86_AMD_INIT_SIPI Kconfig to leverage the same logic (to skip 2nd SIPI and reduce delay between INIT and SIPI while perform AP initialization) even on newer Intel platform. Change-Id: I7a4e6a8b1edc6e8ba43597259bd8b2de697e4e62 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56651 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-11-03cpu/x86/Kconfig: Remove unused CPU_ADDR_BITSArthur Heymans
Change-Id: I88f62c18b814ac0ddd356944359e727d6e3bba5a Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58688 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Mariusz Szafrański <mariuszx.szafranski@intel.com>
2021-10-26src/cpu: drop CPU_X86_CACHE_HELPER and x86_enable_cache wrapper functionFelix Held
Selecting CPU_X86_CACHE_HELPER only added the x86_enable_cache wrapper function around enable_cache which additionally wrote a POST code to port 0x80 and printed a message to the console. This function was only called during multi-processor initialization in ramstage via the init function pointer in the CPU's device operations struct and was run on all cores, so the message on the console was printed once per CPU core. This patch replaces all x86_enable_cache calls by calls to enable_cache and removes the wrapper function and the Kconfig symbol CPU_X86_CACHE_HELPER which was used to only add this when the corresponding CPUs used the x86_enable_cache wrapper function. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Suggested-by: Angel Pons <th3fanbus@gmail.com> Change-Id: I5866b6bf014821ff9e3a48052a5eaf69319b003a Reviewed-on: https://review.coreboot.org/c/coreboot/+/58579 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-10-26cpu/x86/Kconfig.debug_cpu: drop HAVE_DISPLAY_MTRRS optionFelix Held
Since all x86 CPUs in tree have MTRR support, there is no need to guard the DISPLAY_MTRRS option with HAVE_DISPLAY_MTRRS. Also all x86 CPUs/SoCs have a display_mtrrs call at least somewhere in their code, so selecting the DISPLAY_MTRRS option will always have an effect. All SoCs that don't select RESET_VECTOR_IN_RAM have the postcar stage where it gets called. The two AMD SoCs that select RESET_VECTOR_IN_RAM use the FSP2 driver which contains plenty of display_mtrrs calls. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I2894689ce58e7404d9d5a894f3c288bc4016ea19 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51575 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-10-26cpu/x86: drop CPU_X86_LAPIC Kconfig optionFelix Held
All x86 CPUs in the coreboot tree have a local APIC, so the corresponding code can be unconditionally included in the build. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ifc354fb386977b0fca4caa72c03aa77a20bc348e Reviewed-on: https://review.coreboot.org/c/coreboot/+/58551 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-10-26cpu/x86: Introduce and use `CPU_X86_LAPIC`Felix Held
With using a Kconfig option to add the x86 LAPIC support code to the build, there's no need for adding the corresponding directory to subdirs in the CPU/SoC Makefile. Comparing which CPU/SoC Makefiles added (cpu/)x86/mtrr and (cpu/)x86/lapic before this and the corresponding MTRR code selection patch and having verified that all platforms added the MTRR code on that patch shows that soc/example/min86 and soc/intel/quark are the only platforms that don't end up selecting the LAPIC code. So for now the default value of CPU_X86_LAPIC is chosen as y which gets overridden to n in the Kconfig of the two SoCs mentioned above. Change-Id: I6f683ea7ba92c91117017ebc6ad063ec54902b0a Signed-off-by: Angel Pons <th3fanbus@gmail.com> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44228 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-10-26cpu/x86: Introduce `CPU_X86_CACHE_HELPER`Felix Held
There's no need for relative paths with Kconfig options. Change-Id: Ib9b9b29a158c34a30480aaabf6d0b23819d28427 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44226 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-10-25cpu,soc/x86: always include cpu/x86/mtrr on x86 CPUs/SoCsFelix Held
All x86-based CPUs and SoCs in the coreboot tree end up including the Makefile in cpu/x86/mtrr, so include this directly in the Makefile in cpu/x86 to add it for all x86 CPUs/SoCs. In the unlikely case that a new x86 CPU/SoC will be added, a CPU_X86_MTRR Kconfig option that is selected be default could be added and the new CPU/SoC without MTRR support can override this option that then will be used in the Makefile to guard adding the Makefile from the cpu/x86/mtrr sub-directory. In cpu/intel all models except model 2065X and 206AX are selcted by a socket and rely on the socket's Makefile.inc to add x86/mtrr to the subdirs, so those models don't add x86/mtrr themselves. The Intel Broadwell SoC selects CPU_INTEL_HASWELL and which added x86/mtrr to the subdirs. The Intel Xeon SP SoC directory contains two sub-folders for different versions or generations which both add x86/mtrr to the subdirs in their Makefiles. Change-Id: I743eaac99a85a5c712241ba48a320243c5a51f76 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44230 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-22cpu/x86/mp_init: move printing of failure message into mp_init_with_smmFelix Held
Each CPU/SoC checks the return value of the mp_init_with_smm and prints the same error message if it wasn't successful, so move this check and printk to mp_init_with_smm. For this the original mp_init_with_smm function gets renamed to do_mp_init_with_smm and a new mp_init_with_smm function is created which then calls do_mp_init_with_smm, prints the error if it didn't return CB_SUCCESS and passes the return value of do_mp_init_with_smm to its caller. Since no CPU/SoC code handles a mp_init_with_smm failure apart from printing a message, also add a comment at the mp_init_with_smm call sites that the code might want to handle a failure. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I181602723c204f3e43eb43302921adf7a88c81ed Reviewed-on: https://review.coreboot.org/c/coreboot/+/58498 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-10-22cpu/x86/mp_init: use cb_err as status return type in remaining functionsFelix Held
Using cb_err as return type of mp_run_on_aps, mp_run_on_all_aps, mp_run_on_all_cpus and mp_park_aps clarifies the meaning of the different return values. This patch also adds the types.h include that provides the definition of the cb_err enum and checks the return value of all 4 functions listed above against the enum values instead of either checking if it's non-zero or less than zero to handle the error case. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I4b3f03415a041d3ec9cd0e102980e53868b004b0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58494 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-10-21cpu/x86/mp_init: use cb_err as mp_init_with_smm return typeFelix Held
Using cb_err as return type clarifies the meaning of the different return values. This patch also adds the types.h include that provides the definition of the cb_err enum and checks the return value of mp_init_with_smm against the enum values instead of either checking if it's non-zero or less than zero to handle the error case. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ibcd4a9a63cc87fe176ba885ced0f00832587d492 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58491 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-21cpu/x86/mp_init: use cb_err as run_ap_work return typeFelix Held
Using cb_err as return type clarifies the meaning of the different return values. To not change the return types of mp_run_on_aps which is exposed outside of this compilation unit to keep the scope of this patch limited, the return value of run_ap_work gets translated to the int values in mp_run_on_aps. This could also be done by a cast of the run_ap_work return value to int, but an explicit translation of the return values should be clearer about what it does there. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Id346c8edf06229a929b4783498d8c6774f54a8b1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58490 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-10-21cpu/x86/mp_init: use cb_err as mp_init & bsp_do_flight_plan return typeFelix Held
Using cb_err as return type clarifies the meaning of the different return values. To not change the return types of mp_init_with_smm which is exposed outside of this compilation unit to keep the scope of this patch limited, the return value of mp_init gets translated to the int values in mp_init_with_smm. This could also be done by a cast of the mp_init return value to int, but an explicit translation of the return values should be clearer about what it does there. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I4129c1db06a877c47cca87782af965b62dcbbdc2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58489 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-10-21cpu/x86/mp_init: use cb_err as wait_for_aps return typeFelix Held
Using cb_err as return type clarifies the meaning of the different return values. Also restructure the implementation of wait_for_aps to not need a local timeout variable. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I86b8c8b0849ae130c78125b83d159147ce11914c Reviewed-on: https://review.coreboot.org/c/coreboot/+/58488 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-10-21cpu/x86/mp_init: use cb_err as apic_wait_timeout return typeFelix Held
Using cb_err as return type clarifies the meaning of the different return values. Also restructure the implementation of apic_wait_timeout to not need a local timeout variable. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I2fe32c761492d252b154d2f50f2a330cf4f412d5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58487 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-10-21cpu/x86/mp_init: use cb_err as install_permanent_handler return typeFelix Held
Using cb_err as return type clarifies the meaning of the different return values. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ifb64b5908b938bb162153433e5f744ab0b95c525 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58486 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-10-21cpu/x86/mp_init: use cb_err as install_relocation_handler return typeFelix Held
Using cb_err as return type clarifies the meaning of the different return values. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I95f36ba628c7f3ce960a8f3bda730d1c720253cc Reviewed-on: https://review.coreboot.org/c/coreboot/+/58485 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-10-21cpu/x86: Remove cpu parameter to ap_initRaul E Rangel
We now pre-populate cpu_info before jumping to the C handler. We no longer need this parameter. I moved the stack alignment closer to the actual invocation of the C handler so it's easier to reason about. BUG=b:194391185, b:179699789 TEST=Boot guybrush to OS and verify all CPUs still function Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I8997683b6613b7031784cabf7039a400f0efdea1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58147 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-10-21cpu/x86: Require CPU_INFO_V2 when selecting PARALLEL_MPRaul E Rangel
This will reduce the number of AP init paths we need to support. BUG=b:194391185, b:179699789 TEST=Boot guybrush to OS and see all CPUs initialized correctly Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I05beb591bd7b3a26b6c51c10d4ffd6f8621c12eb Reviewed-on: https://review.coreboot.org/c/coreboot/+/58146 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-10-21arch/x86,cpu/x86: Fix 64-bit CPU_INFO_V2 build errorsRaul E Rangel
There are two possible code sections where the cpu_info macros can be included: .code32 and .code64 Doing a `push %eax` while in a .code64 section will result in a compiler error. This macro manually pushes the 32-bit register onto the stack so we can share the code between 32 and 64 bit builds. We also can't implicitly dereference per_cpu_segment_selector because it's a 32-bit address. Trying to do this results in the following: E: Invalid reloc type: 11 E: Illegal use of 32bit sign extended addressing at offset 0x1b2 If we load the address first, then dereference it, we can work around the limitation. With these fixes, 64-bit builds can now use CPU_INFO_V2. BUG=b:179699789 TEST=Boot qemu 64 bit build with CPU_INFO_V2 and 4 CPUs. See AP init work as expected. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I4e72a808c9583bb2d0f697cbbd9cb9c0aa0ea2dc Reviewed-on: https://review.coreboot.org/c/coreboot/+/58232 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-10-20cpu/x86/mp_init: rework start_aps to fix X86_AMD_INIT_SIPI caseFelix Held
When CONFIG_X86_AMD_INIT_SIPI was set, the second/final SIPI that afterwards checks if all APs have checked in was skipped and if it got so far, start_aps returned CB_SUCCESS despite not having checked if all APs had checked in after the SIPI. This patch makes start_aps skip the first SIPI in the CONFIG_X86_AMD_INIT_SIPI case so we use the proper timeouts and error handling for the final and this case only SIPI and signal the caller an error when not all APs have checked in after the SIPI. A timeless build for lenovo/x230 which is a mainboard that doesn't select X86_AMD_INIT_SIPI results in identical binary, so this doesn't change the behavior of the !X86_AMD_INIT_SIPI case. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I39438229497c5d9c44dc7e247c7b2c81252b4bdb Reviewed-on: https://review.coreboot.org/c/coreboot/+/58456 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-10-20cpu/x86/mp_init: use cb_err as start_aps return typeFelix Held
Using cb_err as return type clarifies the meaning of the different return values. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Icb96f28b4d59b3d00638a43c927df80f5d1643f9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58455 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-10-20cpu/x86/mp_init: add final new line to debug messagesFelix Held
Since during AP startup it's not guaranteed that no AP console output will be printed between consecutive printk calls in send_sipi_to_aps, add a new line character to all printks to make sure to have the outputs from the APs on separate lines. For consistency also add a final new line character to the printk call in start_aps. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I3983b8a0e6b272ba5fb2a90a108d17a0c480c8b8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58454 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-10-20cpu/x86/mp_init: factor out send_sipi_to_aps functionFelix Held
Apart from the SIPI number in the debug message the two instances of the SIPI sending code in start_aps are identical, so factor it out into a new send_sipi_to_aps function. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I6a921b81fce77fbf58c7ae3b50efd8c3e6e5aef3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58453 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-10-20cpu/x86/mp_init: use types.h includeFelix Held
Using types.h as include instead of stddef.h and stdint.h will also provide commonlib/bsd/cb_err.h which will be used in follow-up patches. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I08a68dc827d60c6c9a27b3ec8b74b9c8a2c96d12 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58452 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-10-18cpu/x86/cpu_info.S: Remove ebx save/restoreRaul E Rangel
The push/pop of %ebx was only added because smm_stub saves the canary value in it. Now that we no longer use cpu_info in smm, we no longer need to save the register. BUG=b:179699789 TEST=Boot guybrush to the OS Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I554dbe016db8b1c61246c8ffc7fa252b2542ba92 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58205 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-10-18cpu/x86/smm/smm_stub: Remove cpu_infoRaul E Rangel
Now that cpu_info() is no longer used by COOP_MULTITASKING, we no longer need to set up cpu_info in SMM. When using CPU_INFO_V2, if something does manage to call cpu_info() while executing in SMM mode, the %gs segment is disabled, so it will generate an exception. BUG=b:179699789 TEST=Boot guybrush to OS with threads enabled Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Id64f32cc63082880a92dab6deb473431b2238cd0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58204 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2021-10-18arch/x86,cpu/x86,lib/thread: Remove usage of cpu_info from lib/threadRaul E Rangel
We only ever start and execute threads on the BSP. By explicitly checking to see if the CPU is the BSP we can remove the dependency on cpu_info. With this change we can in theory enable threads in all stages. BUG=b:194391185, b:179699789 TEST=Boot guybrush to OS and verify coop multithreading still works Suggested-by: Julius Werner <jwerner@chromium.org> Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Iea4622d52c36d529e100b7ea55f32c334acfdf3e Reviewed-on: https://review.coreboot.org/c/coreboot/+/58199 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-10-18cpu/x86/lapic: Drop xapic_write_atomic()Kyösti Mälkki
Remove code, which was only needed for B and C2 stepping of P54C. The linux kernel source has commentary on X86_BUG_11AP: * See if we have a good local APIC by checking for buggy Pentia, * i.e. all B steppings and the C2 stepping of P54C when using their * integrated APIC (see 11AP erratum in "Pentium Processor * Specification Update") Change-Id: Iec10335f603674bcef2e7494831cf11200795d38 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55199 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-10-17cpu/x86/lapic: Only deliver ExtINT to BSPKyösti Mälkki
ExtINT is related to external PIC mode i8259 interrupts, they should be delivered to one CPU (BSP) only. Change-Id: I78490d2cbe3d9f52e10ef2471508263fd6c146ba Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42434 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-10-15cpu/x86/lapic: Do not set read-only bits in LVTxKyösti Mälkki
The bits REMOTE_IRR and SEND_PENDING are documented as read-only, and reserved bits should not be modified either. Change-Id: I6bcb9eb990debe169340a0bfe662158b62a8f4dc Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55700 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-10-15cpu/x86/lapic: Add comment on spurious interruptKyösti Mälkki
The bit LAPIC_SPIV_ENABLE returns 0 after reset even though LAPIC has not been temporarily disabled. Change-Id: Id261bc68fe9d1b1b0e5a3ef599a8f33a686d283b Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55699 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-10-15cpu/x86/lapic: Split virtual_wire_mode_init()Kyösti Mälkki
Only the enable_lapic() part is required while doing SMP init. Also disable_lapic() must not be called if we rely on LAPIC for timer source. Change-Id: Ib5e37c1a0a91fa4e9542141aa74f1c1876fee94e Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55261 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-10-05arch/x86,cpu/x86: Introduce new method for accessing cpu_infoRaul E Rangel
There is currently a fundamental flaw in the current cpu_info() implementation. It assumes that current stack is CONFIG_STACK_SIZE aligned. This assumption breaks down when performing SMM relocation. The first step in performing SMM relocation is changing the SMBASE. This is accomplished by installing the smmstub at 0x00038000, which is the default SMM entry point. The stub is configured to set up a new stack with the size of 1 KiB (CONFIG_SMM_STUB_STACK_SIZE), and an entry point of smm_do_relocation located in RAMSTAGE RAM. This means that when smm_do_relocation is executed, it is running in SMM with a different sized stack. When cpu_info() gets called it will be using CONFIG_STACK_SIZE to calculate the location of the cpu_info struct. This results in reading random memory. Since cpu_info() has to run in multiple environments, we can't use a compile time constant to locate the cpu_info struct. This CL introduces a new way of locating cpu_info. It uses a per-cpu segment descriptor that points to a per-cpu segment that is allocated on the stack. By using a segment descriptor to point to the per-cpu data, we no longer need to calculate the location of the cpu_info struct. This has the following advantages: * Stacks no longer need to be CONFIG_STACK_SIZE aligned. * Accessing an unconfigured segment will result in an exception. This ensures no one can call cpu_info() from an unsupported environment. * Segment selectors are cleared when entering SMM and restored when leaving SMM. * There is a 1:1 mapping between cpu and cpu_info. When using COOP_MULTITASKING, a new cpu_info is currently allocated at the top of each thread's stack. This no longer needs to happen. This CL guards most of the code with CONFIG(CPU_INFO_V2). I did this so reviewers can feel more comfortable knowing most of the CL is a no-op. I would eventually like to remove most of the guards though. This CL does not touch the LEGACY_SMP_INIT code path. I don't have any way of testing it. The %gs segment was chosen over the %fs segment because it's what the linux kernel uses for per-cpu data in x86_64 mode. BUG=b:194391185, b:179699789 TEST=Boot guybrush with CPU_INFO_V2 and verify BSP and APs have correct %gs segment. Verify cpu_info looks sane. Verify booting to the OS works correctly with COOP_MULTITASKING enabled. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I79dce9597cb784acb39a96897fb3c2f2973bfd98 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57627 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Peers <epeers@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-10-05src/acpi to src/lib: Fix spelling errorsMartin Roth
These issues were found and fixed by codespell, a useful tool for finding spelling errors. Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: I5b8ecdfe75d99028fee820a2034466a8ad1c5e63 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58080 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-29arch/x86,cpu/x86: Disable the %gs and %fs segmentsRaul E Rangel
The %fs and %gs segment are typically used to implement thread local storage or cpu local storage. We don't currently use these in coreboot, so there is no reason to map them. By setting the segment index to 0, it disables the segment. If an instruction tries to read from one of these segments an exception will be raised. The end goal is to make cpu_info() use the %gs segment. This will remove the stack alignment requirements and fix smm_do_relocation. BUG=b:194391185, b:179699789 TEST=Boot guybrush to OS Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Iaa376e562acc6bd1dfffb7a23bdec82aa474c1d5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57860 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Peers <epeers@google.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-09-27arch/x86,cpu/x86: Move cpu_info initialization instructions into macroRaul E Rangel
This will help reduce duplication and make it easier to add new members to the cpu_info struct. BUG=b:194391185, b:179699789 TEST=Compare assembly of romstage and ramstage before and after Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I31f264f4bb8b605fa3cb3bfff0d9bf79224072aa Reviewed-on: https://review.coreboot.org/c/coreboot/+/57859 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-09-27cpu/x86/mp_init: add expansion for SIPI acronymFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ic182d7c551932ab6917a81568490ed18acdcd597 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57927 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-24cpu/x86/mp_init: Add comment to smm_do_relocationRaul E Rangel
It took me a while to understand the SMM set up flow. This adds a clarifying comment. BUG=b:194391185, b:179699789 TEST=None Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I9c73e416b8c583cf870e7a29b0bd7dcc99c2f5f4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57858 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2021-09-08cpu/x86/tsc: Deduplicate Makefile logicAngel Pons
The code under `cpu/x86/tsc` is only compiled in when its `Makefile.inc` is included from platform (CPU/SoC) code and the `UDELAY_TSC` Kconfig option is enabled. Include `cpu/x86/tsc/Makefile.inc` once from `cpu/x86/Makefile.inc` and drop the now-redundant inclusions from platform code. Also, deduplicate the `UDELAY_TSC` guards. Change-Id: I41e96026f37f19de954fd5985b92a08cb97876c1 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57456 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-04cpu/x86: Use MP_RUN_ON_ALL_CPUS macro instead of hardcodingSubrata Banik
This patch ensures mp_run_on_all_aps() is passing 'MP_RUN_ON_ALL_CPUS' macro rather hardcoding `0` while running `func` on all APs. Change-Id: Icd34371c0d4349e1eefe945958eda957c4794707 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57342 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-07-27cpu/x86/mp_init: don't wait between INIT and SIPI for X86_AMD_INIT_SIPIFelix Held
Since current AMD SoCs don't need some wait time between INIT and SIPI, we can skip the 10ms wait there, which improves the boot time a bit. before: CPU_CLUSTER: 0 init finished in 632 msecs after: CPU_CLUSTER: 0 init finished in 619 msecs mpinit still works on Mandolin and all CPU cores show up and are usable. This also doesn't change the binary in a timeless build for boards/SoCs that don't select X86_AMD_INIT_SIPI which I verified for lenovo/x230. BUG=b:193885336 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I1e044776f45021742a88a5e369a74383c1baaab6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56533 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-07-26arch/x86,cpu/x86/mp_init: Switch cpu_info index type to size_tRaul E Rangel
The alignment for `struct cpu_info` is wrong on x86_64. c_start.S uses the `push` instruction when setting up the cpu_info struct. This instruction will push 8 bytes but `unsigned int` is 4 bytes. By making it a `size_t` we get the correct size for both x86_32 and x86_64. BUG=b:179699789 TEST=Boot guybrush to the OS Suggested-by: Julius Werner <jwerner@chromium.org> Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I8ef311aaa8333ccf8a5b3f1f0e852bb26777671c Reviewed-on: https://review.coreboot.org/c/coreboot/+/56573 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-07-06arch/x86: Use ENV_X86_64 instead of _x86_64_Patrick Rudolph
Tested on Intel Sandybridge x86_64 and x86_32. Change-Id: I152483d24af0512c0ee4fbbe8931b7312e487ac6 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44867 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-06-25Asm code: Use NO_EARLY_BOOTBLOCK_POSTCODES to remove Asm port80sMartin Roth
Expand NO_EARLY_BOOTBLOCK_POSTCODES to all of the early assembly code in bootblock. BUG=b:191370340 TEST: Build with & without the option enabled Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: Idb4a96820d5c391fc17a0f0dcccd519d4881b78c Reviewed-on: https://review.coreboot.org/c/coreboot/+/55731 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-06-19soc/intel/common/block/smm: Add `mainboard_smi_finalize`Aseda Aboagye
This commit adds a method called `mainboard_smi_finalize` which provides a mechanism for a mainboard to execute some code as part of the finalize method in the SMM stage before SoC does its finalization. BUG=b:191189275 BRANCH=None TEST=Implement `mainboard_smi_finalize` on lalala and verify that the code executes in SMM. Signed-off-by: Aseda Aboagye <aaboagye@google.com> Change-Id: If1ee63431e3c2a5831a4656c3a361229acff3f42 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55649 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-06-16cpu/x86/mp_init: Support both xapic and x2apic with common codeArthur Heymans
Trigger mode LAPIC_INT_LEVELTRIG was only used with LAPIC_DM_INIT, specifically for (obsolete) Init Level De-assert. Level LAPIC_INT_ASSERT is required to be set for all other delivery modes other than LAPIC_DM_INIT. This reverts the two above changes that X2APIC mode support introduced to the IPI for LAPIC_DM_SMI. Change-Id: I7264f39143cc6edb7a9687d0bd763cb2703a8265 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55197 Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-15cpu/x86/Kconfig: Increase SMM stack size to 0x800 on x86_64Patrick Rudolph
In x86_64 code every function call consumes 32byte of stack with no stack local variables being used. That limits the function call depth in SMM to 32 or less. Double the stack size to prevent overwriting the stack canary as seen on HP8200 and x86_64 enabled. Change-Id: Iee202ba2ae609a474d0eb3b06f49690f33f4eda8 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55449 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-06-15treewide: Disable R_AMD64_32S relocation supportPatrick Rudolph
This fixes a hard to debug hang that could occur in any stage, but in the end it follows simple rules and is easy to fix. In long mode the 32bit displacement addressing used on 'mov' and 'lea' instructions is sign-extended. Those instructions can be found using readelf on the stage and searching for relocation type R_X86_64_32S. The sign extension is no issue when either running in protected mode or the code module and thus the address is below 2GiB. If the address is greater than 2GiB, as usually the case for code in TSEG, the higher address bits [64:32] are all set to 1 and the effective address is pointing to memory not paged. Accessing this memory will cause a page fault, which isn't handled either. To prevent such problems - disable R_AMD64_32S relocations in rmodtool - add comment explaining why it's not allowed - use the pseudo op movabs, which doesn't use 32bit displacement addressing - Print a useful error message if such a reloc is present in the code Fixes a crash in TSEG and when in long mode seen on Intel Sandybridge. Change-Id: Ia5f5a9cde7c325f67b12e3a8e9a76283cc3870a3 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55448 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-06-11cpu/x86/lapic: Replace LOCAL_APIC_ADDR referencesKyösti Mälkki
Note that there are assumptions about LAPIC MMIO location in both AMD and Intel sources in coreboot proper. Change-Id: I2c668f5f9b93d170351c00d77d003c230900e0b4 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55194 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-10cpu/x86/lapic: Drop read/write_around aliasesKyösti Mälkki
Change-Id: Ia3935524e57885ca79586f1f4612020bb05956ab Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55195 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-06-10cpu/x86/lapic: Separate stop_this_cpu()Kyösti Mälkki
Function is needed with PARALLEL_MP and excluding guard will be added to the source file. The incompatibilities with X2APIC_SUPPORT have been fixed so the exclusion is removed here too. Change-Id: I5696da4dfe98579a3b37a027966b6758f22574aa Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55193 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-06-10cpu/x86/lapic: Add wait_ipi_completion() helpersKyösti Mälkki
Change-Id: Ib9c404cb55b96dcc5639287c214c5c8f468c0529 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55192 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-10cpu/x86/lapic: Add lapic_busy() helperArthur Heymans
Change-Id: Ife127d6dc8241cccb9d52236a9152da707f0e261 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55191 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-10cpu/x86/lapic: Add lapic_send_ipi() helperArthur Heymans
Change-Id: I7207a9aadd987b4307ce8b3dd8dbfd47d0a5768e Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55190 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-10cpu/x86/lapic: Do not inline some utility functionsKyösti Mälkki
They are not __always_inline and specially enable_lapic() will become more complex to support X2APIC state changes. Change-Id: Ic180fa8b36e419aba07e1754d4bf48c9dfddb2f3 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55258 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-10cpu/x86/lapic: Add lapic_update32() helperKyösti Mälkki
Change-Id: I57c5d85d3098f9d59f26f427fe16829e4e769194 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55187 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-09cpu/x86/lapic: Add Kconfig choice LAPIC_ACCESS_MODEKyösti Mälkki
Allows compile-time optimisation on platforms that do not wish to enable runtime checking of X2APIC. Legacy lapic_cpu_init() is incompatible so there is dependency on PARALLEL_MP. Also stop_this_cpu() is incompatible, so there is dependency on !AP_IN_SIPI_WAIT. Since the code actually lacks enablement of X2APIC (apparently assuming the blob has done it) and the other small flaws pointed out in earlier reviews, X2APIC_RUNTIME is not selected per default on any platform yet. Change-Id: I8269f9639ee3e89a2c2b4178d266ba2dac46db3f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55073 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
2021-06-09cpu/x86/lapic: Drop IOAPIC testKyösti Mälkki
For the purpose of LAPIC IPI messaging it is not required to evaluate if IOAPIC is enabled. The necessary enable_lapic() will still be called as part of setup_lapic() within cpu init. Change-Id: I8b6a34e39f755452f0af63ae0ced7279747c28fc Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55251 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-06-07cpu/x86/lapic: Redo DEBUG_HALT_SELFKyösti Mälkki
Change-Id: I7e42519d5bcee95970d366fd64923de874098172 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55189 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-07cpu/x86/lapic: Declare start_cpu() staticKyösti Mälkki
This is for the !PARALLEL_MP paths. Change-Id: If4b91834a1b6de2a902ab914610ab76c1423f1e9 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55188 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-07cpu/x86/lapic: Drop parallel_cpu_init inside LEGACY_SMP_INITKyösti Mälkki
It was not used, platforms should move away from LEGACY_SMP_INIT instead of maintaining this. Change-Id: Id89ec4bb0bdc056ac328f31397e4fab02742e444 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55204 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-06-07cpu/x86: Drop Kconfig PARALLEL_CPU_INITKyösti Mälkki
Change-Id: Ibe2c24228045cbf1ed2a6b0cb0a67848cbf03019 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55203 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-07cpu/x86: Default to PARALLEL_MP selectedKyösti Mälkki
Change-Id: I9833c4f6c43b3e67f95bd465c42d7a5036dff914 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55196 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-05-30cpu/x86/smm: Fix u32 type mismatch in print statementPaul Menzel
The 64-bit compiler x86_64-linux-gnu-gcc-10 aborts the build with the format warning below: CC ramstage/cpu/x86/smm/smm_module_loader.o src/cpu/x86/smm/smm_module_loader.c:415:42: error: format '%lx' expects argument of type 'long unsigned int', but argument 4 has type 'u32' {aka 'unsigned int'} [-Werror=format=] 415 | printk(BIOS_DEBUG, "%s: stack_end = 0x%lx\n", | ~~^ | | | long unsigned int | %x 416 | __func__, stub_params->stack_top - total_stack_size); | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ | | | u32 {aka unsigned int} The size of `size_t` differs between i386-elf (32-bit) and x86_64-elf/x86_64-linux-gnu (64-bit). Unfortunately, coreboot hardcodes src/include/inttypes.h:#define PRIx32 "x" so `PRIx32` cannot be used. There use `z` as length modifier, as size_t should be always big enough to hold the value. Found-by: x86_64-linux-gnu-gcc-10 (Debian 10.2.1-6) 10.2.1 20210110 Fixes: afb7a814 ("cpu/x86/smm: Introduce SMM module loader version 2") Change-Id: Ib504bc5e5b19f62d4702b7f485522a2ee3d26685 Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54343 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-05-30cpu/x86/smm: Fix size_t type mismatch in print statementPaul Menzel
The 64-bit compiler x86_64-linux-gnu-gcc-10 aborts the build with the format warning below: CC ramstage/cpu/x86/smm/smm_module_loader.o src/cpu/x86/smm/smm_module_loader.c: In function 'smm_module_setup_stub': src/cpu/x86/smm/smm_module_loader.c:360:70: error: format '%lx' expects argument of type 'long unsigned int', but argument 5 has type 'unsigned int' [-Werror=format=] 360 | printk(BIOS_ERR, "%s: state save size: %zx : smm_entry_offset -> %lx\n", | ~~^ | | | long unsigned int | %x As `size_t` is defined as `long unsigned int` in i386-elf (32-bit), the length modifier `l` matches there. With x86_64-elf/x86_64-linux-gnu (64-bit) and `-m32` `size_t` is defined as `unsigned int` resulting in a type mismatch. So, use the correct length modifier `z` for the type `size_t`. Found-by: x86_64-linux-gnu-gcc-10 (Debian 10.2.1-6) 10.2.1 20210110 Fixes: afb7a814 ("cpu/x86/smm: Introduce SMM module loader version 2") Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Change-Id: I4172e0f4dc40437250da89b7720a5c1e5fbab709 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54342 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2021-05-30cpu/x86/smm: Fix uintptr_t type mismatches in print statementsPaul Menzel
The 64-bit compiler x86_64-linux-gnu-gcc-10 aborts the build with the format warning below: CC ramstage/cpu/x86/smm/smm_module_loader.o src/cpu/x86/smm/smm_module_loader.c: In function 'smm_create_map': src/cpu/x86/smm/smm_module_loader.c:146:19: error: format '%zx' expects argument of type 'size_t', but argument 3 has type 'uintptr_t' {aka 'long unsigned int'} [-Werror=format=] 146 | " smbase %zx entry %zx\n", | ~~^ | | | unsigned int | %lx 147 | cpus[i].smbase, cpus[i].entry); | ~~~~~~~~~~~~~~ | | | uintptr_t {aka long unsigned int} In coreboot `uintptr_t` is defined in `src/include/stdint.h`: typedef unsigned long uintptr_t; As `size_t` is defined as `long unsigned int` in i386-elf (32-bit), the length modifier `z` matches there. With x86_64-elf/x86_64-linux-gnu (64-bit) and `-m32` `size_t` is defined as `unsigned int` resulting in a type mismatch. Normally, `PRIxPTR` would need to be used as a length modifier, but as coreboot always defines `uintptr_t` to `unsigned long` (and in `src/include/inttypes.h` also defines `PRIxPTR` as `"lx"`), use the length modifier `l` to make the code more readable. Found-by: x86_64-linux-gnu-gcc-10 (Debian 10.2.1-6) 10.2.1 20210110 Fixes: afb7a814 ("cpu/x86/smm: Introduce SMM module loader version 2") Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Change-Id: I32bff397c8a033fe34390e6c1a7dfe773707a4e8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54341 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2021-05-28cpu/x86/entry16.S: Make Intel CBnT TOCTOU safeArthur Heymans
Intel CBnT (and Boot Guard) makes the chain of trust TOCTOU safe by setting up NEM (non eviction mode) in the ACM. The CBnT IBB (Initial BootBlock) therefore should not disable caching. Sidenote: the MSR macros are taken from the slimbootloader project. TESTED: ocp/Deltalake boot with and without CBnT and also a broken CBnT setup. Change-Id: Id2031e4e406655e14198e45f137ba152f8b6f567 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54010 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Christian Walter <christian.walter@9elements.com>
2021-05-18cpu/x86: Only include smm code if CONFIG_HAVE_SMI_HANDLER=yArthur Heymans
This removes the need to include this code separately on each platform. Change-Id: I3d848b1adca4921d7ffa2203348073f0a11d090e Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46380 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-05-10cpu/x86/smm: Fix typoPatrick Georgi
Change-Id: I28f262078cf7f5ec4ed707639e845710a8cc56ea Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/53926 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-05-10*x86: fix x2apic mode boot issueWonkyu Kim
Fix booting issues on google/kahlee introduced by CB:51723. Update use inital apic id in smm_stub.S to support xapic mode error. Check more bits(LAPIC_BASE_MSR BIT10 and BIT11) for x2apic mode. TEST=Boot to OS and check apicid, debug log for CPUIDs cpuid_ebx(1), cpuid_ext(0xb, 0), cpuid_edx(0xb) etc Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com> Change-Id: Ia28f60a077182c3753f6ba9fbdd141f951d39b37 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52696 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-05-05src/cpu/x86/smm: remove debug message; not thread safeRocky Phagura
This patch removes a call to console_init() and debug print message since the code is not thread safe. This prevents system hangs (soft hangs) while in SMM if user drops in a new SOC with more cores or another socket or as a result of bad configuration. Console is already initialized after the lock has been acquired so this does not affect any other functionality. Tested on DeltaLake mainboard with SMM enabled and 52 CPU threads. Change-Id: I7e8af35d1cde78b327144b6a9da528ae7870e874 Signed-off-by: Rocky Phagura <rphagura@fb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52518 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-04-29cpu/x86/mtrr: Use a Kconfig for reserving MTRRs for OSTim Wawrzynczak
Some platforms which have large amounts of RAM and also write-combining regions may decide to drop the WC regions in favor of the default when preserving MTRRs for the OS. From a data safety perspective, this is safe to do, but if, say, the graphics framebuffer is the region that is changed from WC to UC/WB, then the performance of writing to the framebuffer will decrease dramatically. Modern OSes typically use Page Attribute Tables (PAT) to determine the cacheability on a page level and usually do not touch the MTRRs. Thus, it is believed to be safe to stop reserving MTRRs for the OS, in general; PentiumII is the exception here in that OSes that still support that may still require MTRRs to be available. In any case, if the OS wants to reprogram all of the MTRRs, it is of course still free to do so (after consulting the e820 table). BUG=b:185452338 TEST=Verify MTRR programming on a brya (where `sa_add_dram_resources` was faked to think it had 32 GiB of DRAM installed) and variable MTRR map includes a WC entry for the framebuffer (and all the RAM): MTRR: default type WB/UC MTRR counts: 13/9. MTRR: UC selected as default type. MTRR: 0 base 0x0000000000000000 mask 0x00003fff80000000 type 6 MTRR: 1 base 0x0000000077000000 mask 0x00003fffff000000 type 0 MTRR: 2 base 0x0000000078000000 mask 0x00003ffff8000000 type 0 MTRR: 3 base 0x0000000090000000 mask 0x00003ffff0000000 type 1 MTRR: 4 base 0x0000000100000000 mask 0x00003fff00000000 type 6 MTRR: 5 base 0x0000000200000000 mask 0x00003ffe00000000 type 6 MTRR: 6 base 0x0000000400000000 mask 0x00003ffc00000000 type 6 MTRR: 7 base 0x0000000800000000 mask 0x00003fff80000000 type 6 MTRR: 8 base 0x000000087fc00000 mask 0x00003fffffc00000 type 0 ADL has 9 variable-range MTRRs, previously 8 of them were used, and there was no separate entry for the framebuffer, thus leaving the default MTRR in place of uncached. Change-Id: I2ae2851248c95fd516627b101ebcb36ec59c29c3 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52522 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-04-23cpu/x86: Fix control flow UNREACHABLE issueJohn Zhao
Coverity detects the control flow UNREACHABLE issue for the printk usage. This change adds rc to keep the smm_module_setup_stub function call and returns rc after printk usage. Found-by: Coverity CID 1452602 TEST=None Signed-off-by: John Zhao <john.zhao@intel.com> Change-Id: Ie3b90a8197c3b84c5a1dbca8a9ef566bef35c9ab Reviewed-on: https://review.coreboot.org/c/coreboot/+/52574 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-19cpu/x86/smm/smm_module_loaderv2.c: Rename fileArthur Heymans
As v1 was dropped, rename v2. Change-Id: I4dd51804e9391284c7624c42ad8180a14b1a4c84 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51528 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-04-19cpu/x86/smm: Drop the V1 smmloaderArthur Heymans
Change-Id: I536a104428ae86e82977f2510b9e76715398b442 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51187 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-04-19cpu/x86/smm_loaderv2: Use the permanent stack top during relocationArthur Heymans
Use the same stack location during relocation as for the permanent handler. When the number of CPUs is too large the stacks during relocation don't fit inside the default SMRAM segment at 0x30000. Currently the code would just let the CPU stack base grow downwards outside of the default SMM segment which would corrupt lower memory if S3 is implemented. Also update the comment on smm_module_setup_stub(). Change-Id: I6a0a890e8b1c2408301564c22772032cfee4d296 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51186 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-04-15*x86: Support x2apic modeWonkyu Kim
Implement x2apic mode as existing code only supports apic mode. Use info from LAPIC_BASE_MSR (LAPIC_BASE_MSR_X2APIC_MODE) to check if apic mode or x2apic mode and implement x2apic mode according to x2apic specfication. Reference: https://software.intel.com/content/www/us/en/develop/download/intel-64-architecture-x2apic-specification.html BUG=None BRANCH=None TEST=boot to OS and check apic mode cat /proc/cpuinfo | grep "apicid" ex) can see apicid bigger than 255 apicid : 256 apicid : 260 Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com> Change-Id: I0bb729b0521fb9dc38b7981014755daeaf9ca817 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51723 Reviewed-by: Ravishankar Sarawadi <ravishankar.sarawadi@intel.com> Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-24cpu/x86/smm: Fix SMM start address passingMarc Jones
This fixes an issue introduced in commit ad0116c0327f575f0af184a2f4861848a49a0e2a cpu/x86/smm_loaderv2: Remove unused variables It removed one variable that was needed to set the SMM start address that is used to set the SMM stack location. Change-Id: Iddf9f204db54f0d97a90bb423b65db2f7625217f Signed-off-by: Marc Jones <marcjones@sysproconsulting.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51721 Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-19cpu/x86/mp_init.c: Drop unnecessary preprocessor usageArthur Heymans
Change-Id: If67bcbf0c8ffbd041e2e4cab8496f4634de26552 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51185 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-03-19cpu/x86/mp_init.c: Don't overwrite the global variable per CPUArthur Heymans
Global variables are located in .bss and not on the CPU stack. Overwriting them a per CPU case is bound to cause race conditions. In this case it is even just plainly wrong. Note: This variable is set up in the get_smm_info() function. Change-Id: Iaef26fa996f7e30b6e4c4941683026b8a29a5fd1 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51184 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-03-19cpu/x86/smm_module_loaderv2.c: Remove noop stack size checkArthur Heymans
The argument provided to the function was always the same as the one computed inside the function so drop the argument. Change-Id: I14abf400dce1bd9b03e401b6619a0500a650fa0e Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51527 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-03-19cpu/x86/mp_init: Allow stub sizes larger than the save state sizeArthur Heymans
The permanent handler module argument 'save_state_size' now holds the meaning of the real save state size which is then substracted from the CPUs save state 'top' to get the save state base. TESTED with qemu Q35 on x86_64 where the stub size exceeds the AMD64 save state size. Change-Id: I55d7611a17b6d0a39aee1c56318539232a9bb781 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50770 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-03-19cpu/x86/smm_loaderv2: Remove unused variablesArthur Heymans
Remove variables that are either constants or are just assigned but not used. Change-Id: I5d291a3464f30fc5d9f4b7233bde575010275973 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50784 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-03-19cpu/x86/smm/smm_module_loaderv2.c: Constify setup_stub()Arthur Heymans
Change-Id: I6648d0710bc0ba71cfbaaf4db7a8c1f33bbc9b35 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51183 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-03-19cpu/x86/smm_module_hander: Set up a save state mapArthur Heymans
With the smm_module_loaderv2 the save state map is not linear so copy a map from ramstage into the smihandler. TESTED on QEMU q35: Both SMMLOADER V1 and V2 handle save states properly. Change-Id: I31c57b59559ad4ee98500d83969424e5345881ee Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50769 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-03-19cpu/x86/smm_loaderv2: Fix when only 1 CPU is presentArthur Heymans
Move out smm_create_map as this was not run if concurrent_save_states is 1. The cpus struct array is used in the smm_get_cpu_smbase() callback so it is necessary to create this. TEST: run qemu/q35 with -smp 1 (or no -smp argument) Change-Id: I07a98bbc9ff6dce548171ee6cd0c303db94087aa Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50783 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-19cpu/x86/smm_stub.S: Drop smm_runtime from the stubArthur Heymans
The parameters that the permanent handler requires are pushed directly to the permanent handlers relocatable module params. The paremeters that the relocation handler requires are not passed on via arguments but are copied inside the ramstage. This is ok as the relocation handler calls into ramstage. Change-Id: Ice311d05e2eb0e95122312511d83683d7f0dee58 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50767 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2021-03-19cpu/x86/smm.h: Remove smm runtime pointer from smm_loader_paramsArthur Heymans
struct smm_loader_params is a struct that is passed around in the ramstage code to set up either the relocation handler or the permanent handler. At the moment no parameters in the stub 'smm_runtime' are referenced so it can be dropped. The purpose is to drop the smm_runtime struct from the stub as it is already located in the permanent handler. Change-Id: I09c1b649b5991f55b5ccf57f22e4a3ad4c9e4f03 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50766 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-03-19cpu/x86/mp_init.c: Copy the stub parameter start32_offset into ramstageArthur Heymans
Keep a copy of start32_offset into ramstage to avoid needing to pass arguments, calling from assembly. Doing this in C code is better than assembly. Change-Id: Iac04358e377026f45293bbee03e30d792df407fd Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50765 Reviewed-by: Eugene Myers <cedarhouse1@comcast.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-19cpu/x86/smm_module_handler: Add relocatable module paramsArthur Heymans
Instead of passing on parameters from the stub to the permanent handler, add them directly to the permanent handler. The parameters in the stub will be removed in a later patch. Change-Id: Ib3bde78dd9e0c02dd1d86e03665fa9c65e3d07eb Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50764 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>