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AgeCommit message (Expand)Author
2013-03-18haswell: lapic timer supportAaron Durbin
2013-03-18haswell: Use SMM ModulesAaron Durbin
2013-03-15Google Link: Add remaining code to support native graphicsRonald G. Minnich
2013-03-14x86: SMM Module SupportAaron Durbin
2013-03-14haswell: Add initial support for Haswell platformsAaron Durbin
2013-03-08Eliminate do_div().David Hendricks
2013-03-01GPLv2 notice: Unify all files to just use one space in »MA 02110-1301«Paul Menzel
2013-02-27smm: Update rev 0x30101 SMM revision save stateAaron Durbin
2013-02-11Intel: Replace MSR 0xcd with MSR_FSB_FREQPatrick Georgi
2012-12-06Unify assembler function handlingStefan Reinauer
2012-11-27Remove AMD special case for LAPIC based udelay()Patrick Georgi
2012-11-27intel/i82801ix: new southbridge, ICH9Patrick Georgi
2012-11-20secondary.S: Fix dropping ramstage.aStefan Reinauer
2012-11-20Make sure only one udelay function is availableStefan Reinauer
2012-11-13Clean up stack checking codeStefan Reinauer
2012-11-13clean up lapic_cpu_init.cStefan Reinauer
2012-11-13Pass the CPU index as a parameter to startup.Ronald G. Minnich
2012-11-13Support better tracking of AP stack usage.Ronald G. Minnich
2012-11-12Fix gcc-4.7 building problem.Han Shen
2012-08-09Synchronize rdtsc instructionsStefan Reinauer
2012-08-07Move cpus_ready_for_init() to AMD K8Kyösti Mälkki
2012-08-01Intel Sandybridge: add reserved memory as resourcesKyösti Mälkki
2012-07-31Revert "Use broadcast SIPI to startup siblings"Sven Schnelle
2012-07-31Revert "remove CONFIG_SERIAL_CPU_INIT"Sven Schnelle
2012-07-26USBDEBUG: buffer up to 8 bytesSven Schnelle
2012-07-25SMM: Fix state table for Intel Core2 CPUsStefan Reinauer
2012-07-25Fix LAPIC timer on Ivy Bridge systemsStefan Reinauer
2012-07-24SMM: Fix state save map for sandybridge and TSEGDuncan Laurie
2012-07-24SMM: Add heap region and move C handler higher in regionDuncan Laurie
2012-07-24Rename cache_lbmem() to cache_ramstage()Stefan Reinauer
2012-07-24MTRR: drop repetetive debug messageStefan Reinauer
2012-07-23Re-initialize Local APIC timer on APsStefan Reinauer
2012-07-16Check for IORESOURCE_UMA_FB in MTRR setupKyösti Mälkki
2012-07-16Define global uma_memory variablesKyösti Mälkki
2012-07-12Drop Kconfig VAR_MTRR_HOLE optionKyösti Mälkki
2012-07-12Fix stack assignment during CPU initializationSven Schnelle
2012-07-05Only copy real-mode section of SIPI vectorKyösti Mälkki
2012-07-05Fix the CPU index parameter passed to secondary_cpu_init().Kyösti Mälkki
2012-07-02remove CONFIG_SERIAL_CPU_INITSven Schnelle
2012-07-02Use broadcast SIPI to startup siblingsSven Schnelle
2012-06-12udelay: add missing bus frequencySven Schnelle
2012-05-30Fix the location of "Setting variable MTRR" printk.Denis 'GNUtoo' Carikli
2012-05-08Some more #if cleanupPatrick Georgi
2012-05-08Clean up #ifsPatrick Georgi
2012-04-20Revert wbind added to the reset_vectorMarc Jones
2012-04-11Remove obsolete empy macro definitionRon Minnich
2012-04-06Fixes and Sandybridge support for lapic cpu initStefan Reinauer
2012-04-06Add Sandybridge/Cougar Point support to SMM relocation handlerStefan Reinauer
2012-04-06Cache 8MB flash instead of 4MBStefan Reinauer
2012-04-05Fix timer frequency detection on SandybridgeStefan Reinauer
2012-04-05Invalidate cache before first jumpStefan Reinauer
2012-04-05Update documentation in smmrelocate.S to mention TSEGStefan Reinauer
2012-04-04Add support to run SMM handler in TSEG instead of ASEGStefan Reinauer
2012-03-30Make MTRR min hole alignment 64MBDuncan Laurie
2012-03-30Fix MB calculation in the reporting of the MTRR holeDuncan Laurie
2012-03-30MTRR: add alternate allocation method for odd memory mapsDuncan Laurie
2012-03-30Add Kconfig options to enable TSEG and set a sizeDuncan Laurie
2012-03-30drop use of MAX_PHYSICAL_CPUS and MAX_CPUS where not neededStefan Reinauer
2012-03-30Add an option to keep the ROM cached after romstageStefan Reinauer
2012-03-25Fix possible deadlock on SMP stop_this_cpuKyösti Mälkki
2012-03-16ROMCC boards have no XIP limitPatrick Georgi
2012-03-16Fix address of IDT in real-mode entryKyösti Mälkki
2012-03-09move console includes to central console/console.hStefan Reinauer
2012-03-07Move C labels to start-of-linePatrick Georgi
2012-02-17Remove whitespace.Patrick Georgi
2012-01-23post code: Replaced hard-coded post code with macroVikram Narayanan
2012-01-21trivial: spelling fixes in commentsVikram Narayanan
2012-01-20Leave SSE and MMX instructions enabled in corebootStefan Reinauer
2012-01-10MTRR: get physical address size from CPUIDSven Schnelle
2011-12-05Bootblock does not need a unique boot_cpu()Kyösti Mälkki
2011-11-24Remove unused code files and cosmetic changesKyösti Mälkki
2011-11-22Fix post_code in 16bit entryKyösti Mälkki
2011-11-01remove trailing whitespaceStefan Reinauer
2011-11-01Remove XIP_ROM_BASEPatrick Georgi
2011-10-28Get rid of AUTO_XIP_ROM_BASEPatrick Georgi
2011-10-15SMM: Move wbinvd after pmode jumpStefan Reinauer
2011-10-13Load an IDT with NULL limitStefan Reinauer
2011-09-12Miscellaneous AMD F14 warning fixesefdesign98
2011-07-22Add SSE3 dependent codeefdesign98
2011-07-04Small SMM fixupsRudolf Marek
2011-06-18SMM: flush caches after disabling cachingSven Schnelle
2011-06-15SMM: don't overwrite SMM memory on resumeSven Schnelle
2011-05-10This replaces the fixed shift values in the apic timer init with macros.Vikram Narayanan
2011-04-26Add support for memory mapped UARTs to coreboot and add the OXPCIe952 as anStefan Reinauer
2011-04-19Fix some more misuses of ifdef/if definedStefan Reinauer
2011-04-14drop half an uart8250 implementation from smiutil and use the common code Stefan Reinauer
2011-04-14earlymtrr.c: wipe some dead code, use names instead of numbers and someStefan Reinauer
2011-04-14drop incorrectly used CONFIG_ROM_IMAGE_SIZE and unused CONFIG_ARCHStefan Reinauer
2011-04-11Unify use of post_codeAlexandru Gagniuc
2011-01-19Now that the VIA code is run above 1Meg (like other boards), it shouldKevin O'Connor
2010-12-18SMM for AMD K8 Part 1/2Stefan Reinauer
2010-12-18Support Intel SCH (Poulsbo) and add iwave/iWRainbowG6 boardPatrick Georgi
2010-12-16- Fix shortcoming in Kconfig when handling multiple "choice"sStefan Reinauer
2010-11-22Printing coreboot debug messages on VGA console is pretty much useless, sinceStefan Reinauer
2010-11-13MTRR related improvements for AMD family 10h and family 0Fh systemsScott Duplichan
2010-10-20Now that no boards set RAMBASE < 1M, get rid of some dead code. Trivial.Myles Watson
2010-10-19To reduce boot time, remove the double startup IPI and 10 ms delay from lapic...Scott Duplichan
2010-09-30Rename build system variables to be more intuitive, andPatrick Georgi
2010-09-29Forgot to 'svn add' src/cpu/x86/name (trivial).Uwe Hermann
2010-09-27Add a few missing license headers based on svn logs, and also add aUwe Hermann
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