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2024-04-12tree: Drop duplicated <device/{path,resource}.h>Elyes Haouas
<device/device.h> is supposed to provide <device/{path,resource}.h> Change-Id: I2ef82c8fe30b1c1399a9f85c1734ce8ba16a1f88 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81830 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-03-09cpu/x86/smm: Set up page tables in safe SMRAMArthur Heymans
Relying on page tables being in RO flash is not safe in every setup, therefore set up some page tables in SMRAM that the permanent smihandler can use. Tested on QEMU. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: Icb3086abd577b9abb9966dd910a264a873ace4ed Reviewed-on: https://review.coreboot.org/c/coreboot/+/80336 Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-by: Benjamin Doron <benjamin.doron00@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-02-28cpu/x86/(sipi|smm): Pass on CR3 from ramstageArthur Heymans
To allow for more flexibility like generating page tables at runtime or page tables that are part of the ramstage, add a parameter to sipi_vector.S and smm_stub.S so that APs use the same page tables as the BSP during their initialization. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I1250ea6f63c65228178ee66e06d988dadfcc2a37 Reviewed-on: https://review.coreboot.org/c/coreboot/+/80335 Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
2023-11-10cpu/x86/smm: Fix get_save_state calculationEugene D. Myers
When the SMI transfer monitor (STM) is configured, get_save_state returns an incorrect pointer to the cpu save state because the size (rounded up to 0x100) of the processor System Management Mode (SMM) descriptor needs to be subtracted out in this case. This patch addresses the issue identified in CB:76601, which means that SMMSTOREv2 now works with the STM. Thanks to Jeremy Compostella for suggesting this version of the patch. Resolves: https://ticket.coreboot.org/issues/511 Change-Id: I0233c6d13bdffb3853845ac6ef25c066deaab747 Signed-off-by: Eugene D. Myers <edmyers@cyberpackventures.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78889 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-09-08arch to drivers/intel: Fix misspellings & capitalization issuesMartin Roth
Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: Ic52f01d1d5d86334e0fd639b968b5eed43a35f1d Reviewed-on: https://review.coreboot.org/c/coreboot/+/77633 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-05-31cpu/x86/mp_init: Use clflush to write SIPI data back to RAMJeremy Compostella
Improve boot time performances by replacing the wbinvd instruction with multiple clflush to ensure that the SIPI data is written back to RAM. According to some experimental measurements, the wbinvd execution takes between 1.6 up and 6 milliseconds to complete. In the case of the SIPI data, wbinvd unnecessarily flushes and invalidates the entire cache. Indeed, the SIPI module is quite small (about 400 bytes) and cflush'ing the associated cache lines is almost instantaneous, typically less than 100 microseconds. BUG=b/260455826 TEST=Successful boot on Skolas and Rex board Change-Id: I0e00db8eaa6a3cb41bec3422572c8f2a9bec4057 Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Suggested-by: Erin Park <erin.park@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75391 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-04-13cpu/x86/mp_init.c: Set topology on BSPArthur Heymans
The BSP might have non-zero lapicid so set the topology accordingly, without assuming it is 0. This fixes a cpu exception on at least Intel Meteorlake. This was caused by FSP CPU PPI being giving incorrect information about the BSP topology. This problem was introduced by 8b8400a "drivers/fsp2_0/mp_service_ppi: Use struct device to fill in buffer" which sets the PPI struct based on struct device. TESTED on google/rex Change-Id: I3fae5efa86d8efc474c129b48bdfa1d1e2306acf Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74374 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-06cpu/x86/topology: Add code to fill in topology on struct pathArthur Heymans
This is needed to generate MADT and SRAT where lapicid for threads need to be added last. When CPUID leaf '0xB' is not present assume some defaults that would result in identical ACPI code generation. Change-Id: I2210eb9b663dd90941a64132aa7154440dc7e5a9 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69222 Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-06cpu/mp_init.c: Only enable CPUs once they execute codeArthur Heymans
On some systems the BSP cannot know how many CPUs are present in the system. A typical use case is a multi socket system. Setting the enable flag only on CPUs that actually exist makes it more flexible. Change-Id: I6c8042b4d6127239175924f996f735bf9c83c6e8 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68892 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-06cpu/smm_module_loader.c: Fix up CPU index locallyArthur Heymans
Don't pass the stub params to the mp_init code. Change-Id: I070bc00ae5e5bceb6c5b90ea833cc057dd41f6cc Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64802 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-06cpu/x86/mp_init.c: Generate a C header to get start32 offsetArthur Heymans
In the current design the relocatable parameters are used to know the offset of the 32bit startpoint. This requires back and forward interaction between the stub, the loader and the mp init code. This makes the code hard to read. This is static information known at buildtime, so a better way to deal with this is to generate a header that contains this offset. Change-Id: Ic01badd2af11a6e1dbc27c8e928916fedf104b5b Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64625 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-06cpu/x86/mp_init.c: Keep track of initial lapic ID inside device_pathArthur Heymans
It's quite confusing to keep track of lapic ID inside the device struct and initial lapic ID inside an array. Change-Id: I4d9f8d23c0b0e5c142f6907593428d8509e4e7bb Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64342 Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-03-10mp_init: Wait longer for APs to check inPatrick Rudolph
On IBM/SBP1 with 384 cores it takes a while for all APs to check in. Use linear scaling instead of hardcoding an arbitrary limit for the timeout. Change-Id: If020a3fa985bfc7fd2f0aa836dc04e6647a1a450 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73369 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shuo Liu <shuo.liu@intel.com> Reviewed-by: TangYiwei Reviewed-by: Naresh <naresh.solanki.2011@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-02-27tree: Move 'asmlinkage' before type 'void'Elyes Haouas
Move 'asmlinkage' before the function type for consistency. Change-Id: I293590ef917b78c6ed3d151cd0080e42d0f10651 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73259 Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-23cpu/x86: Set up a separate stack for APsArthur Heymans
APs use a lot less stack, so set up a separate stack for those in .bss. Now that CPU_INFO_V2 is the only code path that is used, there is no need to align stacks in c_start.S. Change-Id: I7a681a2e3003da0400843daa5d6d6180d952abf5 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69123 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2022-12-14cpu/x86/mp_init.c: Improve AP entry pointArthur Heymans
Make sure that a pointer exists before dereferencing it. Change-Id: I1a9833bb9686451224249efe599346f64dc37874 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70011 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-12-10cpu/cpu.h: Change the function signatureArthur Heymans
There is no need to pass the CPU index around. Change-Id: Iad8e3cb318e6520ac5877118dbf43597dedb75b9 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69504 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-11-12cpu/x86: Set thread local storage in C codeArthur Heymans
Doing this in C code is way easier to understand. Also the thread local storage is now in .bss instead of the AP stack. This makes it more robust against stack overflows, as APs stacks overflow in each other. TESTED: work on qemu. Change-Id: I19d3285daf97798a2d28408b5601ad991e29e718 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69435 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-05cpu/x86/mp_init.c: Use existing code to create cpu struct deviceArthur Heymans
Change-Id: I80baadd405b31d6be2fdbb894b0f4b7c775da6f8 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64341 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Zhang <jonzhang@fb.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-11-03Revert "cpu/x86/mp_init.c: Set a bogus initial lapic_id"Felix Held
This reverts commit 1bb9786da30e ("cpu/x86/mp_init.c: Set a bogus initial lapic_id"), since it breaks MP init on amd/mandolin: [INFO ] CPU #0 initialized [INFO ] Initializing CPU #3 [INFO ] Initializing CPU #1 [INFO ] Initializing CPU #2 [EMERG] CPU: missing CPU device structureCPU: vendor AMD device 810f81 [DEBUG] CPU: family 17, model 18, stepping 01 [DEBUG] microcode: patch id to apply = 0x08108109 [INFO ] microcode: being updated to patch id = 0x08108109 succeeded [INFO ] CPU #1 initialized [ERROR] MP record 3 timeout. [INFO ] bsp_do_flight_plan done after 1206 msecs. [ERROR] MP initialization failure. [EMERG] mp_init_with_smm failed. Halting. TEST=The board boots again with the revert applied Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ic1cae88f7345f9ff79e8f6e574521095b57c8cb7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69186 Reviewed-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-11-03cpu/x86/mp_init.c: Handle failed init_bsp()Arthur Heymans
Bail out of mp_init if this function fails. Change-Id: I7be5d6c32458ba98f4f8c5c9340790ff989c91e7 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69109 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-11-03cpu/x86/mp_init.c: Set a bogus initial lapic_idArthur Heymans
This makes it easier to catch errors later if the ap_init code fails to properly set things up. Change-Id: I938faf042bfa4fe1fc39e78ab740c9b210bc105c Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69108 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
2022-10-28cpu/x86/mp_init.c: Use linked list data structuresArthur Heymans
There is no need to keep track of device structures separately. Change-Id: Ie728110fc8c60fec94ae4bedf74e17740cf78f67 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64340 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-10-27cpu/x86/mp_init: adjust timeout for final SIPIJonathan Zhang
Adjust timeout for final SIPI to satisfy some to-be-launched server processors. Add a spew print to display how long it takes for the APs to be ready. This is intended to facilitate only troubleshooting and trend analysis. Change-Id: Id958f18bdcb34d76df8aa443161123252524328e Signed-off-by: Jonathan Zhang <jonzhang@meta.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68262 Reviewed-by: Christian Walter <christian.walter@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-24cpu/x86/mp_init: drop unused MAX_APIC_IDS defineFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I599e26a40ab584232614440612e95c91a698df27 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67775 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-09-24include/cpu/x86/mtrr: define NUM_FIXED_MTRRS once in mtrr.hFelix Held
Instead of defining NUM_FIXED_MTRRS in both cpu/x86/mp_init.h and cpu/x86/mtrr/mtrr.c in two different ways that will evaluate to the same value, define it once in include/cpu/x86/mtrr.h which is included in both C files. TEST=Timeless build for amd/mandolin results in identical firmware image Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I71cec61e22f5ce76baef21344c7427be29f193f8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67774 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2022-09-15soc/amd: Do SMM relocation via MSRArthur Heymans
AMD CPUs have a convenient MSR that allows to set the SMBASE in the save state without ever entering SMM (e.g. at the default 0x30000 address). This has been a feature in all AMD CPUs since at least AMD K8. This allows to do relocation in parallel in ramstage and without setting up a relocation handler, which likely results in a speedup. The more cores the higher the speedup as relocation was happening sequentially. On a 4 core AMD picasso system this results in 33ms boot speedup. TESTED on google/vilboz (Picasso) with CONFIG_SMI_DEBUG: verify that SMM is correctly relocated with the BSP correctly entering the smihandler. Change-Id: I9729fb94ed5c18cfd57b8098c838c08a04490e4b Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64872 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-09-14timer: Change timer util functions to 64-bitRob Barnes
Since mono_time is now 64-bit, the utility functions interfacing with mono_time should also be 64-bit so precision isn't lost. Fixed build errors related to printing the now int64_t result of stopwatch_duration_[m|u]secs in various places. BUG=b:237082996 BRANCH=All TEST=Boot dewatt Change-Id: I169588f5e14285557f2d03270f58f4c07c0154d5 Signed-off-by: Rob Barnes <robbarnes@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66170 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-07-13cpu/x86/mp_init: retype do_smm element in mp_state struct to boolFelix Held
The do_smm struct element in the mp_state struct was an int even though it only had two possible states, so change it to bool to make this more obvious. Also change the return type of is_smm_enabled from int to bool. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I8d2d95f0497649d67565243d14a5ab9c9cdda412 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65776 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-06-02cpu/x86/mp_init.c: Prolong delay on synchronous APIArthur Heymans
When each AP needs to do a lot of printing 1 sec is not enough. Change-Id: I00f0a49bf60f3915547924c34a62dd0044b0c918 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64828 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kane Chen <kane.chen@intel.corp-partner.google.com>
2022-05-28cpu/x86/mp_init.c: Drop 'real' vs 'used' save stateArthur Heymans
Now that the save state size is handled properly inside the smm_loader there is no reason to make that distinction in the mp_init code anymore. Change-Id: Ia0002a33b6d0f792d8d78cf625fd7e830e3e50fc Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63479 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@tutanota.com>
2022-05-16cpu/x86/mp_init.c: Add mp_run_on_all_cpus_synchronouslyKane Chen
MTRR is a core level register which means 2 threads in one core share same MTRR. There is a race condition could happen that AP overrides BSP MTRR unintentionally. In order to prevent such race condition between BSP and APs, this patch provides a function to let BSP assign tasks to all APs and wait them to complete the assigned tasks. BUG=b:225766934 Change-Id: I8d1d49bca410c821a3ad0347548afc42eb860594 Signed-off-by: Kane Chen <kane.chen@intel.corp-partner.google.com> Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63566 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-04-24{arch,cpu}: Remove redundant <arch/cpu.h>Elyes HAOUAS
<arch/cpu.h> is chain included through <cpu/cpu.h>. Change-Id: I54a837394f67ac2a759907c7212ab947d07338dc Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60931 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <martinroth@google.com>
2022-04-02{cpu/x86, drivers/amd}: Use `get_var_mtrr_count()` to get MTRR countSubrata Banik
This patch replaces the implementation that is used to get the number of variable MTRRs with `get_var_mtrr_count()` function. BUG=b:225766934 TEST=Able to build and boot google/redrix board to ChromeOS. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I4751add9c45374e60b7a425df87d06f52e6fcb8c Reviewed-on: https://review.coreboot.org/c/coreboot/+/63219 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-02-07cpu/x86/mp_init.c: Rename num_concurrent_stacksArthur Heymans
This is just the amount of cpus so rename it for simplicity. Change-Id: Ib2156136894eeda4a29e8e694480abe06da62959 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58699 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-02-07cpu/x86/smm: Improve smm stack setupArthur Heymans
Both the relocation handler and the permanent handler use the same stacks, so things can be simplified. Change-Id: I7bdca775550e8280757a6c5a5150a0d638d5fc2d Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58698 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-02-05cpu/x86/lapic: Move LAPIC configuration to MP initKyösti Mälkki
Implementation for setup_lapic() did two things -- call enable_lapic() and virtual_wire_mode_init(). In PARALLEL_MP case enable_lapic() was redundant as it was already executed prior to initialize_cpu() call. For the !PARALLEL_MP case enable_lapic() is added to AP CPUs. Change-Id: I5caf94315776a499e9cf8f007251b61f51292dc5 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58387 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-02-05cpu/x86/lapic: Add lapic_send_ipi_self,others()Kyösti Mälkki
This avoids unnecessary passing of APIC ID parameter and allows some minor optimisation for X2APIC mode. Change-Id: I0b0c8c39ecd13858cffc91cc781bea52decf67c5 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60713 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-02-05cpu/x86/lapic: Support switching to X2APIC modeKyösti Mälkki
The options X2APIC_ONLY and X2APIC_RUNTIME were already user-visible choices in menuconfig, but the functionality was not actually provided except for platforms where FSP presumably enabled X2APIC. Add the logic and related logging for switching to X2APIC operation. TEST: qemu-system-x86_64 -M Q35 -accel kvm -bios coreboot.rom -serial stdio -smp 2 PARALLEL_MP, and either X2APIC_ONLY or X2APIC_RUNTIME, need to be selected for the build of emulation/qemu-q35. Change-Id: I19a990ba287d21ccddaa64601923f1c4830e95e9 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55262 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
2022-02-03cpu/x86/smm: Retype variablesArthur Heymans
Change-Id: I85750282ab274f52bc176a1ac151ef2f9e0dd15d Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58697 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2021-12-10cpu/x86/mp_init.c: Make it work for !CONFIG_SMPArthur Heymans
With very little changes this code can be used to initialize systems without SMP. The linker will remove most of the code. Change-Id: Ia0e8fdf8ed7bc2e0e4ff01be8d3e3c3cb837e6c7 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59692 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-12-06cpu/x86/mp_init.c: Fix HAVE_SMI_HANDLERArthur Heymans
Fixes commit 29c7622 ("cpu/x86/mp_init.c: Fix building with no smihandler") broke SMM init because is_smm_enable() was called before smm_enable. Rework the code a little to make it clear what codepaths are used with CONFIG_HAVE_SMI_HANDLER. TESTED: now prodrive/hermes boots again. Change-Id: If4ce0dca2f29754d131dacf2da63e946be9a7b6d Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59912 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-12-03cpu/x86/mp_init.c: Fix building with no smihandlerArthur Heymans
The build fails because smm_stub_size() tries to find a symbol that won't be present. Change-Id: I73fee3cf26c0e37cca03299c6730f7b4f1ef6685 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54754 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2021-12-01cpu/x86/mp_init.c: Fix building without an SMI_HANDLERArthur Heymans
Tested on Qemu/i440fx. The follow-up commit adds a config file to buildtest it. Change-Id: Ieeaa85691e4c4516bb51df0e87c4ecaa940810f0 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59694 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-11-29cpu/x86: Rename X86_AMD_INIT_SIPI to X86_INIT_NEED_1_SIPISubrata Banik
This patch renames X86_AMD_INIT_SIPI Kconfig to leverage the same logic (to skip 2nd SIPI and reduce delay between INIT and SIPI while perform AP initialization) even on newer Intel platform. Change-Id: I7a4e6a8b1edc6e8ba43597259bd8b2de697e4e62 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56651 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-10-22cpu/x86/mp_init: move printing of failure message into mp_init_with_smmFelix Held
Each CPU/SoC checks the return value of the mp_init_with_smm and prints the same error message if it wasn't successful, so move this check and printk to mp_init_with_smm. For this the original mp_init_with_smm function gets renamed to do_mp_init_with_smm and a new mp_init_with_smm function is created which then calls do_mp_init_with_smm, prints the error if it didn't return CB_SUCCESS and passes the return value of do_mp_init_with_smm to its caller. Since no CPU/SoC code handles a mp_init_with_smm failure apart from printing a message, also add a comment at the mp_init_with_smm call sites that the code might want to handle a failure. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I181602723c204f3e43eb43302921adf7a88c81ed Reviewed-on: https://review.coreboot.org/c/coreboot/+/58498 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-10-22cpu/x86/mp_init: use cb_err as status return type in remaining functionsFelix Held
Using cb_err as return type of mp_run_on_aps, mp_run_on_all_aps, mp_run_on_all_cpus and mp_park_aps clarifies the meaning of the different return values. This patch also adds the types.h include that provides the definition of the cb_err enum and checks the return value of all 4 functions listed above against the enum values instead of either checking if it's non-zero or less than zero to handle the error case. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I4b3f03415a041d3ec9cd0e102980e53868b004b0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58494 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-10-21cpu/x86/mp_init: use cb_err as mp_init_with_smm return typeFelix Held
Using cb_err as return type clarifies the meaning of the different return values. This patch also adds the types.h include that provides the definition of the cb_err enum and checks the return value of mp_init_with_smm against the enum values instead of either checking if it's non-zero or less than zero to handle the error case. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ibcd4a9a63cc87fe176ba885ced0f00832587d492 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58491 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-21cpu/x86/mp_init: use cb_err as run_ap_work return typeFelix Held
Using cb_err as return type clarifies the meaning of the different return values. To not change the return types of mp_run_on_aps which is exposed outside of this compilation unit to keep the scope of this patch limited, the return value of run_ap_work gets translated to the int values in mp_run_on_aps. This could also be done by a cast of the run_ap_work return value to int, but an explicit translation of the return values should be clearer about what it does there. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Id346c8edf06229a929b4783498d8c6774f54a8b1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58490 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-10-21cpu/x86/mp_init: use cb_err as mp_init & bsp_do_flight_plan return typeFelix Held
Using cb_err as return type clarifies the meaning of the different return values. To not change the return types of mp_init_with_smm which is exposed outside of this compilation unit to keep the scope of this patch limited, the return value of mp_init gets translated to the int values in mp_init_with_smm. This could also be done by a cast of the mp_init return value to int, but an explicit translation of the return values should be clearer about what it does there. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I4129c1db06a877c47cca87782af965b62dcbbdc2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58489 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-10-21cpu/x86/mp_init: use cb_err as wait_for_aps return typeFelix Held
Using cb_err as return type clarifies the meaning of the different return values. Also restructure the implementation of wait_for_aps to not need a local timeout variable. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I86b8c8b0849ae130c78125b83d159147ce11914c Reviewed-on: https://review.coreboot.org/c/coreboot/+/58488 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-10-21cpu/x86/mp_init: use cb_err as apic_wait_timeout return typeFelix Held
Using cb_err as return type clarifies the meaning of the different return values. Also restructure the implementation of apic_wait_timeout to not need a local timeout variable. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I2fe32c761492d252b154d2f50f2a330cf4f412d5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58487 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-10-21cpu/x86/mp_init: use cb_err as install_permanent_handler return typeFelix Held
Using cb_err as return type clarifies the meaning of the different return values. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ifb64b5908b938bb162153433e5f744ab0b95c525 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58486 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-10-21cpu/x86/mp_init: use cb_err as install_relocation_handler return typeFelix Held
Using cb_err as return type clarifies the meaning of the different return values. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I95f36ba628c7f3ce960a8f3bda730d1c720253cc Reviewed-on: https://review.coreboot.org/c/coreboot/+/58485 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-10-21cpu/x86: Remove cpu parameter to ap_initRaul E Rangel
We now pre-populate cpu_info before jumping to the C handler. We no longer need this parameter. I moved the stack alignment closer to the actual invocation of the C handler so it's easier to reason about. BUG=b:194391185, b:179699789 TEST=Boot guybrush to OS and verify all CPUs still function Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I8997683b6613b7031784cabf7039a400f0efdea1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58147 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-10-21cpu/x86: Require CPU_INFO_V2 when selecting PARALLEL_MPRaul E Rangel
This will reduce the number of AP init paths we need to support. BUG=b:194391185, b:179699789 TEST=Boot guybrush to OS and see all CPUs initialized correctly Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I05beb591bd7b3a26b6c51c10d4ffd6f8621c12eb Reviewed-on: https://review.coreboot.org/c/coreboot/+/58146 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-10-20cpu/x86/mp_init: rework start_aps to fix X86_AMD_INIT_SIPI caseFelix Held
When CONFIG_X86_AMD_INIT_SIPI was set, the second/final SIPI that afterwards checks if all APs have checked in was skipped and if it got so far, start_aps returned CB_SUCCESS despite not having checked if all APs had checked in after the SIPI. This patch makes start_aps skip the first SIPI in the CONFIG_X86_AMD_INIT_SIPI case so we use the proper timeouts and error handling for the final and this case only SIPI and signal the caller an error when not all APs have checked in after the SIPI. A timeless build for lenovo/x230 which is a mainboard that doesn't select X86_AMD_INIT_SIPI results in identical binary, so this doesn't change the behavior of the !X86_AMD_INIT_SIPI case. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I39438229497c5d9c44dc7e247c7b2c81252b4bdb Reviewed-on: https://review.coreboot.org/c/coreboot/+/58456 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-10-20cpu/x86/mp_init: use cb_err as start_aps return typeFelix Held
Using cb_err as return type clarifies the meaning of the different return values. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Icb96f28b4d59b3d00638a43c927df80f5d1643f9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58455 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-10-20cpu/x86/mp_init: add final new line to debug messagesFelix Held
Since during AP startup it's not guaranteed that no AP console output will be printed between consecutive printk calls in send_sipi_to_aps, add a new line character to all printks to make sure to have the outputs from the APs on separate lines. For consistency also add a final new line character to the printk call in start_aps. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I3983b8a0e6b272ba5fb2a90a108d17a0c480c8b8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58454 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-10-20cpu/x86/mp_init: factor out send_sipi_to_aps functionFelix Held
Apart from the SIPI number in the debug message the two instances of the SIPI sending code in start_aps are identical, so factor it out into a new send_sipi_to_aps function. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I6a921b81fce77fbf58c7ae3b50efd8c3e6e5aef3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58453 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-10-20cpu/x86/mp_init: use types.h includeFelix Held
Using types.h as include instead of stddef.h and stdint.h will also provide commonlib/bsd/cb_err.h which will be used in follow-up patches. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I08a68dc827d60c6c9a27b3ec8b74b9c8a2c96d12 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58452 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-10-18arch/x86,cpu/x86,lib/thread: Remove usage of cpu_info from lib/threadRaul E Rangel
We only ever start and execute threads on the BSP. By explicitly checking to see if the CPU is the BSP we can remove the dependency on cpu_info. With this change we can in theory enable threads in all stages. BUG=b:194391185, b:179699789 TEST=Boot guybrush to OS and verify coop multithreading still works Suggested-by: Julius Werner <jwerner@chromium.org> Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Iea4622d52c36d529e100b7ea55f32c334acfdf3e Reviewed-on: https://review.coreboot.org/c/coreboot/+/58199 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-10-05arch/x86,cpu/x86: Introduce new method for accessing cpu_infoRaul E Rangel
There is currently a fundamental flaw in the current cpu_info() implementation. It assumes that current stack is CONFIG_STACK_SIZE aligned. This assumption breaks down when performing SMM relocation. The first step in performing SMM relocation is changing the SMBASE. This is accomplished by installing the smmstub at 0x00038000, which is the default SMM entry point. The stub is configured to set up a new stack with the size of 1 KiB (CONFIG_SMM_STUB_STACK_SIZE), and an entry point of smm_do_relocation located in RAMSTAGE RAM. This means that when smm_do_relocation is executed, it is running in SMM with a different sized stack. When cpu_info() gets called it will be using CONFIG_STACK_SIZE to calculate the location of the cpu_info struct. This results in reading random memory. Since cpu_info() has to run in multiple environments, we can't use a compile time constant to locate the cpu_info struct. This CL introduces a new way of locating cpu_info. It uses a per-cpu segment descriptor that points to a per-cpu segment that is allocated on the stack. By using a segment descriptor to point to the per-cpu data, we no longer need to calculate the location of the cpu_info struct. This has the following advantages: * Stacks no longer need to be CONFIG_STACK_SIZE aligned. * Accessing an unconfigured segment will result in an exception. This ensures no one can call cpu_info() from an unsupported environment. * Segment selectors are cleared when entering SMM and restored when leaving SMM. * There is a 1:1 mapping between cpu and cpu_info. When using COOP_MULTITASKING, a new cpu_info is currently allocated at the top of each thread's stack. This no longer needs to happen. This CL guards most of the code with CONFIG(CPU_INFO_V2). I did this so reviewers can feel more comfortable knowing most of the CL is a no-op. I would eventually like to remove most of the guards though. This CL does not touch the LEGACY_SMP_INIT code path. I don't have any way of testing it. The %gs segment was chosen over the %fs segment because it's what the linux kernel uses for per-cpu data in x86_64 mode. BUG=b:194391185, b:179699789 TEST=Boot guybrush with CPU_INFO_V2 and verify BSP and APs have correct %gs segment. Verify cpu_info looks sane. Verify booting to the OS works correctly with COOP_MULTITASKING enabled. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I79dce9597cb784acb39a96897fb3c2f2973bfd98 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57627 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Peers <epeers@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-09-27cpu/x86/mp_init: add expansion for SIPI acronymFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ic182d7c551932ab6917a81568490ed18acdcd597 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57927 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-24cpu/x86/mp_init: Add comment to smm_do_relocationRaul E Rangel
It took me a while to understand the SMM set up flow. This adds a clarifying comment. BUG=b:194391185, b:179699789 TEST=None Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I9c73e416b8c583cf870e7a29b0bd7dcc99c2f5f4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57858 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2021-09-04cpu/x86: Use MP_RUN_ON_ALL_CPUS macro instead of hardcodingSubrata Banik
This patch ensures mp_run_on_all_aps() is passing 'MP_RUN_ON_ALL_CPUS' macro rather hardcoding `0` while running `func` on all APs. Change-Id: Icd34371c0d4349e1eefe945958eda957c4794707 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57342 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-07-27cpu/x86/mp_init: don't wait between INIT and SIPI for X86_AMD_INIT_SIPIFelix Held
Since current AMD SoCs don't need some wait time between INIT and SIPI, we can skip the 10ms wait there, which improves the boot time a bit. before: CPU_CLUSTER: 0 init finished in 632 msecs after: CPU_CLUSTER: 0 init finished in 619 msecs mpinit still works on Mandolin and all CPU cores show up and are usable. This also doesn't change the binary in a timeless build for boards/SoCs that don't select X86_AMD_INIT_SIPI which I verified for lenovo/x230. BUG=b:193885336 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I1e044776f45021742a88a5e369a74383c1baaab6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56533 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-07-26arch/x86,cpu/x86/mp_init: Switch cpu_info index type to size_tRaul E Rangel
The alignment for `struct cpu_info` is wrong on x86_64. c_start.S uses the `push` instruction when setting up the cpu_info struct. This instruction will push 8 bytes but `unsigned int` is 4 bytes. By making it a `size_t` we get the correct size for both x86_32 and x86_64. BUG=b:179699789 TEST=Boot guybrush to the OS Suggested-by: Julius Werner <jwerner@chromium.org> Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I8ef311aaa8333ccf8a5b3f1f0e852bb26777671c Reviewed-on: https://review.coreboot.org/c/coreboot/+/56573 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-06-16cpu/x86/mp_init: Support both xapic and x2apic with common codeArthur Heymans
Trigger mode LAPIC_INT_LEVELTRIG was only used with LAPIC_DM_INIT, specifically for (obsolete) Init Level De-assert. Level LAPIC_INT_ASSERT is required to be set for all other delivery modes other than LAPIC_DM_INIT. This reverts the two above changes that X2APIC mode support introduced to the IPI for LAPIC_DM_SMI. Change-Id: I7264f39143cc6edb7a9687d0bd763cb2703a8265 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55197 Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-10cpu/x86/lapic: Add lapic_busy() helperArthur Heymans
Change-Id: Ife127d6dc8241cccb9d52236a9152da707f0e261 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55191 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-10cpu/x86/lapic: Add lapic_send_ipi() helperArthur Heymans
Change-Id: I7207a9aadd987b4307ce8b3dd8dbfd47d0a5768e Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55190 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-19cpu/x86/smm: Drop the V1 smmloaderArthur Heymans
Change-Id: I536a104428ae86e82977f2510b9e76715398b442 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51187 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-04-19cpu/x86/smm_loaderv2: Use the permanent stack top during relocationArthur Heymans
Use the same stack location during relocation as for the permanent handler. When the number of CPUs is too large the stacks during relocation don't fit inside the default SMRAM segment at 0x30000. Currently the code would just let the CPU stack base grow downwards outside of the default SMM segment which would corrupt lower memory if S3 is implemented. Also update the comment on smm_module_setup_stub(). Change-Id: I6a0a890e8b1c2408301564c22772032cfee4d296 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51186 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-04-15*x86: Support x2apic modeWonkyu Kim
Implement x2apic mode as existing code only supports apic mode. Use info from LAPIC_BASE_MSR (LAPIC_BASE_MSR_X2APIC_MODE) to check if apic mode or x2apic mode and implement x2apic mode according to x2apic specfication. Reference: https://software.intel.com/content/www/us/en/develop/download/intel-64-architecture-x2apic-specification.html BUG=None BRANCH=None TEST=boot to OS and check apic mode cat /proc/cpuinfo | grep "apicid" ex) can see apicid bigger than 255 apicid : 256 apicid : 260 Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com> Change-Id: I0bb729b0521fb9dc38b7981014755daeaf9ca817 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51723 Reviewed-by: Ravishankar Sarawadi <ravishankar.sarawadi@intel.com> Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-19cpu/x86/mp_init.c: Drop unnecessary preprocessor usageArthur Heymans
Change-Id: If67bcbf0c8ffbd041e2e4cab8496f4634de26552 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51185 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-03-19cpu/x86/mp_init.c: Don't overwrite the global variable per CPUArthur Heymans
Global variables are located in .bss and not on the CPU stack. Overwriting them a per CPU case is bound to cause race conditions. In this case it is even just plainly wrong. Note: This variable is set up in the get_smm_info() function. Change-Id: Iaef26fa996f7e30b6e4c4941683026b8a29a5fd1 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51184 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-03-19cpu/x86/mp_init: Allow stub sizes larger than the save state sizeArthur Heymans
The permanent handler module argument 'save_state_size' now holds the meaning of the real save state size which is then substracted from the CPUs save state 'top' to get the save state base. TESTED with qemu Q35 on x86_64 where the stub size exceeds the AMD64 save state size. Change-Id: I55d7611a17b6d0a39aee1c56318539232a9bb781 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50770 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-03-19cpu/x86/smm_stub.S: Drop smm_runtime from the stubArthur Heymans
The parameters that the permanent handler requires are pushed directly to the permanent handlers relocatable module params. The paremeters that the relocation handler requires are not passed on via arguments but are copied inside the ramstage. This is ok as the relocation handler calls into ramstage. Change-Id: Ice311d05e2eb0e95122312511d83683d7f0dee58 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50767 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2021-03-19cpu/x86/mp_init.c: Copy the stub parameter start32_offset into ramstageArthur Heymans
Keep a copy of start32_offset into ramstage to avoid needing to pass arguments, calling from assembly. Doing this in C code is better than assembly. Change-Id: Iac04358e377026f45293bbee03e30d792df407fd Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50765 Reviewed-by: Eugene Myers <cedarhouse1@comcast.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-18cpu/x86/mp_init.c: Calculate perm_smbase from ramstage dataArthur Heymans
The data needed to compute the permanent smbase for a core, when relocating, is present in the ramstage data which the stub located at DEFAULT_SMBASE (0x30000) calls back to. There is no need to fetch this from via the stub params. Change-Id: I3894c39ec8cae3ecc46b469a0fdddcad2a8f26c4 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50763 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-18cpu/x86/smm: Move apic_id_to_cpu map to smm_stub paramsArthur Heymans
This is only consumed by the stub and not by the relocation handler or the permanent handler, so move it out of the runtime struct. Change-Id: I01ed0a412c23c8a82d88408be058a27e55d0dc4d Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50762 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-03-11src/cpu/x86: Add helper mp_run_on_all_apsAamir Bohra
Add a helper function mp_run_on_all_aps, it allows running a given func on all APs excluding the BSP, with an added provision to run func in serial manner per AP. BUG=b:169114674 Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Change-Id: I74ee8168eb6380e346590f2575350e0a6b73856e Reviewed-on: https://review.coreboot.org/c/coreboot/+/51271 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-01cpu/x86/mp_init.c: Print out the microcode revision of APsArthur Heymans
It is useful to know if MCU have been applied successfully. On the start of MP init lines similar to: "AP: slot 1 apic_id 1, MCU rev: 0x0700001d" will be printed. The example is taken from the log of an ocp/deltalake. Change-Id: Ia0a6428b41d07f87943f3aa7736b8cb457fdd15a Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49840 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-15cpu/mp_init: Fix microcode lockPatrick Rudolph
Fix C code to match comment and assembly implementation. Tested on Prodrive hermes: The microcode spinlock is no longer used. Change-Id: I21441299f538783551d4d5ba2b2e7567e152d718 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49304 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-03cpu/x86/mp_init: Add support for x86_64Patrick Rudolph
Fix compilation on x86_64. Tested on HP Z220: * Still boots on x86_32. Change-Id: Id7190d24172803e40acaf1495ce20f3ea38016b0 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44675 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-30cpu/x86: increase timeout for CPUs to check in after 2nd SIPIJonathan Zhang
Increase timeout for CPUs to check in after 2nd SIPI completion from 10ms to 100ms. Update logging level for mp init failure cases from BIOS_DEBUG to BIOS_ERR. Without this patch, "mp initialization failure" happens on some reboots on DeltaLake server. As consequence, not all 52 cpus come up in Linux: [root@localhost ~]# lscpu ... CPU(s): 40 Also following Hardware Errors are seen: [ 4.365762] mce: [Hardware Error]: Machine check events logged [ 4.366565] mce: [Hardware Error]: CPU 0: Machine Check: 0 Bank 9: ee2000000003110a [ 4.367561] mce: [Hardware Error]: TSC 0 ADDR fe9e0000 MISC 228aa040101086 [ 4.368563] mce: [Hardware Error]: PROCESSOR 0:5065b TIME 948438164 SOCKET 0 APIC 0 microcode 700001d With this patch, no such failure is observed with 370 reboots. Signed-off-by: Tim Chu <Tim.Chu@quantatw.com> Signed-off-by: Jonathan Zhang <jonzhang@fb.com> Change-Id: Iab10f116dd4af152c24d5d8f999928c038a5b208 Reviewed-on: https://review.coreboot.org/c/coreboot/+/46898 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-21src/cpu: Drop unneeded empty linesElyes HAOUAS
Change-Id: I116b15c83fcc5d69d3f80a2e6cf0fb085064d9a6 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44604 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-08-15cpu/x86/smm: Introduce SMM module loader version 2Rocky Phagura
Xeon-SP Skylake Scalable Processor can have 36 CPU threads (18 cores). Current coreboot SMM is unable to handle more than ~32 CPU threads. This patch introduces a version 2 of the SMM module loader which addresses this problem. Having two versions of the SMM module loader prevents any issues to current projects. Future Xeon-SP products will be using this version of the SMM loader. Subsequent patches will enable board specific functionality for Xeon-SP. The reason for moving to version 2 is the state save area begins to encroach upon the SMI handling code when more than 32 CPU threads are in the system. This can cause system hangs, reboots, etc. The second change is related to staggered entry points with simple near jumps. In the current loader, near jumps will not work because the CPU is jumping within the same code segment. In version 2, "far" address jumps are necessary therefore protected mode must be enabled first. The SMM layout and how the CPUs are staggered are documented in the code. By making the modifications above, this allows the smm module loader to expand easily as more CPU threads are added. TEST=build for Tiogapass platform under OCP mainboard. Enable the following in Kconfig. select CPU_INTEL_COMMON_SMM select SOC_INTEL_COMMON_BLOCK_SMM select SMM_TSEG select HAVE_SMI_HANDLER select ACPI_INTEL_HARDWARE_SLEEP_VALUES Debug console will show all 36 cores relocated. Further tested by generating SMI's to port 0xb2 using XDP/ITP HW debugger and ensured all cores entering and exiting SMM properly. In addition, booted to Linux 5.4 kernel and observed no issues during mp init. Change-Id: I00a23a5f2a46110536c344254868390dbb71854c Signed-off-by: Rocky Phagura <rphagura@fb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43684 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-05-11treewide: Remove "this file is part of" linesPatrick Georgi
Stefan thinks they don't add value. Command used: sed -i -e '/file is part of /d' $(git grep "file is part of " |egrep ":( */\*.*\*/\$|#|;#|-- | *\* )" | cut -d: -f1 |grep -v crossgcc |grep -v gcov | grep -v /elf.h |grep -v nvramtool) The exceptions are for: - crossgcc (patch file) - gcov (imported from gcc) - elf.h (imported from GNU's libc) - nvramtool (more complicated header) The removed lines are: - fmt.Fprintln(f, "/* This file is part of the coreboot project. */") -# This file is part of a set of unofficial pre-commit hooks available -/* This file is part of coreboot */ -# This file is part of msrtool. -/* This file is part of msrtool. */ - * This file is part of ncurses, designed to be appended after curses.h.in -/* This file is part of pgtblgen. */ - * This file is part of the coreboot project. - /* This file is part of the coreboot project. */ -# This file is part of the coreboot project. -# This file is part of the coreboot project. -## This file is part of the coreboot project. --- This file is part of the coreboot project. -/* This file is part of the coreboot project */ -/* This file is part of the coreboot project. */ -;## This file is part of the coreboot project. -# This file is part of the coreboot project. It originated in the - * This file is part of the coreinfo project. -## This file is part of the coreinfo project. - * This file is part of the depthcharge project. -/* This file is part of the depthcharge project. */ -/* This file is part of the ectool project. */ - * This file is part of the GNU C Library. - * This file is part of the libpayload project. -## This file is part of the libpayload project. -/* This file is part of the Linux kernel. */ -## This file is part of the superiotool project. -/* This file is part of the superiotool project */ -/* This file is part of uio_usbdebug */ Change-Id: I82d872b3b337388c93d5f5bf704e9ee9e53ab3a9 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41194 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-02intel/stm: Drop now unneeded `num_cpus` paramEugene D Myers
Suggested by Nico Huber in CB:38766 Change-Id: Ib8a340f17a12951bc6bc67e3093046575e7b0e46 Signed-off-by: Eugene D Myers <cedarhouse@comcast.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40438 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-04-04src/cpu: Use SPDX for GPL-2.0-only filesAngel Pons
Done with sed and God Lines. Only done for C-like code for now. Change-Id: I2adf28d805fe248d55a9514f74c38280c0ad9a78 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40049 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2020-03-21cpu/x86: Fix typoSubrata Banik
CIRTICAL -> CRITICAL Change-Id: Ie2c1427b197dbfebdc7f0c6ffd85f768845ff1bd Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39671 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2020-02-17cpu/x86: Remove unnecessary guardEugene Myers
The is_smm_enabled is not necessary because it is done previously in this code path. Signed-off-by: Eugene D. Myers <edmyers@tycho.nsa.gov> Change-Id: I20d50acbea891cb56ad49edc128df25d21c5f1ca Reviewed-on: https://review.coreboot.org/c/coreboot/+/38820 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-02-17cpu/x86: Adjust STM smm_save_state_sizeEugene Myers
Initial testing of STM support revealed a sizing issue for greater than 4 threads. This patch reduces the STM smm_save_state_size, which should allow for 24 threads. Signed-off-by: Eugene D. Myers <edmyers@tycho.nsa.gov> Change-Id: I025694185469577e072a92ea75cbbb53c24b2c24 Reviewed-on: https://review.coreboot.org/c/coreboot/+/38819 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-02-06cpu/x86: Put guard around align for smm_save_state_sizeEugene Myers
The STM support aligns the smm_save_state_size. However, this creates issue for some platforms because of this value being hard coded to 0x400 Signed-off-by: Eugene D. Myers <edmyers@tycho.nsa.gov> Change-Id: Ia584f7e9b86405a12eb6cbedc3a2615a8727f69e Reviewed-on: https://review.coreboot.org/c/coreboot/+/38734 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: ron minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-02-05security/intel/stm: Add STM supportEugene Myers
This update is a combination of all four of the patches so that the commit can be done without breaking parts of coreboot. This possible breakage is because of the cross-dependencies between the original separate patches would cause failure because of data structure changes. security/intel/stm This directory contains the functions that check and move the STM to the MSEG, create its page tables, and create the BIOS resource list. The STM page tables is a six page region located in the MSEG and are pointed to by the CR3 Offset field in the MSEG header. The initial page tables will identity map all memory between 0-4G. The STM starts in IA32e mode, which requires page tables to exist at startup. The BIOS resource list defines the resources that the SMI Handler is allowed to access. This includes the SMM memory area where the SMI handler resides and other resources such as I/O devices. The STM uses the BIOS resource list to restrict the SMI handler's accesses. The BIOS resource list is currently located in the same area as the SMI handler. This location is shown in the comment section before smm_load_module in smm_module_loader.c Note: The files within security/intel/stm come directly from their Tianocore counterparts. Unnecessary code has been removed and the remaining code has been converted to meet coreboot coding requirements. For more information see: SMI Transfer Monitor (STM) User Guide, Intel Corp., August 2015, Rev 1.0, can be found at firmware.intel.com include/cpu/x86: Addtions to include/cpu/x86 for STM support. cpu/x86: STM Set up - The STM needs to be loaded into the MSEG during BIOS initialization and the SMM Monitor Control MSR be set to indicate that an STM is in the system. cpu/x86/smm: SMI module loader modifications needed to set up the SMM descriptors used by the STM during its initialization Change-Id: If4adcd92c341162630ce1ec357ffcf8a135785ec Signed-off-by: Eugene D. Myers <edmyers@tycho.nsa.gov> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33234 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: ron minnich <rminnich@gmail.com>
2020-02-04cpu/x86: Make MP init timeout configurableJonathan Zhang
The current MP init timeout is hardcoded as 1s. To support platform with many cpus, the timeout needs to be adjusted. The number of cpus is calculated as: number of sockets * number of cores per socket * number of threads per core How long the timeout should be set to, is heuristic. It needs to be set long enough to ensure reboot stability, but not unreasonable so that real failures can be detected soon enough, especially for smaller systems. This patch sets timeout to be minimum as 1 second, while each cpu adds 0.1 second. Signed-off-by: Jonathan Zhang <jonzhang@fb.com> Signed-off-by: Reddy Chagam <anjaneya.chagam@intel.com> Change-Id: Ibc079fc6aa8641d4ac8d8e726899b6c8d055052e Reviewed-on: https://review.coreboot.org/c/coreboot/+/38546 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2019-12-18cpu/x86/mp_init: Fix typoElyes HAOUAS
Change-Id: Iee9cd3dc51937774b990bc6f9e00bb82e0132e76 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37811 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-10AUTHORS: Move src/cpu copyrights into AUTHORS fileMartin Roth
As discussed on the mailing list and voted upon, the coreboot project is going to move the majority of copyrights out of the headers and into an AUTHORS file. This will happen a bit at a time, as we'll be unifying license headers at the same time. Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: Id6070fb586896653a1e44951a6af8f42f93b5a7b Reviewed-on: https://review.coreboot.org/c/coreboot/+/35184 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-08-15soc/*: mp_run_on_all_cpus: Remove configurable timeoutPatrick Rudolph
Some timeouts given were too small when serial console is enabled due to its spinlock making code runtime worse with every AP present. In addition we usually don't know how long specific code runs and how long ago it was sent to the APs. Remove the timeout argument from mp_run_on_all_cpus and instead wait up to 1 second, to prevent possible crashing of secondary APs still processing the old job. Tested on Supermicro X11SSH-TF. Change-Id: I456be647b159f7a2ea7d94986a24424e56dcc8c4 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34587 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
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