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path: root/src/cpu/x86/lapic
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2014-02-11SMP: Add arch-agnostic boot_cpu()Kyösti Mälkki
We should not have x86 specific includes in lib/. Change-Id: I18fa9c8017d65c166ffd465038d71f35b30d6f3d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5156 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-01-28x86: add common definitions for control registersAaron Durbin
The access to control registers were scattered about. Provide a single header file to provide the correct access function and definitions. BUG=chrome-os-partner:22991 BRANCH=None TEST=Built and booted using this infrastructure. Also objdump'd the assembly to ensure consistency (objdump -d -r -S | grep xmm). Change-Id: Iff7a043e4e5ba930a6a77f968f1fcc14784214e9 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/172641 Reviewed-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/4873 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2013-11-22Don't wait on 2065xVladimir Serbinenko
The mdelay is not necessarry on 2065x. Tested on X201 that it works without delay. Change-Id: Ida9e85be7c214f3ba4c9476b5d8a0351e7980e5e Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/4083 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2013-10-13Rename cpu/x86/car.h to arch/early_variables.hStefan Reinauer
and add an ARMv7 version. Change-Id: I14fbff88d7c2b003dde57a19bf0ba9640d322156 Signed-off-by: Stefan Reinauer <reinauer@google.com> [km: rebased fa004acf8 from chromium git] Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3939 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2013-08-15Include boot_cpu.c for romstage buildsKyösti Mälkki
ROMCC boards were left unmodified. Change-Id: I3d842196b3f5b6999b6891b914036e9ffcc3cef0 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3853 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-07-22X86: make the SIPI num_starts a config variableRonald G. Minnich
The code to figure out how to set num_starts was starting to get kludgy. It's a constant for a given CPU; constants should be constant; make it a config variable. This change includes an example of how to override it. Build but not boot tested; drivers welcome. Change-Id: Iddd906a707bb16251615c7b42f2bfb5a044379b4 Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: http://review.coreboot.org/3796 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com> Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
2013-07-11cpu: Fix spellingMartin Roth
Change-Id: I69c46648de0689e9bed84c7726906024ad65e769 Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/3729 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-05-14x86: add thread supportAaron Durbin
Thread support is added for the x86 architecture. Both the local apic and the tsc udelay() functions have a call to thread_yield_microseconds() so as to provide an opportunity to run pending threads. Change-Id: Ie39b9eb565eb189676c06645bdf2a8720fe0636a Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/3207 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-05-01lapic: monotonic time implementationAaron Durbin
Implement the timer_monotonic_get() functionality based off of the local apic timer. Change-Id: I1aa1ff64d15a3056d6abd1372be13da682c5ee2e Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/3154 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-21ramstage: prepare for relocationAaron Durbin
The current ramstage code contains uses of symbols that cause issues when the ramstage is relocatable. There are 2 scenarios resolved by this patch: 1. Absolute symbols that are actually sizes/limits. The symbols are problematic when relocating a program because there is no way to distinguish a symbol that shouldn't be relocated and one that can. The only way to handle these symbols is to write a program to post process the relocations and keep a whitelist of ones that shouldn't be relocated. I don't believe that is a route that should be taken so fix the users of these sizes/limits encoded as absolute symbols to calculate the size at runtime or dereference a variable in memory containing the size/limit. 2. Absoulte symbols that were relocated to a fixed address. These absolute symbols are generated by assembly files to be placed at a fixed location. Again, these symbols are problematic because one can't distinguish a symbol that can't be relocated. The symbols are again resolved at runtime to allow for proper relocation. For the symbols defining a size either use 2 symbols and calculate the difference or provide a variable in memory containing the size. Change-Id: I1ef2bfe6fd531308218bcaac5dcccabf8edf932c Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/2789 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2013-03-18haswell: lapic timer supportAaron Durbin
Haswell's BCLK is fised at 100MHz like Sandy/Ivy. Add Haswell's model to the switch statement. Change-Id: Ib9e2afc04eba940bfcee92a6ee5402759b21cc45 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/2747 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-01GPLv2 notice: Unify all files to just use one space in »MA 02110-1301«Paul Menzel
In the file `COPYING` in the coreboot repository and upstream [1] just one space is used. The following command was used to convert all files. $ git grep -l 'MA 02' | xargs sed -i 's/MA 02/MA 02/' [1] http://www.gnu.org/licenses/gpl-2.0.txt Change-Id: Ic956dab2820a9e2ccb7841cab66966ba168f305f Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/2490 Tested-by: build bot (Jenkins) Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
2013-02-11Intel: Replace MSR 0xcd with MSR_FSB_FREQPatrick Georgi
And move the corresponding #define to speedstep.h Change-Id: I8c884b8ab9ba54e01cfed7647a59deafeac94f2d Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/2339 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-12-06Unify assembler function handlingStefan Reinauer
Instead of adding regparm(0) to each assembler function called by coreboot, add an asmlinkage macro (like the Linux kernel does) that can be different per architecture (and that is empty on ARM right now) Change-Id: I7ad10c463f6c552f1201f77ae24ed354ac48e2d9 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1973 Reviewed-by: David Hendricks <dhendrix@chromium.org> Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-27Remove AMD special case for LAPIC based udelay()Patrick Georgi
- Optionally override FSB clock detection in generic LAPIC code with constant value. - Override on AMD Model fxx, 10xxx, agesa CPUs with 200MHz - compile LAPIC code for romstage, too - Remove #include ".../apic_timer.c" in AMD based mainboards - Remove custom udelay implementation from intel northbridges' romstages Future work: - remove the compile time special case (requires some cpuid based switching) - drop northbridge udelay implementations (i945, i5000) if not required anymore (eg. can SMM use the LAPIC timer?) Change-Id: I25bacaa2163f5e96ab7f3eaf1994ab6899eff054 Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com> Reviewed-on: http://review.coreboot.org/1618 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-11-20secondary.S: Fix dropping ramstage.aStefan Reinauer
This unused code was not silently dropped as before. Change-Id: Ic76c58e233869a60c3a8a27c2efc2182b3a4442d Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1863 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-13Clean up stack checking codeStefan Reinauer
Several small improvements of the stack checking code: - move the CPU0 stack check right before jumping to the payload and out of hardwaremain (that file is too crowded anyways) - fix prototype in lib.h - print size of used stack - use checkstack function both on CPU0 and CPU1-x - print amount of stack used per core Signed-off-by: Stefan Reinauer <reinauer@google.com> Test: Boot coreboot on Link, see the following output: ... CPU1: stack: 00156000 - 00157000, lowest used address 00156c68, stack used: 920 bytes CPU2: stack: 00155000 - 00156000, lowest used address 00155c68, stack used: 920 bytes CPU3: stack: 00154000 - 00155000, lowest used address 00154c68, stack used: 920 bytes ... Jumping to boot code at 1110008 CPU0: stack: 00157000 - 00158000, lowest used address 00157af8, stack used: 1288 bytes Change-Id: I7b83eeee0186559a0a62daa12e3f7782990fd2df Reviewed-on: http://review.coreboot.org/1787 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-13clean up lapic_cpu_init.cStefan Reinauer
- drop changelog and add license header instead - 80+ character fixes - make stacks array static because it's not used externally - rename copy_secondary_start_to_1m_below() Change-Id: I8b461bea21ee0ddd85ea3a3a923d1e15167f54f0 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1821 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-13Pass the CPU index as a parameter to startup.Ronald G. Minnich
This addition is in support of future multicore support in coreboot. It also will allow us to remove some asssembly code. The CPU "index" -- i.e., its order in the sequence in which cores are brought up, NOT its APIC id -- is passed into the secondary start. We modify the function to specify regparm(0). We also take this opportunity to do some cleanup: indexes become unsigned ints, not unsigned longs, for example. Build and boot on a multicore system, with pcserial enabled. Capture the output. Observe that the messages Initializing CPU #0 Initializing CPU #1 Initializing CPU #2 Initializing CPU #3 appear exactly as they do prior to this change. Change-Id: I5854d8d957c414f75fdd63fb017d2249330f955d Signed-off-by: Ronald G. Minnich <rminnich@chromium.org> Reviewed-on: http://review.coreboot.org/1820 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2012-11-13Support better tracking of AP stack usage.Ronald G. Minnich
This change allows us to figure out how much of the AP stacks we are using, as well as to catch any case of an AP overrunning its stack. Also, the stack is poisoned, which is a good way to catch programming errors -- code should never count on auto variables being zerod. The stack bases are recorded in a new array, stacks. At the end, when all APs are initialized, the stacks are walked and the lowest level of the stack that is reached is printed. Build and boot and look for output like this: CPU1: stack allocated from 00148000 to 00148ff4:\ lowest stack address was 00148c4c CPU2: stack allocated from 00147000 to 00147ff4:\ lowest stack address was 00147c4c CPU3: stack allocated from 00146000 to 00146ff4:\ lowest stack address was 00146c4c Note that we used only about 1K of stack, even though in this case we allocated 4K (and in the main branch, we allocate 32K!) Change-Id: I99b7b9086848496feb3ecd207f64203fa69fadf5 Signed-off-by: Ronald G. Minnich <rminnich@chromium.org> Reviewed-on: http://review.coreboot.org/1818 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins)
2012-11-12Fix gcc-4.7 building problem.Han Shen
Applied function attribute to function definition to avoid 'conflicting type' warning. Function declaration is in src/include/cpu.h void secondary_cpu_init(unsigned int cpu_index)__attribute__((regparm(0))); But function definition in lapic_cpu_init.c is missing the "__attribute__" part. Change-Id: Idb7cd00fda5a2d486893f9866920929c685d266e Signed-off-by: Han Shen <shenhan@google.com> Reviewed-on: http://review.coreboot.org/1784 Tested-by: build bot (Jenkins) Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
2012-08-07Move cpus_ready_for_init() to AMD K8Kyösti Mälkki
The function is a noop for all but amd/serengeti_cheetah. Change-Id: I09e2e710aa964c2f31e35fcea4f14856cc1e1dca Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/1184 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2012-07-31Revert "Use broadcast SIPI to startup siblings"Sven Schnelle
This reverts commit 042c1461fb777e583e5de48edf9326e47ee5595f. It turned out that sending IPIs via broadcast doesn't work on Sandybridge. We tried to come up with a solution, but didn't found any so far. So revert the code for now until we have a working solution. Change-Id: I7dd1cba5a4c1e4b0af366b20e8263b1f6f4b9714 Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/1381 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-07-25Fix LAPIC timer on Ivy Bridge systemsStefan Reinauer
The LAPIC timer is running at BCLK (100MHz) on Sandy Bridge and Ivy Bridge systems. However, the current timer code assumed that the clock would run at 200MHz instead. This made all delays twice as long as needed. Change-Id: I41b1186daee11cfd9a25b3a9d5ebdeeb271293c7 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1330 Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Tested-by: build bot (Jenkins)
2012-07-23Re-initialize Local APIC timer on APsStefan Reinauer
In order to be able to use udelay in code running on AP cores the timer has to be initialized on the according local APICs or the system will just hang when udelay is used. Change-Id: I776bc96aa6d876ff2582d0c05cbc9c7611cb06b5 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1267 Tested-by: build bot (Jenkins) Reviewed-by: Sven Schnelle <svens@stackframe.org>
2012-07-12Fix stack assignment during CPU initializationSven Schnelle
There are two errors in the code. The first one is a missing $ sign in mov _stack, %esp. Thanks to Ronald G Minnich for catching that bug. The second bug is the 'incl %eax', which shouldn't be there, as there's no secondary CPU with index 0. CPU0 uses always the stack below _estack. Change-Id: Id267a654ba95b0e898eeaaafb2403b438250a563 Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/1212 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2012-07-05Only copy real-mode section of SIPI vectorKyösti Mälkki
The SIPI vector copy can use a static location below 1MB, aligned to 4kB. Jump out of the copy once in protected mode. Change-Id: I6299aa3448270663941cf2c4113efee74bcc7993 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/1165 Tested-by: build bot (Jenkins) Reviewed-by: Sven Schnelle <svens@stackframe.org>
2012-07-05Fix the CPU index parameter passed to secondary_cpu_init().Kyösti Mälkki
Count 0,1,2,3,... instead of 0,2,3,4,... Change-Id: I3c6b85e5e71b32deac5470809e1618d28f19c00f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/1173 Tested-by: build bot (Jenkins) Reviewed-by: Sven Schnelle <svens@stackframe.org>
2012-07-02Use broadcast SIPI to startup siblingsSven Schnelle
The current code for initializing AP cpus has several shortcomings: - it assumes APIC IDs are sequential - it uses only the BSP for determining the AP count, which is bad if there's more than one physical CPU, and CPUs are of different type Note that the new code call cpu->ops->init() in parallel, and therefore some CPU code needs to be changed to address that. One example are old Intel HT enabled CPUs which can't do microcode update in parallel. Change-Id: Ic48a1ebab6a7c52aa76765f497268af09fa38c25 Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/1139 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-06-12udelay: add missing bus frequencySven Schnelle
commit 5b6404e4195157eac8d97ae5bf30f45612109d57 ("Fix timer frequency detection on Sandybridge") reworked the udelay code, but didn't add the 333MHz FSB entry used on Model 15 Xeons. Change-Id: Ie34f9ae3703b64672625e7bf1b943654a7a5eaa6 Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/1099 Tested-by: build bot (Jenkins)
2012-05-08Clean up #ifsPatrick Georgi
Replace #if CONFIG_FOO==1 with #if CONFIG_FOO: find src -name \*.[ch] -exec sed -i "s,#if[[:space:]]*\(CONFIG_[A-Z0-9_]*\)[[:space:]]*==[[:space:]]*1[[:space:]]*\$,#if \1," {} + Replace #if (CONFIG_FOO==1) with #if CONFIG_FOO: find src -name \*.[ch] -exec sed -i "s,#if[[:space:]]*(\(CONFIG_[A-Z0-9_]*\)[[:space:]]*==[[:space:]]*1)[[:space:]]*\$,#if \1," {} + Replace #if CONFIG_FOO==0 with #if !CONFIG_FOO: find src -name \*.[ch] -exec sed -i "s,#if[[:space:]]*\(CONFIG_[A-Z0-9_]*\)[[:space:]]*==[[:space:]]*0[[:space:]]*\$,#if \!\1," {} + Replace #if (CONFIG_FOO==0) with #if !CONFIG_FOO: find src -name \*.[ch] -exec sed -i "s,#if[[:space:]]*(\(CONFIG_[A-Z0-9_]*\)[[:space:]]*==[[:space:]]*0)[[:space:]]*\$,#if \!\1," {} + (and some manual changes to fix false positives) Change-Id: Iac6ca7605a5f99885258cf1a9a2473a92de27c42 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/1004 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Martin Roth <martin@se-eng.com>
2012-04-11Remove obsolete empy macro definitionRon Minnich
In the early days of v2 the (e.g.) #ifdef SMP style was frowned upon in some quarters. Hence, empty definitions of functions were created. This particular function, possibly the last remaining example, was no longer even being used anywhere. Signed-off-by: Ron Minnich <rminnich@gmail.com>
2012-04-06Fixes and Sandybridge support for lapic cpu initStefan Reinauer
- preprocessor macros should not use defined(CONFIG_*) but just CONFIG_* - drop AMD CPU model 14XXX config variable use. Those do not exist. - skip some delays on Sandybridge systems - Count how long we're waiting for each AP to stop - Skip speedstep specific CPU entries Change-Id: I13db384ba4e28acbe7f0f8c9cd169954b39f167d Signed-off-by: Stefan Reinauer <reinauer@google.com> Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: http://review.coreboot.org/871 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2012-04-05Fix timer frequency detection on SandybridgeStefan Reinauer
Change-Id: Ide720bd91cde56a0afdd231d93500c371b1ffbe8 Signed-off-by: Duncan Laurie <dlaurie@google.com> Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/870 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins)
2012-03-30drop use of MAX_PHYSICAL_CPUS and MAX_CPUS where not neededStefan Reinauer
Change-Id: Idf875ddec417e627f1e72a6d834860e7fd324a50 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/760 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-03-30Add an option to keep the ROM cached after romstageStefan Reinauer
Change-Id: I05f1cbd33f0cb7d80ec90c636d1607774b4a74ef Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/739 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-03-25Fix possible deadlock on SMP stop_this_cpuKyösti Mälkki
Do not use printk on the running thread after it has been sent the INIT IPI, execution may halt with console spinlock held. Change-Id: I64608935ea740fb827fa0307442f3fb102de7a08 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/776 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins) Reviewed-by: Rudolf Marek <r.marek@assembler.cz>
2012-03-07Move C labels to start-of-linePatrick Georgi
Also mark the corresponding lint test stable. Change-Id: Ib7c9ed88c5254bf56e68c01cdbd5ab91cd7bfc2f Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/772 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-12-05Bootblock does not need a unique boot_cpu()Kyösti Mälkki
Detection of a CPU being a BSP CPU is not dependent of the existence of northbridge and/or southbridge init code in the bootblock. Even if CONFIG_LOGICAL_CPUS==0, boot_cpu() can get executed on an AP CPU of a hyper-threading CPU and needs to return actual BSP bit from MSR. Change-Id: I9187f954bb357ba1dbd459cfe11cc96cb7567968 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/447 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-11-01remove trailing whitespaceStefan Reinauer
Change-Id: Ib91889a374515d36a2b12b53aeb12b6ea6e22732 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/364 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-07-22Add SSE3 dependent codeefdesign98
This change separates out changes that were initially found in the commit for XHCI and AHCI changes to "arch/x86/Makefile. inc". It also corrects a comment. The SSE3 dependent code adds a pair of CR4 access functions and a blob of code that re-sets CR4.OSFXSR and CR4.OSXMMEXCPT. Change-Id: Id97256978da81589d97dcae97981a049101b5258 Signed-off-by: Frank Vibrans <frank.vibrans@amd.com> Signed-off-by: efdesign98 <efdesign98@gmail.com> Reviewed-on: http://review.coreboot.org/113 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-05-10This replaces the fixed shift values in the apic timer init with macros.Vikram Narayanan
Signed-off-by: Vikram Narayanan <vikram186@gmail.com> Acked-by: Patrick Georgi <patrick@georgi-clan.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6564 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-22Printing coreboot debug messages on VGA console is pretty much useless, sinceStefan Reinauer
initializing VGA happens pretty much as the last thing before starting the payload. Hence, drop VGA console support, as we did in coreboot v3. - Drop VGA and BTEXT console support. Console is meant to be debugging only, and by the time graphics comes up 99% of the risky stuff has already happened. Note: This patch does not remove hardware init but only the actual output functionality. The ragexl driver needs some extra love, but that's for another day - factor out die() and post() - drop some leftover RAMBASE < 0x100000 checks. Signed-off-by: Stefan Reinauer <stepan@coreboot.org> Acked-by: QingPei Wang<wangqingpei@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6111 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-19To reduce boot time, remove the double startup IPI and 10 ms delay from ↵Scott Duplichan
lapic_cpu_init.c. The change is currently restricted to recent model AMD processors, though it could be applied to others after successful testing. Signed-off-by: Scott Duplichan <scott@notabs.org> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5967 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-09-30Rename build system variables to be more intuitive, andPatrick Georgi
at the same time let the user specify sources instead of object files: - objs becomes ramstage-srcs - initobjs becomes romstage-srcs - driver becomes driver-srcs - smmobj becomes smm-srcs The user servicable parts are named accordingly: ramstage-y, romstage-y, driver-y, smm-y Also, the object file names are properly renamed now, using .ramstage.o, .romstage.o, .driver.o, .smm.o suffixes consistently. Remove stubbed out via/epia-m700 dsdt/ssdt files - they didn't easily fit in the build system and aren't useful anyway. Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de> Acked-by: Stefan Reinauer <stepan@coreystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5886 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-04-27Since some people disapprove of white space cleanups mixed in regular commitsStefan Reinauer
while others dislike them being extra commits, let's clean them up once and for all for the existing code. If it's ugly, let it only be ugly once :-) Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5507 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-04-25drop "arch/asm.h" and "arch/intel.h" and create "cpu/x86/post_code.h"Stefan Reinauer
(which could at some time hold global post code definitions, too) Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5498 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-03-22printk_foo -> printk(BIOS_FOO, ...)Stefan Reinauer
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5266 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-03-01- Simplify stack size determination: MAX_CPUS * STACK_SIZEPatrick Georgi
- Check that this doesn't run into vga/oprom/bios area at link time - Avoid overly complicated and not well understood hack which avoids that area by leaving a hole in the stack area. - Adapt technexion/tim5690 to put ramstage at 1MB Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5181 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-02-20trival. All the changes is about comment and spaces.Zheng Bao
1. Delete trailing white spaces. 2. Change the // comment to /* */. 3. Add some copyright header. 4. reindent. 5. delete multi blank lines. Signed-off-by: Zheng Bao <zheng.bao@amd.com> Acked-by: Zheng Bao <zheng.bao@amd.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5133 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-02-07newconfig is no more.Patrick Georgi
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5089 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-01-04- use LAPIC timer if selected (instead of TSC all the time) [kconfig]Patrick Georgi
- uncomment commented out intel socket [kconfig] - HAVE_MOVNTI is a property of the cpu [kconfig] Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4996 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-30Remove some warnings from the tyan s2895.Myles Watson
Declare superio functions to be static and remove duplicates. Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4890 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-16Change CONFIG_LB_MEM_TOPK to CONFIG_RAMTOP to match CONFIG_RAMBASE.Myles Watson
Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4788 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-09-29Remove some warnings.Myles Watson
Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4686 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-08-12Kconfig!Patrick Georgi
Works on Kontron, qemu, and serengeti. Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de> tested on abuild only. Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4534 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-07-21this bug sneaked in during conversionStefan Reinauer
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4457 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-07-21* rework tsc based timer code to use inb instead of outb for calibrationStefan Reinauer
* Add generic Local APIC based timer code. This timer does not need expensive calibration and thus reduces the boot time by up to more than a second. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Peter Stuge <peter@stuge.se> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4446 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-06-30This patch unifies the use of config options in v2 to all start with CONFIG_Stefan Reinauer
It's basically done with the following script and some manual fixup: VARS=`grep ^define src/config/Options.lb | cut -f2 -d\ | grep -v ^CONFIG | grep -v ^COREBOOT |grep -v ^CC` for VAR in $VARS; do find . -name .svn -prune -o -type f -exec perl -pi -e "s/(^|[^0-9a-zA-Z_]+)$VAR($|[^0-9a-zA-Z_]+)/\1CONFIG_$VAR\2/g" {} \; done Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4381 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-30Remove warnings from compilation of the s2892 with and without CBFS.Myles Watson
I didn't try to remove "defined but not used" warnings because there are too many ifdefs to be sure I wouldn't break something. For shadowed variable declarations I renamed the inner-most variable. The one in src/pc80/keyboard.c might need help. I didn't change the functionality but it looks like a bug. I boot tested it on s2892 and abuild tested it. Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4240 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-13Following patch adds necessary hooks and as well the compile time checks forRudolf Marek
ACPI suspend/resume. The memory cleared now is just the coreboot memory not the low memory. Signed-off-by: Rudolf Marek <r.marek@assembler.cz> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4099 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-03drop another shadow variable (trivial)Stefan Reinauer
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4056 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-03-06fix a bunch of cast and type warnings and don't call the apic "nvram", thatStefan Reinauer
doesn't make no sense. (trivial) Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3977 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-03-04I just went on a bugfix frenzy and fixed all printk format warningsCarl-Daniel Hailfinger
triggered by the AMD 690/SB600 targets. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3970 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-02-28coreboot-v2: drop this ugly historic union name in v2 that was dropped in v3Stefan Reinauer
a long time ago. This will make it easier to port v2 boards forward to v3 at some point (and other things) Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3964 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-02-09Remove some warnings, mainly from format strings which didn't match theMyles Watson
arguments. Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3931 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-12-18This patch gets rid of all the implicit definition warnings for serengeti ↵Myles Watson
except get_nodes. Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Marc Jones <marcj303@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3818 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-10-29Support for Intel Core Duo and Core 2 Duo (tm) CPUs.Stefan Reinauer
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3702 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-02Go back to SIPI WAIT state for those CPUS defining the newly introducedStefan Reinauer
CONFIG_AP_IN_SIPI_WAIT flag. Newer Intel CPUs need this to operate with multiple cores. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3465 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-01-18Rename almost all occurences of LinuxBIOS to coreboot. Stefan Reinauer
Due to the automatic nature of this update, I am self-acking. It worked in abuild. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3053 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-10-04AMD Rev F supportYinghai Lu
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2435 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-05-18init the ECC for BSP and AP at the same time. So reduce init cpus timeYinghai Lu
from 2.1x to 1.1x or from 4x(SERIAL_CPU_INIT) to 1.1x git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2309 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-04-03new cache_as_ram support Yinghai Lu
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2232 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-01-09don't need copy_secondary_start_to_1m_below for non-smpYinghai Lu
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2158 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-01-041M boundary for _RAMBASE=1M, and CONFIG_LB_TOPK 8M above supportYinghai Lu
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2152 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2005-12-14issue 51 and 52: set mtrr for ap before stop it, and _RAMBASE above 1MYinghai Lu
support and pgtbl after 1M support git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2142 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2005-12-021201_ht_bus0_dev0_fidvid_core.diffStefan Reinauer
https://openbios.org/roundup/linuxbios/issue41 Lord have mercy upon us. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2118 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2005-09-12Fix hang during secondary CPU sibling init caused by nested spinlocks.Steven J. Magnani
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2022 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2005-07-06Revision: linuxbios@linuxbios.org--devel/freebios--devel--2.0--patch-51arch import user (historical)
Creator: Yinghai Lu <yhlu@tyan.com> cache_as_ram for AMD and some intel git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1967 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2005-07-06Revision: linuxbios@linuxbios.org--devel/freebios--devel--2.0--patch-34arch import user (historical)
Creator: Yinghai Lu <yhlu@tyan.com> AMD D0/E0 Opteron new mem mapping support, AMD E Opteron mem hole support,AMD K8 Four Ranks DIMM support git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1950 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2005-01-03serialize cpus for >2Yinghai Lu
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1837 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-11-18- First stab at getting the ppc ports building and working.Eric Biederman
- The sandpointx3+altimus has been consolidated into one directory for now. - Added support for having different versions of the pci access functions on a per bus basis if needed. Hopefully I have not broken something inadvertently. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1786 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-11-04tell people that the segment descriptors are different for ROMCC andLi-Ta Lo
GCC code. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1740 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-30- To reduce confuse rename the parts of linuxbios bios that run fromEric Biederman
ram linuxbios_ram instead of linuxbios_c and linuxbios_payload... - Reordered the linker sections so the LinuxBIOS fallback image can take more the 64KiB on x86 - ROM_IMAGE_SIZE now will work when it is specified as larger than 64KiB. - Tweaked the reset16.inc and reset16.lds to move the sanity check to see if everything will work. - Start using romcc's built in preprocessor (This will simplify header compiler checks) - Add helper functions for examining all of the resources - Remove debug strings from chip.h - Add llshell to src/arch/i386/llshell (Sometime later I can try it...) - Add the ability to catch exceptions on x86 - Add gdb_stub support to x86 - Removed old cpu options - Added an option so we can detect movnti support - Remove some duplicate definitions from pci_ids.h - Remove the 64bit resource code in amdk8/northbridge.c in preparation for making it generic - Minor romcc bug fixes git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1727 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-29Changes to allow Via/Epia code to be compiled after recent code changes.Mark Wilkinson
New Files :- src/cpu/via/model_centaur/Config.lb src/cpu/via/model_centaur/model_centaur_init.c Updated Files :- src/arch/i386/include/arch/smp/mpspec.h - make write_smp_table a define for non smp systems src/cpu/x86/lapic/lapic_cpu_init.c - change possible typo src/mainboard/via/epia/Config.lb src/mainboard/via/epia/Options.lb src/mainboard/via/epia/auto.c src/mainboard/via/epia/chip.h src/mainboard/via/epia/failover.c - updated after recent code changes src/northbridge/via/vt8601/chip.h src/northbridge/via/vt8601/northbridge.c src/northbridge/via/vt8601/raminit.c - corrections after recent code changes to allow compiling src/southbridge/via/vt8231/chip.h src/southbridge/via/vt8231/vt8231.c - initial pass to allow compiling after recent code changes. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1726 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-16- HDAMA boots!Eric Biederman
- Set the bootstrap processor flag in the mptable. - Implement 64bit support in our print statements - Fix the reporting of how many cpus we are waiting to stop. It is the 1 less than the actual number of cpus running. - Actually enable cpu_initialization. - Fix firstsiblingdevice in config.g - Add IORESOURCE_FIXED to all of the resources set by config.g - Fix the apic_cluster rule to add an apic_cluster path not an apic path. - Add a div64.h to assist in the 64bit printf. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1682 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-16- First stab at running linuxbios without the old static device tree.Eric Biederman
Things are close but not quite there yet. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1681 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-14- Add new cvs code to cvsEric Biederman
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1657 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-13 06:26:11 +0000