coreboot.git - my copy of coreboot

Age	Commit message (Expand)	Author
2008-08-02	Go back to SIPI WAIT state for those CPUS defining the newly introduced	Stefan Reinauer
2008-01-18	Rename almost all occurences of LinuxBIOS to coreboot.	Stefan Reinauer
2006-10-04	AMD Rev F support	Yinghai Lu
2006-05-18	init the ECC for BSP and AP at the same time. So reduce init cpus time	Yinghai Lu
2006-04-03	new cache_as_ram support	Yinghai Lu
2006-01-09	don't need copy_secondary_start_to_1m_below for non-smp	Yinghai Lu
2006-01-04	1M boundary for _RAMBASE=1M, and CONFIG_LB_TOPK 8M above support	Yinghai Lu
2005-12-14	issue 51 and 52: set mtrr for ap before stop it, and _RAMBASE above 1M	Yinghai Lu
2005-12-02	1201_ht_bus0_dev0_fidvid_core.diff	Stefan Reinauer
2005-09-12	Fix hang during secondary CPU sibling init caused by nested spinlocks.	Steven J. Magnani
2005-07-06	Revision: linuxbios@linuxbios.org--devel/freebios--devel--2.0--patch-51	arch import user (historical)
2005-07-06	Revision: linuxbios@linuxbios.org--devel/freebios--devel--2.0--patch-34	arch import user (historical)
2005-01-03	serialize cpus for >2	Yinghai Lu
2004-11-18	- First stab at getting the ppc ports building and working.	Eric Biederman
2004-11-04	tell people that the segment descriptors are different for ROMCC and	Li-Ta Lo
2004-10-30	- To reduce confuse rename the parts of linuxbios bios that run from	Eric Biederman
2004-10-29	Changes to allow Via/Epia code to be compiled after recent code changes.	Mark Wilkinson
2004-10-16	- HDAMA boots!	Eric Biederman
2004-10-16	- First stab at running linuxbios without the old static device tree.	Eric Biederman
2004-10-14	- Add new cvs code to cvs	Eric Biederman