coreboot.git - my copy of coreboot

Age	Commit message (Expand)	Author
2020-06-23	src/*: Update makefiles to exclude x86 code from psp-verstage	Martin Roth
2019-12-11	AGESA, binaryPI: implement C bootblock	Michał Żygowski
2018-08-03	cpu/x86/lapic/apic_timer.c: Compile the same code for all stages	Arthur Heymans
2017-08-19	arch/x86: Clean up CONFIG_SMP and MAX_CPUS test	Kyösti Mälkki
2016-03-23	arch/x86: introduce postcar stage/phase	Aaron Durbin
2016-01-21	*/Makefile.inc: Compile files needed by uart8250 in x86 bootblock	Alexandru Gagniuc
2015-10-14	x86: add standalone verstage support	Aaron Durbin
2015-07-06	Revert "sandy/ivybridge: use LAPIC timer in SMM"	Patrick Georgi
2015-07-02	sandy/ivybridge: use LAPIC timer in SMM	Stefan Reinauer
2013-08-15	Include boot_cpu.c for romstage builds	Kyösti Mälkki
2012-11-27	Remove AMD special case for LAPIC based udelay()	Patrick Georgi
2012-03-30	Add an option to keep the ROM cached after romstage	Stefan Reinauer
2010-09-30	Rename build system variables to be more intuitive, and	Patrick Georgi
2010-01-04	- use LAPIC timer if selected (instead of TSC all the time) [kconfig]	Patrick Georgi
2009-08-12	Kconfig!	Patrick Georgi