| Age | Commit message (Expand) | Author |
|---|---|---|
| 2024-11-21 | cpu/via/c7: Compress ramstage with LZ4 by default | Nico Huber |
| 2024-11-11 | cpu/via: Implement cache as RAM | Nico Huber |
| 2024-11-11 | via: Start template for VIA C7 w/ CX700 northbridge | Nico Huber |
| 2018-05-31 | Remove VIA C7 CPU support | Kyösti Mälkki |
| 2016-03-10 | cpu/via/c7: Don't manually include udelay_io.c | Stefan Reinauer |
| 2015-01-27 | vboot2: add verstage | Stefan Reinauer |
| 2014-07-05 | Drop redundant select CACHE_AS_RAM | Kyösti Mälkki |
| 2014-05-06 | Introduce stage-specific architecture for coreboot | Furquan Shaikh |
| 2014-05-03 | Move ARCH_* from board/Kconfig to cpu or soc Kconfig. | Furquan Shaikh |
| 2012-02-09 | VIA cpus: apply un-written naming rules | Kyösti Mälkki |
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index : coreboot.git | |
| my copy of coreboot | User & |
| summaryrefslogtreecommitdiff |