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2015-05-053rdparty: move to 3rdparty/blobsPatrick Georgi
There's now room for other repositories under 3rdparty. Change-Id: I51b02d8bf46b5b9f3f8a59341090346dca7fa355 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/10109 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-05-053rdparty: Move to blobsPatrick Georgi
To move 3rdparty to 3rdparty/blobs (ie. below itself from git's broken perspective), we need to work around it - since some git implementations don't like the direct approach. Change-Id: I1fc84bbb37e7c8c91ab14703d609a739b5ca073c Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/10108 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-08-26armv7: Move Exynos from 'cpu' to 'soc'.Hung-Te Lin
The Exynos family and most ARM products are SoC, not just CPU. We used to put ARM code in src/cpu to avoid polluting the code base for what was essentially an experiment at the time. Now that it's past the experimental phase and we're going to see more SoCs (including intel/baytrail) in coreboot. Change-Id: I5ea1f822664244edf5f77087bc8018d7c535f81c Reviewed-on: https://chromium-review.googlesource.com/170891 Tested-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Ronald Minnich <rminnich@chromium.org> Commit-Queue: Hung-Te Lin <hungte@chromium.org> (cherry picked from commit c8bb8fe0b20be37465f93c738d80e7e43033670a) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6739 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-08-25intel/gma: Clarify code and use dedicated init for Google PeppyRonald G. Minnich
Peppy had some issues with FUI. We decided it was time to create peppy-specific gma.c and i915io.c files. Using yabel and the i915tool, we generated a replay attack, then interpolated against the slippy i915io.c to get something working. Also, in preparation for moving code out of the mainboard gma.c to generic driver code, we got rid of some hardcodes in the mainboard gma.c that have no business being there. The worst were the computation of gmch_[m,n] and it turns out that we had some long-standing bugs related to confusion about 'bpp'. I've killed the word bpp everywhere I could because there are at least 3 things that correspond to bpp. We now have framebuffer, pipe, and panel bpp. The names are long because I want to avoid all the mistakes we've all been making in the last year :-) Sadly, that means a lot of changes not just peppy-related, but they are simple and in a good cause. The test pattern generation is driven by a global variable in mainboard/peppy/gma.c. I've found in the past that it's very useful to have a function like this available, as one can activate it while using a jtag debugger: halt at the right place in ramstage, set the variable to 1, continue. It's not enough code to worry about always including. The last hard-codes for M and N registers are gone, and the function to set from generic intel_dp.c code works. To avoid screen trash on a dev mode boot, which we liked but nobody else did :-), we now take the time to put a pleasing background color that sort of doubles as a power LED. Rough timing is ramstage start is at 2.2, and dev setup is done at 3.3. These new platforms are depressingly slow to boot. Rom init alone is taking 1.9 seconds. 13 years ago it was 3 seconds from power on to bash prompt. These CPUs are at least 10x faster and take much longer to get going. Future work, once we get this through, is to move more functions to the intel driver, and combine the mainboard i915io.c into the mainboard gma.c. That separation only existed because i915io.c was generated by a tool, and it had lots of ugliness. Most ugliness is gone. Old-Change-Id: I6a6295b423a41e263f82cef33eacb92a14163321 Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: https://chromium-review.googlesource.com/170013 Reviewed-by: Stefan Reinauer <reinauer@google.com> Commit-Queue: Ronald Minnich <rminnich@chromium.org> Tested-by: Ronald Minnich <rminnich@chromium.org> Reviewed-by: Furquan Shaikh <furquan.m.shaikh@gmail.com> (cherry picked from commit 8cdaf73e3602e15925859866714db4d5ec6c947d) snow: Fix a typo in devicetree.cb that was breaking the snow build. A typo in a recent change broke the snow build. Old-Change-Id: I93074e68eb3d21510d974fd8e9c63b3947285afd Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://chromium-review.googlesource.com/171014 Reviewed-by: Ronald Minnich <rminnich@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> (cherry picked from commit 154876c126a6690930141df178485658533096d2) Squashed a fix into the initial patch and updated nehalem/gma.c to have a non-static gtt_poll. Change-Id: I2f4342c610d87335411da1d6d405171dc80c1f14 Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6657 Tested-by: build bot (Jenkins)
2014-08-22ARM: Overhaul the ARM Makefile.Gabe Black
The ARM Makefile was copied from x86 and then modified, and as a result it was carrying a lot of baggage. On top of that, the extra complication made it inflexible, and we need a lot of flexiblity in order to support the fact that the Tegra124 starts on an ARMv4 coprocessor instead of one of the ARMv7 main CPUs. Change-Id: Ia6ddc27619bdb51e152ad0c628ad6f3037c103ce Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://chromium-review.googlesource.com/171017 Reviewed-by: Ronald Minnich <rminnich@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> (cherry picked from commit 512d942788336c8d52470135b43ee4e6a1c95f6c) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6709 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: David Hendricks <dhendrix@chromium.org>
2014-08-21arm: Get rid of the INTERMEDIATE variable used on exynos.Gabe Black
The INTERMEDIATE variable was used to hook dd-ing the BL1 into the image for Exynos SOCs, but we can do that directly without having a special hook. Change-Id: I434506b52ca4ea1d01e25a785cbfe66dfdea21c4 Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://chromium-review.googlesource.com/170921 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> (cherry picked from commit 8db03c387ad654227d064e2a7fa5ecf09d07e3c5) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6714 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: David Hendricks <dhendrix@chromium.org>
2014-08-18trustzone: Pull trustzone init out of cpu.c and do it in romstage.Gabe Black
Trustzone needs to be initialized/disabled both on boot and on wake, so it needs to be done before ramstage which doesn't run on wake. cpu.c isn't compiled into romstage and fixing that causes other problems, so the trustzone functions were split out. Change-Id: I8fc630237ebec1f02a91600f8baf3d4e9ea66d0e Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://chromium-review.googlesource.com/169817 Reviewed-by: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> (cherry picked from commit 055ed0e28476123b0bd666109af90baf40aadcee) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6666 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-08-18exynos5420: Don't map low addresses that lead nowhereJulius Werner
I just spent half a day (including the time to implement a stack dumper) to figure out that I am reading from a NULL pointer. A problem this simple should be more easy to catch. Let's mark the address range below SRAM as uncached so that the MMU can yell at you right away for being the bad programmer you are when you access a NULL pointer. Change-Id: I4a3a13f75bf21b25732be2ecb69d47503eff1b53 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/170112 Reviewed-by: Ronald Minnich <rminnich@chromium.org> (cherry picked from commit 7316732ea0ccdc0d607bde81dbb38ca9abd29fa9) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6650 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-08-18arm/exynos: Allow releasing UART retention for resume.Hung-Te Lin
The UART / serial console is put in retention state by kernel during suspend / resume path, which caused Coreboot not able to print any messages during resume. Sending values to the padret_uart_opt inside PMU may release UART, but that may also cause unexpected output when kernel is back. However, it's still very helpful when we are debugging suspend/resume inside Coreboot. To get UART message on resume, call wakeup_enable_uart() in boot block or romstage (before console_init). Change-Id: Ib5759cb402c6e018d9dba14fad8b61f6a1b1a265 Reviewed-on: https://chromium-review.googlesource.com/170440 Tested-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Commit-Queue: Hung-Te Lin <hungte@chromium.org> (cherry picked from commit 547fbbfe2eeb6da4e161f36be2caf8099f9eac9b) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6649 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-08-18exynos5: Implement support for USB 3.0 DRD PHYs/controllersJulius Werner
This patch adds support for the DesignWare3 USB 3.0 DRD controller and PHY to the Exynos5250 and Exynos5420 CPUs. It also adds code to the Google Snow and Pit boards to turn these controllers on where applicable. Change-Id: Idcca627363a69f1d65402e1acb9a62b439f077ff Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/169452 Reviewed-by: Stefan Reinauer <reinauer@google.com> (cherry picked from commit e9809ae12ef8b8bd6cd61d3f604cb9e4718cf7eb) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6642 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-08-18console: conditionally include console in bootblockStefan Reinauer
Right now some console specific objects are included in the bootblock even if CONFIG_BOOTBLOCK_CONSOLE is disabled while others are not. Make all of them conditional and also fix a preprocessor misuse in bootblock_simple.c and a stray (useless) die() in the Exynos wakeup code that made inclusion of those files necessary. Change-Id: Ia7f9d17654466f199b0e13afbdc9e14c9706530f Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: https://chromium-review.googlesource.com/168772 Reviewed-by: David Hendrix <dhendrix@chromium.org> (cherry picked from commit 855da1f07b52898c7edcaffe5baabe9d485bbd83) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6637 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2014-08-16exynos5xx0: rename local "main" variablePatrick Georgi
Change-Id: I9a454c88c65e4e70d351f1ec781e75ba400ceb29 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/6664 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-08-14Exynos: de-duplicate mct timer initializationStefan Reinauer
timer initialization is the first thing happening in the Exynos CPU's bootblock code. Hence we don't need to keep track of it in several places, and we don't need to do it over and over again (e.g. in each stage) Change-Id: I7bd9a0b7930fc9c37faabd62e3eecc3e5614a879 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: https://chromium-review.googlesource.com/168994 Reviewed-by: Stefan Reinauer <reinauer@chromium.org> Commit-Queue: Stefan Reinauer <reinauer@chromium.org> Tested-by: Stefan Reinauer <reinauer@chromium.org> (cherry picked from commit 5a95bc2bcab5a92c5e6c144005861bf731f59de3) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6638 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-08-14ARMv7/Exynos: Fix memory location assumptionsStefan Reinauer
This patch cleans out a lot of unused variables in the ARM Kconfig files and introduces CONFIG_RAMSTAGE_BASE which is similar to CONFIG_RAMBASE on x86. This gets rid of the hard coded assumption that on ARM coreboot is always executed at the lowest DRAM address. But in fact, this might not be true because we might want coreboot to live at the end of RAM, or in SRAM Change-Id: I03e992645f9eb730e39a521aa21f702959311f74 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: https://chromium-review.googlesource.com/168645 Reviewed-by: David Hendrix <dhendrix@chromium.org> Tested-by: David Hendrix <dhendrix@chromium.org> (cherry picked from commit 15b87892eb2d5e27759c49dc6c8c7e626f651d77) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6634 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-08-14exynos5: Refactor crazy old U-Boot base address macros awayJulius Werner
All this samsung_get_base_address_of_device_with_a_really_long_name() boilerplate makes my eyes bleed... I think there are so much cleaner ways to do this. Unfortunately changing this ends up touching nearly every Exynos5 file, but I hope you agree that it's worth it (and the sooner we get it over with, the better... I can't bring myself to make another device fit into that ugly scheme). This also removes the redundant EXYNOS5 base address definitions from the 5420 directory when there are EXYNOS5420 ones, to avoid complete confusion. The new scheme tries to use EXYNOS5 for base addresses and exynos5 for types that are common between the two processors, and EXYNOS5420/exynos5420 for things that have changes (although I probably didn't catch all differences). Change-Id: I87e58434490ed55a9bbe743af1f9bf2520dec13f Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/167579 Reviewed-by: Stefan Reinauer <reinauer@google.com> Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-by: ron minnich <rminnich@chromium.org> (cherry picked from commit 66c87693352c248eec029c1ce83fb295059e6b5b) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6632 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-08-13exynos5420: Enable relocatable module supportStefan Reinauer
Since we're now supporting ARMv7 relocations, we can enable rmodule support on Exynos 5420. This does not automatically enable relocatable ramstage. Signed-off-by: Stefan Reinauer <reinauer@google.com> Change-Id: Ic3af1eabb3b816944587a46409224f778d941b8a Reviewed-on: https://chromium-review.googlesource.com/167403 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: Stefan Reinauer <reinauer@google.com> Commit-Queue: Stefan Reinauer <reinauer@google.com> (cherry picked from commit 7b5afef4ee87fc3245ec887dfda873c529d8d04d) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6629 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2014-08-12exynos5420: minor clean-up memory related stuffDavid Hendricks
This cleans up a few minor things (mostly #defines) of the memory code for exynos5420, pit, and kirby. Specifically: - CONCONTROL.empty is read-only, so don't try to set it and also get rid of the unneeded DMC_CONCONTROL_EMPTY_ENABLE #define. - MEMBASECONFIG* overlaps members of the mem_timings struct and are mainboard-dependent anyway, so get rid of 'em. - DMC_MEMCONTROL_TP_DISABLE corresponds to a reserved bit. It may have been deprecated. - Same with TIMING* #defines. - Clarify DDR_MODE_* usage and use mem->mem_type when appropriate. Signed-off-by: David Hendricks <dhendrix@chromium.org> Change-Id: Ideb21efcc97b24f7e115e90051c20daef4480f17 Reviewed-on: https://chromium-review.googlesource.com/167500 Commit-Queue: David Hendricks <dhendrix@chromium.org> Tested-by: David Hendricks <dhendrix@chromium.org> Reviewed-by: ron minnich <rminnich@chromium.org> (cherry picked from commit 650dba32cb217414c422907398f68e784e5720e8) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6614 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2014-08-12exynos5420/pit: re-factor membaseconfig0/1 usageDavid Hendricks
membaseconfig0/1 are utterly dependent on the mainboard's particular DRAM setup. This defines their values in the mem_timings struct for pit. Signed-off-by: David Hendricks <dhendrix@chromium.org> Old-Change-Id: Ifd782d1229b2418f8ddbf0bcb3f45cc828ac34b0 Reviewed-on: https://chromium-review.googlesource.com/167488 Commit-Queue: David Hendricks <dhendrix@chromium.org> Tested-by: David Hendricks <dhendrix@chromium.org> Reviewed-by: ron minnich <rminnich@chromium.org> (cherry picked from commit 80eebd5bc0dbb9fabf81f46c25dcd5c5d5747579) exynos5420: necessary updates for DRAM This updates DRAM usage for Exynos5420 so that we can actually use 3.5GB: - Memory chips used with Exynos5420 may have 16 row address lines. Signed-off-by: David Hendricks <dhendrix@chromium.org> Old-Change-Id: I86d1a96d0d1a028587f7655f8de5a2e52165e9d2 Reviewed-on: https://chromium-review.googlesource.com/167489 Commit-Queue: David Hendricks <dhendrix@chromium.org> Tested-by: David Hendricks <dhendrix@chromium.org> Reviewed-by: ron minnich <rminnich@chromium.org> (cherry picked from commit 04bbaf5d8e125166dd689f656d5b37776be01fb1) Squashed two related commits. Change-Id: I4e45bc8a446715897ec21b0160701152fa6b226b Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6613 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-08-12exynos5420: ddr3: Switch from 4G setup to 2G setup on exynos5420David Hendricks
This changes the number of chip selects that we configure from 2 to 1. On current setups with (x16 memory 4Gbit chips) that means that we're at 2GByte. Technically we should add a second setting in the ares_ddr3_timings and select between the two of the based on board strappings. That would make the CONFIG_RUN_TIME_BANK_NUMBER work properly. I've changed the ddr3_mem_ctrl_init() so it should handle that, but I'm not actually doing the board strapping read right now. This change means that accesses to 0xA0000000 - 0xFFFFFFFF on 2G systems will no longer put the system in a messed up state (leading to a hang). It also prevents some of the weird boot behavior that we've seen that comes and goes depending on U-Boot alignment. See <http://crosbug.com/p/20577>. This patch was ported from: https://gerrit.chromium.org/gerrit/66117 Signed-off-by: David Hendricks <dhendrix@chromium.org> Change-Id: Ib4cfe420aac30bd817438f06d01e8671afc4a27d Reviewed-on: https://chromium-review.googlesource.com/167210 Commit-Queue: David Hendricks <dhendrix@chromium.org> Tested-by: David Hendricks <dhendrix@chromium.org> Reviewed-by: ron minnich <rminnich@chromium.org> (cherry picked from commit 0ea574243058068702e3f6bc7355098745d16880) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6612 Tested-by: build bot (Jenkins)
2014-08-12Exynos5420: ddr3: fine tuning the DDR3 timing valuesDavid Hendricks
Fine tuning DDR timings value for better stability * Changed Data Driver Strength from 34 ohms to 30 ohms, expected to enhance signal integrity. * Changed DQ signal from 0xf to 0x1f000f, to keep default value safe. * Changed mrs[2] and added new mrs direct command for setting WL/RL without resetting DLL. * Added explicit reset value write in phy_con0 instead of just setting a bit, to ensure that reset happens. * Added DREX automatic control for ctrl_pd in none read memory state. This is ported from: https://gerrit.chromium.org/gerrit/61405 Signed-off-by: David Hendricks <dhendrix@chromium.org> Change-Id: I59e96e6dede7b49c6572548aca664d82ad110bb1 Reviewed-on: https://chromium-review.googlesource.com/66995 Reviewed-by: ron minnich <rminnich@chromium.org> Commit-Queue: David Hendricks <dhendrix@chromium.org> Tested-by: David Hendricks <dhendrix@chromium.org> (cherry picked from commit ec34b711c6d270672c56d45c370ca14c0aa27ca3) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6611 Reviewed-by: David Hendricks <dhendrix@chromium.org> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-08-12Exynos5420: Remove code for enabling read levelingDavid Hendricks
This patch intends to remove all code which enables hardware read leveling. We need to disable h/w read leveling because new ASV table is merged in kernel (which is based on the new characterization condition) and new characterization environment has h/w read leveling disabled, so we should also disable this. Also, disabling h/w read leveling improves the MIF LVcc value (LVcc value is the value at which DDR will fail to work properly), improve LVcc means we have enough voltage margin for MIF. When h/w leveling is enabled, we have almost zero volatge margin. This was ported from: https://gerrit.chromium.org/gerrit/66070 Signed-off-by: David Hendricks <dhendrix@chromium.org> Change-Id: Id0a2d77e6214325f226d51ae08464b39424cea83 Reviewed-on: https://chromium-review.googlesource.com/66994 Reviewed-by: Gabe Black <gabeblack@chromium.org> Commit-Queue: David Hendricks <dhendrix@chromium.org> Tested-by: David Hendricks <dhendrix@chromium.org> (cherry picked from commit d29add98f52876aaed4fee2b76edf6b4591e66e8) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6610 Reviewed-by: David Hendricks <dhendrix@chromium.org> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-08-12exynos5: Refactor board-specific parts out of USB PHY codeJulius Werner
This patch moves around some of the existing Exynos5 USB 2.0 PHY code to make it cleaner in preparation of the 3.0 PHYs. It moves the VBUS GPIOs (which are completely board-specific) into the mainboard code and makes sure to only initialize PHYs on the boards that actually need them. It also removes the USB 3.0 PLL hack that was needed on Snow from the Pit and Kirby boards (which do not have that PLL anymore). Change-Id: Ia35f47a765acff60481f0907f7448ec4f78e0937 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/66887 Reviewed-by: Stefan Reinauer <reinauer@google.com> (cherry picked from commit c3b1a8b687b535f4d5ac1b3bd2a4760151698fdb) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6609 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-08-12exynos5420: ddr3: Cleanup init to use constants for directcmdDavid Hendricks
The old ddr3_mem_ctrl_init() for exynos5420 had hardcoded constants for accessing directcmd registers. Modify to use #defines where possible. This is ported from: https://gerrit.chromium.org/gerrit/#/c/65616 Signed-off-by: David Hendricks <dhendrix@chromium.org> Change-Id: I01567fc6941608a570832de97259c55e84942d01 Reviewed-on: https://gerrit.chromium.org/gerrit/66789 Commit-Queue: David Hendricks <dhendrix@chromium.org> Tested-by: David Hendricks <dhendrix@chromium.org> Reviewed-by: Ronald G. Minnich <rminnich@chromium.org> (cherry picked from commit d751e019f450172f060ce255ae53e972bc4a19ea) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6605 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-08-12exynos5420: Alter init sequence as per recommendationDavid Hendricks
As per hardware recommendation, CKE PAD retention release must happen just before gate leveling enable and only in case of resume. Hence, this patch moves pad retention release from dmc_common.c to dmc_init_ddr3_exynos5420.c. In addition to this we are providing 125 (+3 extra being safe) times auto refresh to DRAM by sending REFA direct command. This is required because when CKE PAD retention release happens, self refresh mode of DDR3 is disabled. Hence, auto refresh 125 times. This is ported from https://gerrit.chromium.org/gerrit/#/c/65573 Note: Since WAKEUP_DIRECT does not go thru memory init, it should be safe to move CKE PAD retention out of bootblock.c. Signed-off-by: David Hendricks <dhendrix@chromium.org> Change-Id: Idec5d6fbbe3c6344d47401ba7203079c52a9b866 Reviewed-on: https://gerrit.chromium.org/gerrit/66788 Commit-Queue: David Hendricks <dhendrix@chromium.org> Tested-by: David Hendricks <dhendrix@chromium.org> Reviewed-by: Ronald G. Minnich <rminnich@chromium.org> (cherry picked from commit 96cbcb09245d4df92d3e1998704ab440be42df25) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6604 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-08-12exynos5420: Make USB A-A booting work with early data cacheJulius Werner
Apparently the IROM doesn't like data caches... the recently added dcache-in-bootblock makes A-A booting fail, and flushes/invalidations alone don't seem to fix it. It's pretty fast anyway, so we just disable the cache again for the duration of the IROM call. Also removes a superfluous invalidation line from the bootblock code... dcache_mmu_enable/disable already take care of that. Old-Change-Id: I35580d15664c7b4197d4ed14028720147adbf918 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/66602 Reviewed-by: Gabe Black <gabeblack@chromium.org> Reviewed-by: David Hendricks <dhendrix@chromium.org> (cherry picked from commit e9c28a6a7a88c8286e62764ee5ad2694da2e822f) exynos5: Implement booting from SDMMC media This patch augments the alternative CBFS media source implementation for Exynos5250 and Exynos5420 to allow booting from SDMMC devices (such as an SD or uSD card reader, if available). It also moves MMC initialization for the Snow, Pit and Kirby boards from romstage to ramstage (mainboard_init) to prevent it from interfering with the IROM during SDMMC boot. Old-Change-Id: Ic4adef80c28262d084a53c28ec59aa7ac3af50c8 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/66154 (cherry picked from commit 08de13b72432c076e3327c048df93d89d52b0ecc) snow and pit: turn on FET4 (for SD card) at bootup Explictly enable FET4 on Snow and Pit. Historically we haven't needed to do this because: * On snow there's a bypass around FET4 which effectively eliminates it. Even if we don't turn on FET4 the SD card is still powered. Turning on FET4 doesn't hurt though and is technically correct. * On pit the EC turns on FET4 on cold bootup. On pit we run into a problem if the kernel turns off FET4 like in <https://gerrit.chromium.org/gerrit/#/c/65332/> and then we get a software reset or warm reset. In this case the EC won't know to turn it back on. This was ported from: https://gerrit.chromium.org/gerrit/#/c/65673 Signed-off-by: David Hendricks <dhendrix@chromium.org> Old-Change-Id: I57337f12b38889e6afee8577cf8807ec4c41e91c Reviewed-on: https://gerrit.chromium.org/gerrit/66786 Commit-Queue: David Hendricks <dhendrix@chromium.org> Tested-by: David Hendricks <dhendrix@chromium.org> Reviewed-by: Ronald G. Minnich <rminnich@chromium.org> (cherry picked from commit e910117047d898b6b1d0dc965ef2ec0237d17646) Squashed three commits for alternate cbfs SD support. Change-Id: Idbd1fd4776cbf8cb20d03e6b691104cd8540a1ec Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6530 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-08-10exynos5420: Tighten up displayport timing loopsRonald G. Minnich
We were running this loop 100 times with 5 ms delays. Change it to run 500 times with 1 ms delays, which gives us the same overall timeout but lets us bail out a bit sooner -- in practice, at most, 4 ms sooner but every bit counts. Note, however, that the tighter timing does reduce opportunities for threading. There is a non-obvious set of tradeoffs on timeouts. Change-Id: I4af671c2a791aa92e446e66ac2fe5710d1e6aa4c Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: https://chromium-review.googlesource.com/167387 Reviewed-by: David Hendricks <dhendrix@chromium.org> Commit-Queue: ron minnich <rminnich@chromium.org> Tested-by: ron minnich <rminnich@chromium.org> (cherry picked from commit 575e910127dc74416018f182ef27ef223e61daef) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6543 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-08-10armv7: Support stack dump after exceptionsJulius Werner
This patch enhances the armv7 exception handlers in Coreboot and libpayload to show the correct SP and LR registers from the aborted context, and also dump a part of the current stack. Since we cannot access the banked registers of SVC mode from a different exception mode, it changes Coreboot (and its payloads) to run in System mode instead. As both modes can execute all privileged instructions, this should not have any noticeable effect on firmware operation (please correct me if I'm wrong!). Change-Id: I0e04f47619e55308f7da4a3a99c9cae6ae35cc30 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/170045 Reviewed-by: Gabe Black <gabeblack@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org> (cherry picked from commit d0db2f5e938200e3f5899c5e1f1606ab2dd5b334) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6538 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-08-10exynos: Get rid of the unused reset.c.Gabe Black
The source file reset.c, present in both the exynos5250 and 5420 directories, is not being built for either SOC. Let's get rid of the clutter. Change-Id: Iab4c7982a271d08cbaf3207b6f5431f0ef52697e Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://chromium-review.googlesource.com/170402 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: David Hendrix <dhendrix@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> (cherry picked from commit 0ce3898276ff49d171a0d8a650806f0305c0576f) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6542 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-08-09Exynos5420: clean up SPI driverStefan Reinauer
That extra struct is not needed, we already defined it earlier on. Also fix coding style in the file. Signed-off-by: Stefan Reinauer <reinauer@google.com> Change-Id: I586d290f2f3ba2f44aca7fdee400b88547465599 Reviewed-on: https://chromium-review.googlesource.com/169780 Reviewed-by: Stefan Reinauer <reinauer@google.com> Commit-Queue: Stefan Reinauer <reinauer@google.com> Tested-by: Stefan Reinauer <reinauer@google.com> (cherry picked from commit f7df9f05fb707cac7976cd8a0b36bcf30cef8e0f) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6532 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-08-08exynos5420: Implement support to boot with USB A-A firmware uploadJulius Werner
This patch ports the USB A-A firmware upload functionality from exynos5250 over to exynos5420. Essentially just like a conflictless cherry-pick of 9e69421f5f0eebf88c09913dee90082feab2856c. It also fixes the exact same bug with SPI initialization for Pit and Kirby. Old-Change-Id: Ief0ed54c0beb2701e51201041f9bc426b2167747 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/65751 Reviewed-by: David Hendricks <dhendrix@chromium.org> (cherry picked from commit 5dff43f929478f83939221df13b961a69f89b132) exynos5: Fix trivial style nits A few curly braces on the wrong line. Old-Change-Id: I4ddac4476c6509dc1716e8c1915fbdb67d346786 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/66153 Reviewed-by: Ronald G. Minnich <rminnich@chromium.org> (cherry picked from commit 41e3fd9eaafe36433723f4e96a6d94c04e5fbafb) Squashed two related commits. Change-Id: I22d579693b5e7270aacb45bbe3557e40893dd1f8 Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6500 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-08-07Exynos 5420: skip the EDID read if there is already an EDID.Ronald G. Minnich
For many boards, the EDID is known and is set in the ramstage. Reading the EDID is slow and if we have it we do not want to reread it. If the raw_edid struct member is non-null, skip reading the EDID. Change-Id: I63fb11aa90b2f739a351cdc3209faac2713ea451 Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: https://chromium-review.googlesource.com/167116 Reviewed-by: Gabe Black <gabeblack@google.com> Tested-by: ron minnich <rminnich@chromium.org> Commit-Queue: Ronald Minnich <rminnich@google.com> (cherry picked from commit 80f48655570de544a7e1939c4f5f28713f11d829) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6514 Tested-by: build bot (Jenkins)
2014-08-07exynos5420: Set the CLK_DIV_CPERI1 value as per manualDavid Hendricks
Set the CLK_DIV_CPERI1 value as recommended by the 0.02 UM section 7.9.1.25. This suggests to use 0x3F3F0000 as the value to be set to save power. This is ported from https://gerrit.chromium.org/gerrit/#/c/64905 Signed-off-by: David Hendricks <dhendrix@chromium.org> Change-Id: I89a6a72d20374a513019a272628a05e139b31773 Reviewed-on: https://gerrit.chromium.org/gerrit/66787 Commit-Queue: David Hendricks <dhendrix@chromium.org> Tested-by: David Hendricks <dhendrix@chromium.org> Reviewed-by: Ronald G. Minnich <rminnich@chromium.org> (cherry picked from commit 34be13b008e262c641268b7c1c6a08e49f18fc37) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6512 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-08-07exynos: Set up caching in the bootblock.Gabe Black
This improves firmware boot time substantially. Because cbmem isn't available yet, we need to allocate some space in sram for the ttb. Doing cache initialization in the bootblock means we can implement this once per CPU instead of once per mainboard. Old-Change-Id: Iad339de24df8ec2e23f91fe7bf57744e4cc766c5 Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/65938 Reviewed-by: David Hendricks <dhendrix@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> (cherry picked from commit c32b9b32ad933e627b9ea98434b392239b1fea73) exynos5420: flush caches and disable MMU in resume path This patch flushes the caches and disables the MMU before resuming. c32b9b3 ("Set up caching in the bootblock.") had a bug where the dcache and MMU remained enabled in the resume path. This caused the machine to hang on resume. However, other bugs were preventing us from testing this properly earlier on so it went unnoticed until now. Signed-off-by: David Hendricks <dhendrix@chromium.org> Old-Change-Id: Ib1774f09d286a4d659da9fc2dad1d7a6fc1ebe5e Reviewed-on: https://chromium-review.googlesource.com/67007 Reviewed-by: ron minnich <rminnich@chromium.org> Commit-Queue: David Hendricks <dhendrix@chromium.org> Tested-by: David Hendricks <dhendrix@chromium.org> (cherry picked from commit 4fdf9763d25f70fd1e3591f6ff9785f78dd6170d) Squashed two related commits. Change-Id: Ibd42b28bb06930159248130e5ceaddb3b4b6cc2a Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6511 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-08-07Exynos5420: invoke the cooperative threading in udelayRonald G. Minnich
Call thread_yield_microseconds in udelay. This works with and without COOP_MULTITASKING enabled. Change-Id: Ib3eab00d1630dc4daada850e7458ab89702d1864 Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: https://gerrit.chromium.org/gerrit/66327 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org> Commit-Queue: Ronald G. Minnich <rminnich@chromium.org> Tested-by: Ronald G. Minnich <rminnich@chromium.org> (cherry picked from commit 12e55ba8a68e5d40e08ad169848bdf274887ce0b) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6510 Tested-by: build bot (Jenkins)
2014-08-06Exynos5: Remove unneeded USB delaysStefan Reinauer
Change-Id: I1144e9d6d6c4278842fdd36743c8a88555f81707 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/65912 Reviewed-by: Ronald G. Minnich <rminnich@chromium.org> Commit-Queue: Stefan Reinauer <reinauer@chromium.org> Tested-by: Stefan Reinauer <reinauer@chromium.org> (cherry picked from commit 95b518877edc88347ce9725ffee32f3aed0de7dc) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6505 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-08-06Exynos5420: tighten up display port delaysRonald G. Minnich
Shorten a few delays, and make some delays shorter but let the loops have a higher termination count (i.e. give it the same amount of time to warm up, but check more frequently). Change-Id: Id9fe846ae3a8d792b14d62aea4e98d8aad05be43 Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: https://gerrit.chromium.org/gerrit/66156 Commit-Queue: Ronald G. Minnich <rminnich@chromium.org> Tested-by: Ronald G. Minnich <rminnich@chromium.org> Reviewed-by: Stefan Reinauer <reinauer@google.com> (cherry picked from commit a112e77f2f21f41f982ca22bebdac213cc8d233a) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6506 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-08-06exynos5420: Fix mmc clock source.Hung-Te Lin
The DWMMC controller internally divided clock by values in CLKSEL registers, so we must adjust MMC clock for that. Change-Id: I44f55b634cfc6fd81d76631595b6928c862a219f Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/66657 Commit-Queue: Ronald G. Minnich <rminnich@chromium.org> Reviewed-by: Ronald G. Minnich <rminnich@chromium.org> Tested-by: Ronald G. Minnich <rminnich@chromium.org> Reviewed-by: David Hendricks <dhendrix@chromium.org> (cherry picked from commit 89ed6c9154f16c6b8d01af03c0b78914773eb469) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6504 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-08-06Set armv7 up for cpu_info to work as on x86 (so threads can work)Ronald G. Minnich
On x86, cpu_info lives at the top of stack. Make the arm do that as well, as the threading model needs that and so will multicore support. As part of this change, make the stack size a power of 2. Also make it much smaller -- 2048 bytes is PLENTY for ram stage. Note that the small stack size is counterintuitive for rom stage. How can this work in rom stage, which needs a HUGE stack for lzma? The main use of STACK_SIZE has always been in ram stage; since 2002 or so it was to size per-core stacks (see, e.g., src/arch/x86/lib/c_start.S:.space CONFIG_MAX_CPUS*CONFIG_STACK_SIZE and, more recently, thread stacks. So, we define the STACK_TOP for rom and ram stage, but the STACK_SIZE has no real effect on the ROM stage (no hardware red zones on the stack) and hence we're ok with actually defining the "wrong" stack size. In fact, the coreboot_ram ldscript for armv7 sizes the stack by subtracting CONFIG_STACK_BOTTOM from CONFIG_STACK_TOP, so we replicate that arithmetic in bootblock.inc Observed stack usage in ramstage: BS: BS_PAYLOAD_LOAD times (us): entry 1 run 153887 exit 1 Jumping to boot code at 23104044 CPU0: stack: 02072800 - 02073000, lowest used address 020728d4, stack used: 1836 bytes entry = 23104044 Which means we do need 2K, not 1K. Change-Id: I1a21db87081597efe463095bfd33c89eba1d569f Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: https://gerrit.chromium.org/gerrit/66135 Reviewed-by: Ronald G. Minnich <rminnich@chromium.org> Tested-by: Ronald G. Minnich <rminnich@chromium.org> Commit-Queue: Ronald G. Minnich <rminnich@chromium.org> (cherry picked from commit f011097e9f2bfb2f4c1109d465be89a79a65ba3e) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6501 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-08-05exynos5420: get rid of old exynos5420_config_l2_cache()David Hendricks
We set up L2 cache early in romstage now so the old function is now redundant. Signed-off-by: David Hendricks <dhendrix@chromium.org> Old-Change-Id: Icec93810ddd7feb48286d4b600cb2d58af38b7ef Reviewed-on: https://gerrit.chromium.org/gerrit/65428 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Commit-Queue: David Hendricks <dhendrix@chromium.org> Tested-by: David Hendricks <dhendrix@chromium.org> (cherry picked from commit bb91f1078ea55a7c8bdc19336cef2ec9a5f4511f) exynos: stack size: Increase the stack size to 16KB. The lzma decoding function in the RAM stage allocates nearly 16KB on the stack which is shared between the bootblock, rom stage, and ram stage. The stack had been much too small and needed to be expanded. Old-Change-Id: I1b74fff9b54e506320d58956b779b3a102e66868 Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/65937 Reviewed-by: Ronald G. Minnich <rminnich@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> (cherry picked from commit 243d8a80f68dd257ecc5b4e19614bc7f0f5d398b) exynos: gpio: add a bigger delay when reading board strappings Z-state pins were not reading reliably with a 5us delay, so increase it to 15us. This is ported from https://gerrit.chromium.org/gerrit/64338 Signed-off-by: David Hendricks <dhendrix@chromium.org> Old-Change-Id: Ife6ea2ef5989e1a4c17913278ab972f0fd7f7f35 Reviewed-on: https://gerrit.chromium.org/gerrit/65727 Reviewed-by: Ronald G. Minnich <rminnich@chromium.org> Tested-by: Ronald G. Minnich <rminnich@chromium.org> Commit-Queue: David Hendricks <dhendrix@chromium.org> Tested-by: David Hendricks <dhendrix@chromium.org> (cherry picked from commit 76f0f8203f1af3f461745cefcc94e97c422d9084) exynos5420: enable DMC internal clock gating lets enable memory controller internal clock gating for ddr3. with these bits enabled we save some power out of ddr3. This is ported from https://gerrit.chromium.org/gerrit/#/c/60774 Signed-off-by: David Hendricks <dhendrix@chromium.org> Old-Change-Id: I2f9b0d78483b3ea7441f54a715c7c1e42eda3f7f Reviewed-on: https://gerrit.chromium.org/gerrit/65728 Reviewed-by: Ronald G. Minnich <rminnich@chromium.org> Commit-Queue: David Hendricks <dhendrix@chromium.org> Tested-by: David Hendricks <dhendrix@chromium.org> (cherry picked from commit 022a81c44e655a9f81e974e730c0cecc1f048781) exynos5420: Correct the 600MHz PMS value In UM ver0.02, 600MHz clock PMS values differs from what is programed currently. Though this also results in 600MHz clock, but it is better to match what UM says. This patch chnage this as per UM This is ported from https://gerrit.chromium.org/gerrit/#/c/65106/3 (Note: we already used the correct 600MHz value for KPLL) Signed-off-by: David Hendricks <dhendrix@chromium.org> Old-Change-Id: I6786815ab33427a23436e6ee37295f6c37dcd3d5 Reviewed-on: https://gerrit.chromium.org/gerrit/65726 Reviewed-by: Ronald G. Minnich <rminnich@chromium.org> Tested-by: Ronald G. Minnich <rminnich@chromium.org> Commit-Queue: David Hendricks <dhendrix@chromium.org> Tested-by: David Hendricks <dhendrix@chromium.org> (cherry picked from commit ceabf57ca78449fa6e9cfd212bdf4774706de92f) Squashed five commits pertaining to exynos. Change-Id: I3fd894aed15b8cd161c30904a46dac7e07eb8992 Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6425 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-07-31timer: Add functions to initialize absolute timer structures.Gabe Black
Otherwise there's no good way to create an absolute timer structure without fiddling with its internal structure or assuming a zero initialized structure has a value of zero. Old-Change-Id: Iffe3b6b25ed7963fcfb66f749c531ea445ea4aeb Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/65301 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Commit-Queue: Stefan Reinauer <reinauer@google.com> Reviewed-by: Stefan Reinauer <reinauer@google.com> Tested-by: Stefan Reinauer <reinauer@google.com> (cherry picked from commit e2e5c1ef3bb2df95fdf0e33cb2d975a990d07a4a) exynos: Simplify the monotonic timer implementation. The previous implementation was overly complicated, and when used in the timestamp implementation produced some weird and broken results. Old-Change-Id: I3048028ddea0657b01b0c94f312764b38d1397e4 Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/65302 Reviewed-by: Ronald G. Minnich <rminnich@chromium.org> Commit-Queue: Stefan Reinauer <reinauer@google.com> Reviewed-by: Stefan Reinauer <reinauer@google.com> Tested-by: Stefan Reinauer <reinauer@google.com> (cherry picked from commit 6a3fde9a5b80cdac76d79c65d20d7dd1f1d9e557) Squashed two closely related commits. Change-Id: Ifc32d773f4f93d34275a81781001d080357fe8ef Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6406 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-07-31armv7/exynos5420: Configure CPU cores for kernel to enable SMP.Hung-Te Lin
The SMP on Exynos 5420 requires setting a special page and entry wrappers in firmware side (SRAM) so kernel can start cores (and to switch clusters). Change-Id: I77ca98bb6cff5b13e95dd29228e4536302f0aee9 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/64770 Reviewed-by: Ronald G. Minnich <rminnich@chromium.org> (cherry picked from commit 4a11c7ab78cc0811df0f88763b0af8b9f24e5433) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6405 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-07-11src: Make use of 'CEIL_DIV(a, b)' macro across treeEdward O'Callaghan
The objective here is to tighten coreboot up a bit by not repeating common helpers. This makes the code base more consistent and unified/tight. Change-Id: Ia163eae68b4a84a00ed118125e70308fab1cea0c Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/6215 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-07-08cpu: Trivial - drop trailing blank lines at EOFEdward O'Callaghan
Change-Id: I9004f34ba0c13b4489b26ac8c1476d00a6c6d01d Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/6207 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-07-05spi: Change spi_xfer to work in units of bytes instead of bits.Gabe Black
Whenever spi_xfer is called and whenver it's implemented, the natural unit for the amount of data being transfered is bytes. The API expected things to be expressed in bits, however, which led to a lot of multiplying and dividing by eight, and checkes to make sure things were multiples of eight. All of that can now be removed. BUG=None TEST=Built and booted on link, falco, peach_pit and nyan and looked for SPI errors in the firmware log. Built for rambi. BRANCH=None Change-Id: I02365bdb6960a35def7be7a0cd1aa0a2cc09392f Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://chromium-review.googlesource.com/192049 Reviewed-by: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> [km: cherry-pick from chromium] Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/6175 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-07-05spi: Remove unused parameters from spi_flash_probe and setup_spi_slave.Gabe Black
The spi_flash_probe and and spi_setup_slave functions each took a max_hz parameter and a spi_mode parameter which were never used. BUG=None TEST=Built for link, falco, rambi, nyan. BRANCH=None Change-Id: I3a2e0a9ab530bcc0f722f81f00e8c7bd1f6d2a22 Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://chromium-review.googlesource.com/192046 Reviewed-by: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> [km: cherry-pick from chromium] Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/6174 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-06Introduce stage-specific architecture for corebootFurquan Shaikh
Make all three coreboot stages (bootblock, romstage and ramstage) aware of the architecture specific to that stage i.e. we will have CONFIG_ARCH variables for each of the three stages. This allows us to have an SOC with any combination of architectures and thus every stage can be made to run on a completely different architecture independent of others. Thus, bootblock can have an x86 arch whereas romstage and ramstage can have arm32 and arm64 arch respectively. These stage specific CONFIG_ARCH_ variables enable us to select the proper set of toolchain and compiler flags for every stage. These options can be considered as either arch or modes eg: x86 running in different modes or ARM having different arch types (v4, v7, v8). We have got rid of the original CONFIG_ARCH option completely as every stage can have any architecture of its own. Thus, almost all the components of coreboot are identified as being part of one of the three stages (bootblock, romstage or ramstage). The components which cannot be classified as such e.g. smm, rmodules can have their own compiler toolset which is for now set to *_i386. Hence, all special classes are treated in a similar way and the compiler toolset is defined using create_class_compiler defined in Makefile. In order to meet these requirements, changes have been made to CC, LD, OBJCOPY and family to add CC_bootblock, CC_romstage, CC_ramstage and similarly others. Additionally, CC_x86_32 and CC_armv7 handle all the special classes. All the toolsets are defined using create_class_compiler. Few additional macros have been introduced to identify the class to be used at various points, e.g.: CC_$(class) derives the $(class) part from the name of the stage being compiled. We have also got rid of COREBOOT_COMPILER, COREBOOT_ASSEMBLER and COREBOOT_LINKER as they do not make any sense for coreboot as a whole. All these attributes are associated with each of the stages. Change-Id: I923f3d4fb097d21071030b104c372cc138c68c7b Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: http://review.coreboot.org/5577 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@gmail.com>
2014-05-03Move ARCH_* from board/Kconfig to cpu or soc Kconfig.Furquan Shaikh
CONFIG_ARCH is a property of the cpu or soc rather than a property of the board. Hence, move ARCH_* from every single board to respective cpu or soc Kconfigs. Also update abuild to ignore ARCH_ from mainboards. Change-Id: I6ec1206de5a20601c32d001a384a47f46e6ce479 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: http://review.coreboot.org/5570 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-04-30console: Move UART port defaults to mainboardKyösti Mälkki
Correct selection of UART depends of board layout, not the CPU internals, so default setting should originate from mainboard. Change-Id: Ibf0ab0847ccce73c22704e86983dbe3d24ebc8a0 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5618 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-04-30console: Drop EARLY_CONSOLE optionKyösti Mälkki
We have means to easily disable a specific console in romstage if necessary, so this global option makes little sense. The option was initially introduced as a work-around for build issues around CACHE_AS_RAM, ROMCC and ARCH_ARMV7 dependencies for UARTs. Change-Id: I797bdd11a48ddd813d3ee7ccef9a0c050f16f669 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5607 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-04-30uart: Support multiple portsKyösti Mälkki
The port for console remains to be a compile time constant. The Kconfig option is changed to select an UART port with index to avoid putting map of UART base addresses in Kconfigs. With this change it is possible to have other than debug console on different UART port. Change-Id: Ie1845a946f8d3b2604ef5404edb31b2e811f3ccd Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5342 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-04-09uart: Redefine Kconfig optionsKyösti Mälkki
Option DRIVERS_UART builds with support for UART hardware. Option CONSOLE_SERIAL enables the console output for UART. Those x86 boards that do not have serial port on SuperIO should select NO_UART_ON_SUPERIO to disable 8250 UART for the default configuration. Removes: CONSOLE_SERIAL_UART HAVE_UART_IO_MAPPED HAVE_UART_MEMORY_MAPPED Renames: CONSOLE_SERIAL8250 -> DRIVERS_UART_8250IO CONSOLE_SERIAL8250MEM -> DRIVERS_UART_8250MEM Change-Id: Id3afa05f85c0d6849746886db8b6c2ed6c846b61 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5311 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-04-09console uart: Fill coreboot table entriesKyösti Mälkki
Also fixes the reported baudrate to take get_option() into account. Change-Id: Ieadad70b00df02a530b0ccb6fa4e1b51526089f3 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5310 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-04-09uart: Prepare to support multiple base addressesKyösti Mälkki
Prepare low-level register access to take UART base address as a parameter. This is done to support a list of base addresses defined in the platform. Change-Id: Ie630e55f2562f099b0ba9eb94b08c92d26dfdf2e Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5309 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-03-04console: Use single driver entry for UARTsKyösti Mälkki
UARTs now have unified prototypes and can use a single entry in the list of drivers for ramstage. Change-Id: I315daaf9a83cfa60f1a270146c729907a1d6d45b Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5308 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-03-04console: Fix includesKyösti Mälkki
Do not pull in console hw-specific prototypes everywhere with console.h as those are not needed for higher levels. Move prototypes for UARTs next to other consoles. Change-Id: Icbc9cd3e5bdfdab85d7dccd7c3827bba35248fb8 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5232 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-03-04samsung/exynos5: Fix baudrate calculationKyösti Mälkki
Account for possible use of get_option() when baudrate is no longer compile-time constant. Change-Id: Ib45acd98e55c5892dbce9903830665aefeda5be0 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5288 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-02-06ARMv7: Remove static CBMEM allocationKyösti Mälkki
The calculations for static allocation are no longer valid. Change-Id: I6740cdcec789abddf78485a0edaf24882ef8c2a5 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/4569 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: David Hendricks <dhendrix@chromium.org>
2013-12-21pit: disable LCD FETs before doing any graphics initDavid Hendricks
This ensures that the LCD FETs are off before we do graphics init. FIXME: The location of the code is sub-optimal and should probably be done in romstage, but there are __PRE_RAM__ considerations to take into account. Signed-off-by: David Hendricks <dhendrix@chromium.org> Change-Id: I0844030d0a0e51eee1d29f1762f0b495777268df Reviewed-on: https://gerrit.chromium.org/gerrit/64305 Reviewed-by: Ronald G. Minnich <rminnich@chromium.org> Commit-Queue: Ronald G. Minnich <rminnich@chromium.org> Tested-by: Ronald G. Minnich <rminnich@chromium.org> Reviewed-on: http://review.coreboot.org/4470 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21exynos5420: Assign corect parent PLLsDavid Hendricks
Assign correct parent PLL's for the following clocks: ACLK_400_WCORE (MPLL->CPLL) (400 -> 333MHz) PCLK_200_FSYS (MPLL->DPLL) (200 -> 200MHz) MUX_ACLK_100_NOC_SEL (MPLL -> DPLL) (100 -> 100MHz) ACLK_266 (DPLL->MPLL) (300 -> 266MHz) ACLK_200_DISP1(MPLL->DPLL) (200 -> 200MHz) ACLK_400_MSCL(MPLL->CPLL) (400 -> 333MHz) ACLK_66 (MPLL->CPLL) (66.666 -> 66.6MHz) MUX_ACLK_400_DISP1_SEL (CPLL->DPLL) (666 -> 300MHz) MUX_MPHY_REFCLK (MPLL->OSC) MUX_UNIPRO (MPLL->OSC) MUX_MIPI1 (EPLL->OSC) MUX_DP1_EXT_VID (EPLL->OSC) MUX_FIMD1_OPT (EPLL->OSC) MUX_IPLL(IPLL->OSC) This also corrects the clock dividers for few of the clocks, as the clock parent changes affect the final frequency of the clocks. This is ported from: https://gerrit.chromium.org/gerrit/#/c/62437/ Signed-off-by: David Hendricks <dhendrix@chromium.org> Change-Id: Ie833c01913d0961a6190446bd573511de8dee5f8 Reviewed-on: https://gerrit.chromium.org/gerrit/65620 Commit-Queue: Ronald G. Minnich <rminnich@chromium.org> Reviewed-by: Ronald G. Minnich <rminnich@chromium.org> Tested-by: Ronald G. Minnich <rminnich@chromium.org> Reviewed-on: http://review.coreboot.org/4469 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21exynos5420: don't assume MPLL for i2c parent clockDavid Hendricks
This reads the clock select field for MUX_ACLK_66_SEL in the CLK_SRC_TOP1 register in order to obtain the source clock rate for I2C peripherals. Before we were always assuming that the source was the MPLL. Unfortunately not all fields in the CLK_SRC_TOPn registers are enumerated the same with regard to clock select. So this is just a one-off for now. This is basically ported from https://gerrit.chromium.org/gerrit/#/c/62443. Signed-off-by: David Hendricks <dhendrix@chromium.org> Change-Id: I9fa85194ae1a1fadab79695f059efdc2e2f1f75f Reviewed-on: https://gerrit.chromium.org/gerrit/65611 Reviewed-by: Ronald G. Minnich <rminnich@chromium.org> Tested-by: David Hendricks <dhendrix@chromium.org> Commit-Queue: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/4468 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21exynos5420: Set SPLL to 400MHzDavid Hendricks
Increase SPLL to 400MHz from 300MHz as we set SPLL as the switching parent for ARM and KFC. This value is as per recommendation of the hardware team. This is ported from https://gerrit.chromium.org/gerrit/62618 Signed-off-by: David Hendricks <dhendrix@chromium.org> Change-Id: I8a5a5b957083b0b1f3e3e318fe5753cf7ae19223 Reviewed-on: https://gerrit.chromium.org/gerrit/65432 Reviewed-by: Gabe Black <gabeblack@chromium.org> Tested-by: David Hendricks <dhendrix@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/4464 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21exynos5420: re-factor clock_get_periph_rate()David Hendricks
This re-factors clock_get_periph_rate() to be a simpler and also make a few corrections along the way. To summarize: - clk_bit_info is no longer used. It had numerous errors and was really painful anyway since it was just a bunch of opaque magic numbers that made bugs non-obvious. - Clock source bitfields for peripherals handled in the switch statement are 3 bits, not 4. Some divider values are 3 bits, some are 4. The earlier code always assumed 4 bits for both which included reserved bits in many cases. - UART source clock and divider shift values were wrong. - PWM clock divider was being read from the wrong register. - SPI3 divider value was being read from the wrong register. - There was a really confusing calculation for SDMMC0 and SDMMC2 clock rates, but it was never actually used since the switch statement never handled PERIPH_ID_SDMMC{0,2} and would thus return if they were ever passed into this function. Signed-off-by: David Hendricks <dhendrix@chromium.org> Change-Id: I0a03a64d8b42fbe83dbf377292597ce681b22f4b Reviewed-on: https://gerrit.chromium.org/gerrit/65284 Commit-Queue: David Hendricks <dhendrix@chromium.org> Tested-by: David Hendricks <dhendrix@chromium.org> Reviewed-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/4463 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21exynos5420: add a peripheral clock select --> PLL decoderDavid Hendricks
This adds a helper function to translate between peripheral clock select fields in clock source registers and PLLs. Some of this was already done to handle a few special cases, this generalizes the earlier work so that follow-up patches can do further clean-up. Unfortunately, the PLLs represented by clock select fields in various modules are not uniformly ordered. So for now we focus on peripheral clock sources only. Signed-off-by: David Hendricks <dhendrix@chromium.org> Change-Id: Id58a3e488650d09e6a35c22d5394fcbf0ee9ddff Reviewed-on: https://gerrit.chromium.org/gerrit/65283 Commit-Queue: David Hendricks <dhendrix@chromium.org> Tested-by: David Hendricks <dhendrix@chromium.org> Reviewed-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/4462 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21exynos5420: add CPLL and DPLL to the known list of PLLsDavid Hendricks
This patch adds CPLL and DPLL to the known list of PLLs. This is ported from https://gerrit.chromium.org/gerrit/#/c/62617/ Signed-off-by: David Hendricks <dhendrix@chromium.org> Change-Id: I2f2614e44cd9c98d98b8db9347f29de21703d1af Reviewed-on: https://gerrit.chromium.org/gerrit/65282 Reviewed-by: Gabe Black <gabeblack@chromium.org> Tested-by: David Hendricks <dhendrix@chromium.org> Commit-Queue: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/4461 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21exynos5420: correct the PMS value for CPLLDavid Hendricks
This patch matches the User Manual Table 7-2 about the PMS value for CPLL. This doesn't change the PLL frequency (before and after both make 666MHz) but this is the suggested PMSK values for obtaining 666. (Suggested as per user manual). This is ported from https://gerrit.chromium.org/gerrit/#/c/62438/ Signed-off-by: David Hendricks <dhendrix@chromium.org> Change-Id: Ia33e1971ab88da761000d443792560476514626b Reviewed-on: https://gerrit.chromium.org/gerrit/65281 Reviewed-by: Gabe Black <gabeblack@chromium.org> Commit-Queue: David Hendricks <dhendrix@chromium.org> Tested-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/4460 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21exynos5420: Configure the UART pins unconditionallyGabe Black
Configure the pins for the UART unconditionally in the mainboard code (when we know which UART to configure) instead of in the UART driver. This also means the UART will work if later software wants to use it without setting up the pins. Built and booted on pit with the serial turned off and some serial init in the kernel decompression stub fixed. Change-Id: Icab5755e4f935f52d44b9cb3b43d1cb62acce08f Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/65299 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/4457 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21exynos5250: Implement support to boot with USB A-A firmware uploadJulius Werner
This patch implements the basic infrastructure required to use the USB A-A firmware upload feature on Exynos5 processors with Coreboot. It will require a corresponding host-side script that activates the feature and uploads the correct image parts in the correct order to harcoded target addresses, as described in the comments of alternate_cbfs.c. Also fixes a bug in the Google Snow mainboard where it would not correctly initialize the pinmux configuration for the SPI flash bus. During a normal SPI boot the IROM would already do that for you, but when booting from USB you have to do it yourself. Change-Id: I40a39f8f5d1d70b58dbf258015c1653a27097d67 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/64875 Reviewed-by: Stefan Reinauer <reinauer@chromium.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/4456 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21exynos5420: re-factor the SDMMC GPIO config routinesDavid Hendricks
The existing GPIO config routines for SDMMC0-2 are over-generalized and somewhat confusing as a result. It would work nicely if all SDMMC ports were configured in the same fashion, but there are a few exceptions. For example, the inner function runs differently if we're using 8 bits of data instead of 4, so a big chunk is skipped for SDMMC2. SDMMC0 requires SD_0_CDn to be an output rather than alternate function and must have a value set. This patch trades some verbosity for simplicy. Now the SDMMC GPIO configuration a straight-forward sequence of GPIO operations without any exceptions. Signed-off-by: David Hendricks <dhendrix@chromium.org> Change-Id: If75075b24c6588c4c1b3be3fb9b1aa95e2fac2d1 Reviewed-on: https://gerrit.chromium.org/gerrit/65248 Reviewed-by: Gabe Black <gabeblack@chromium.org> Commit-Queue: David Hendricks <dhendrix@chromium.org> Tested-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/4446 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21exynos5420: configure SD_0_CDn as VDDEN for eMMCDavid Hendricks
On Exynos5420 the MMC channel 0 is connected to eMMC Which does not have a card detection pin. Also this pin is connected as VDDEN to PMIC. This is ported from https://gerrit.chromium.org/gerrit/#/c/60732/ Signed-off-by: David Hendricks <dhendrix@chromium.org> Change-Id: I19048d22b7dd00df1716b6b5b332a7eb70fe0836 Reviewed-on: https://gerrit.chromium.org/gerrit/65247 Reviewed-by: Gabe Black <gabeblack@chromium.org> Commit-Queue: David Hendricks <dhendrix@chromium.org> Tested-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/4445 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21exynos5420: init APLL at 1800MHzDavid Hendricks
This initializes the APLL at 1800MHz. Change-Id: I366bf4e75510847ab93d9c9f214a49c731cca08a Reviewed-on: https://gerrit.chromium.org/gerrit/64745 Reviewed-by: Gabe Black <gabeblack@chromium.org> Commit-Queue: David Hendricks <dhendrix@chromium.org> Tested-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/4443 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21exynos5xxx: use oscillator clock when changing ARM frequencyDavid Hendricks
Switch ARM clock source when changing the APLL frequency to avoid stability issues. This is ported from https://gerrit.chromium.org/gerrit/#/c/64189/5 Signed-off-by: David Hendricks <dhendrix@chromium.org> Change-Id: I923107555e6d3287b3694cbf9e4bb548d3e5f4a8 Reviewed-on: https://gerrit.chromium.org/gerrit/64838 Reviewed-by: David Hendricks <dhendrix@chromium.org> Tested-by: David Hendricks <dhendrix@chromium.org> Commit-Queue: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/4442 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21exynos5420: set L2ACTLR parameters for A15 coresDavid Hendricks
This patch does the following for the A15 cores: - Disable clean/evict push to external - Enable hazard detect timout - Prevent gating the L2 logic clock This is ported from https://gerrit.chromium.org/gerrit/#/c/60154 Signed-off-by: David Hendricks <dhendrix@chromium.org> Change-Id: I7ac9f40acecfa7daee6fb81772676bf5119d0536 Reviewed-on: https://gerrit.chromium.org/gerrit/64862 Commit-Queue: David Hendricks <dhendrix@chromium.org> Reviewed-by: David Hendricks <dhendrix@chromium.org> Tested-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/4441 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21exynos5250: Add a pinmux function to set up i2s bus 0Gabe Black
This bus is hooked up on snow and, as it's the only bus hooked up on some other boards, having it available in firmware to test is handy. Change-Id: Icb48b9af4a67d382bd6fbce1e4c6a320d811d365 Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/64877 Reviewed-by: Ronald G. Minnich <rminnich@chromium.org> Commit-Queue: Stefan Reinauer <reinauer@google.com> Tested-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/4438 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21exynos5420: minor correction to CPU frequency printDavid Hendricks
This divides the CPU frequency by 1,000,000 instead of 2^20. serial console shows "CPU: S5P5420 @ 800MHz" instead of claiming 762MHz. Change-Id: I70cc5b62f689c5553b57c82be61233fb9f733f6e Reviewed-on: https://gerrit.chromium.org/gerrit/64743 Reviewed-by: Gabe Black <gabeblack@chromium.org> Reviewed-by: Ronald G. Minnich <rminnich@chromium.org> Commit-Queue: David Hendricks <dhendrix@chromium.org> Tested-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/4434 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21armv7/exynos: Fix and remove memory reset workaroundsHung-Te Lin
The memory corruption problem in Exynos suspend/resume process is caused by two things together: PHY_RESET and MRS command. After stop sending MRS on resume, we can now remove the workaround of skipping PHY_RESET. Change-Id: I64acc27c1d2bb549ae6ad7d32ecda94b0355972c Reviewed-on: https://gerrit.chromium.org/gerrit/64736 Tested-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: David Hendricks <dhendrix@chromium.org> Commit-Queue: Hung-Te Lin <hungte@chromium.org> Reviewed-on: http://review.coreboot.org/4433 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21Pit: graphicsRonald G. Minnich
This includes the new dp code, which is better, and the fimd code, which is changed and improved. We took the chance to remove un-needed files, and also to remove some foolish u-boot habits, but not all of them. That will take time. With these changes we get graphics. Since the only mainboards we have with 16 bit graphics are 5:6:5, adjust edid.c to just use that format. If at some future time we need 4:4:4, which seems unlikely, we'll need to add a function to adjust the lb_framebuffer. Note that you can't just divine this from the EDID, as the graphics pipe format need not match the actual final format used. The EDID reading works. We've been requested to support hard-coded EDIDs and that will come in the next revision. Currently the hard-coded EDID is ignored for testing. Change-Id: Ib4d06dc3388ab90c834f94808a51133e5b515a4d Signed-off-by: Ronald G. Minnich <rminnich@google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/64240 Reviewed-by: Stefan Reinauer <reinauer@google.com> Tested-by: Ronald G. Minnich <rminnich@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/4432 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21Snow: correctly disable trust zone hardwareRonald G. Minnich
The kernel assumes that trust zone is disabled. Change-Id: Ia8d6fa69adcb812a747d8b89eb77e57144423eaa Signed-off-by: Ronald G. Minnich <rminnich@google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/64722 Reviewed-by: Stefan Reinauer <reinauer@google.com> Reviewed-by: David Hendricks <dhendrix@chromium.org> Commit-Queue: Ronald G. Minnich <rminnich@chromium.org> Tested-by: Ronald G. Minnich <rminnich@chromium.org> Reviewed-on: http://review.coreboot.org/4431 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21Pit: correctly initialize trust zoneRonald G. Minnich
This ensures that various trust zone things are reset, which is important because the kernel assumes they are. Change-Id: Ie02ea89885621f58a3ccc4f1729617208a264153 Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: https://gerrit.chromium.org/gerrit/64697 Tested-by: Ronald G. Minnich <rminnich@chromium.org> Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-by: Stefan Reinauer <reinauer@google.com> Commit-Queue: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/4430 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21exynos5420: update set_cpu_id()David Hendricks
The current function seems to be outdated... Signed-off-by: David Hendricks <dhendrix@chromium.org> built and booted. Now we see "CPU: S5P5420 @ 762MHz" instead of "CPU: S5PC420 @ 762MHz" Change-Id: Ieb103a5fa62bda9a6b2cbd9a82fb4f72c5dd6466 Reviewed-on: https://gerrit.chromium.org/gerrit/64302 Commit-Queue: David Hendricks <dhendrix@chromium.org> Reviewed-by: David Hendricks <dhendrix@chromium.org> Tested-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/4425 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21exynos5250: Add mct_start to the timer init blob in timer_monotonic_getGabe Black
A previous change removed init_timer from timer_monotonic_get because its old implementation set up the PWM based timer which was going away. It would still be a good idea to initialize the timer at that point, just not the pwm. Change-Id: I4816710ec2c9d5ca53b704c6b9397bcfac183fdc Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/64160 Reviewed-by: Ronald G. Minnich <rminnich@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/4419 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21Exynos 5420: Enable dynamic CBMEMStefan Reinauer
... In order to do this, the graphics memory has to move into the resource allocator and out of CBMEM. Change-Id: I565c3d6dea747822fbabf6f3845232d4adfbf333 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/63657 Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/4391 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21Exynos 5250: Enable dynamic CBMEMStefan Reinauer
... In order to do this, the graphics memory has to move into the resource allocator and out of CBMEM. Change-Id: I7396da4a7068404b0d2e4d308becab4dd6ea59bb Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/59326 Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/4390 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21exynos5420: Fix some clock settingsGabe Black
Some registers and bit fields were wrong, but the difference is mostly academic since the code that uses them are never called. Change-Id: I0ce5e1529cdda1a4973765af8c31b79130b1111c Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/63189 Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/4385 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21exynos5420: Fix the clock divisor maskGabe Black
The divisor mask had been set to 0xff, but the bitfield is 4 bits wide. Change-Id: Id8a205c80ca2fb0b6f0d86a0c3be4bba9527c0b5 Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/63188 Reviewed-by: David Hendricks <dhendrix@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/4384 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21exynos5420: Get rid of the PWM code like on the 5250Gabe Black
The timer code was supposed to be using the mct, and also using the monotonic timer infrastructure instead of the get_timer function. This change had been made for the 5250 but not yet for the 5420. Change-Id: I03a4fbb434f2346761f28fb6bd2218b526f2a4a2 Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/64159 Reviewed-by: Ronald G. Minnich <rminnich@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/4418 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21exynos5250: Get rid of the PWM timer code we shouldn't be using anymoreGabe Black
This code was left over from U-Boot and was superceded by the MCT. Change-Id: Ia85e3b7281dcdd4740238dddd0dfc6f0ba2c94da Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/63778 Commit-Queue: Gabe Black <gabeblack@chromium.org> Reviewed-by: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/4401 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21exynos5420: Apply pwm const fix to the 5420 as wellGabe Black
When the const was removed from write function arguments, a related bug in the 5250 code was fixed so that it would still compile. Unfortunately, that same change needed to be made to the 5420. Change-Id: If15057c92422de91dc8e35dbd8b5c978bfae122a Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/64154 Reviewed-by: Ronald G. Minnich <rminnich@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/4417 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21exynos5250: Fix consts in the pwm codeGabe Black
The code generally intended to make the pointer const instead of the thing it pointed at, but it had const backwards. Sometimes both the pointer and the data could be const, but sometimes there were writes where only the pointer should be. Change-Id: Ifcd5495769b86b47d7b583cce63ed5c2158bec4e Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/63775 Reviewed-by: David Hendricks <dhendrix@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/4397 Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Tested-by: build bot (Jenkins)
2013-12-20armv7: Remove SYS_TEXT_BASE config.Hung-Te Lin
SYS_TEXT_BASE is not used by any one. To prevent confusion when changing memory layout, remove it from current configurations. Change-Id: I15012b864bbb9c12003843b9b24ea64c91f4578b Reviewed-on: https://gerrit.chromium.org/gerrit/61853 Reviewed-by: David Hendricks <dhendrix@chromium.org> Commit-Queue: Hung-Te Lin <hungte@chromium.org> Tested-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: http://review.coreboot.org/4371 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-12EXYNOS5250: be less chatty at critical momentsRonald G. Minnich
The 5250 DRAM code is *really* chatty. That's not a great idea in time critical code, and DRAM init is generally very sensitive about such things. Finally, for those things that are errors, print them at an error level, not a debug level. Change-Id: Ifa86b019dfd5f8ae6c8a1da2a35b5d0808dc3623 Signed-off-by: Ronald G. Minnich <rminnich@google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/60100 Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Commit-Queue: Ronald G. Minnich <rminnich@chromium.org> Tested-by: Ronald G. Minnich <rminnich@chromium.org> Reviewed-on: http://review.coreboot.org/4359 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-12-12exynos5250: Correct DDR3 Phy-reset value names.Hung-Te Lin
The name "LPDDR3PHY_CTRL_PHY_RESET_OFF" is not appropriate because the real phy-reset is a low-active pin, so "off(0)" will trigger "start to reset". To prevent confusion, we should rename the constants to "RESET_ENABLE" and "RESET_DISABLE". Change-Id: Iccba5ef3a2e992f877dea90741f0308c161758c9 Reviewed-on: https://gerrit.chromium.org/gerrit/61081 Tested-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: David Hendricks <dhendrix@chromium.org> Commit-Queue: Hung-Te Lin <hungte@chromium.org> Reviewed-on: http://review.coreboot.org/4357 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-12-12exynos5420: Setup clocks for MMC bus controller.Hung-Te Lin
To configure source clocks on Exynos 5420 for MMC drivers. Some registers are different from the 5250. FSYS now has two parts and MMC uses FSYS2. The MMC block uses MPLL as the clock source. The "high-speed" MMC interface runs as 52MHz, so divider is set accordingly. Also, the MMC driver has changed from MSHCI (Mobile Storage Host Controller Interface) to DWMCI (DesignWare MMC Controller Interface). Change-Id: I9ba9cf43e2f2dcd9da747888c0c7676bd545177b Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/60858 Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/4354 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-09-28exynos5420: Fix build warningAllen Martin
Fix "set but not used" variable warning with gcc 4.7.3 Change-Id: Ia27291ecb4f993c4ba6f29b134167dc23a449bf5 Signed-off-by: Allen Martin <amartin@nvidia.com> Reviewed-on: http://review.coreboot.org/3949 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Gabe Black <gabeblack@chromium.org>
2013-07-11cpu: Fix spellingMartin Roth
Change-Id: I69c46648de0689e9bed84c7726906024ad65e769 Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/3729 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10i2c: Change the type of the data parameter to uint8_t.Gabe Black
Data is intended to be a byte array, so it should be described by a type which has a fixed size equal to an 8 bit byte. Also, the data passed to write shouldn't be modified and can be const. Change-Id: I6466303d962998f6c37c2d4006a39c2d79a235c1 Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3721 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10armv7/exynos5420: Remove the extra reopen when reading SPI.Hung-Te Lin
The workaround of re-opening device in exynos_spi_read has been fixed by the new correct open/close and xfer procedure. It's safe to be removed now. Change-Id: I6b1bf717c916903999a137998a578b0a866829bd Signed-off-by: Hung-Te Lin <hungte@chromium.org> Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3715 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10armv7/exynos5420: Apply new implementation for SPI transmission.Hung-Te Lin
Switch spi_xfer and exynos_spi_read to use the new spi_rx_tx function. Change-Id: I01ab43509df1319672bec30dd111f98001d655d0 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3714 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10armv7/exynos5420: Add output ability and half-duplex mode in SPI driver.Hung-Te Lin
The SPI driver (exynos_spi_rx_tx) was implemented with only "read" ability and only full-duplex mode. To communicate with devices like ChromeOS EC, we need both output (tx) and half-duplex (searching frame header) features. This commit adds a spi_rx_tx that can handle all cases we need. Change-Id: I6aba3839eb0711d49c143dc0620245c0dfe782d8 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3713 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10armv7/exynos5420: Revise SPI open/close/reset procedure.Hung-Te Lin
The original Exynos SPI open/close procedure was copied from U-Boot SPL with some assumptions that only works in SPL stage. For example, it tries to always work in 4-byte transmission mode with only RX data is swapped, and claims a packet for initial address command (and with incorrect size). This commit revises open/close and reset so only the required SPI registers are configured. Change-Id: Ieba1f03d80a8949c39a6658218831ded39853744 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3712 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10armv7/exynos5420: Provide configuration for SPI0~SPI2.Hung-Te Lin
Fill the SPI device parameters for spi_setup_slave on Exynos 5420. Change-Id: I10b4b9e6cfe46d7bfa34e80e3727c7e7da99ba9d Signed-off-by: Hung-Te Lin <hungte@chromium.org> Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3711 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>