summaryrefslogtreecommitdiff
path: root/src/cpu/samsung
AgeCommit message (Collapse)Author
2013-07-11cpu: Fix spellingMartin Roth
Change-Id: I69c46648de0689e9bed84c7726906024ad65e769 Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/3729 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10i2c: Change the type of the data parameter to uint8_t.Gabe Black
Data is intended to be a byte array, so it should be described by a type which has a fixed size equal to an 8 bit byte. Also, the data passed to write shouldn't be modified and can be const. Change-Id: I6466303d962998f6c37c2d4006a39c2d79a235c1 Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3721 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10armv7/exynos5420: Remove the extra reopen when reading SPI.Hung-Te Lin
The workaround of re-opening device in exynos_spi_read has been fixed by the new correct open/close and xfer procedure. It's safe to be removed now. Change-Id: I6b1bf717c916903999a137998a578b0a866829bd Signed-off-by: Hung-Te Lin <hungte@chromium.org> Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3715 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10armv7/exynos5420: Apply new implementation for SPI transmission.Hung-Te Lin
Switch spi_xfer and exynos_spi_read to use the new spi_rx_tx function. Change-Id: I01ab43509df1319672bec30dd111f98001d655d0 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3714 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10armv7/exynos5420: Add output ability and half-duplex mode in SPI driver.Hung-Te Lin
The SPI driver (exynos_spi_rx_tx) was implemented with only "read" ability and only full-duplex mode. To communicate with devices like ChromeOS EC, we need both output (tx) and half-duplex (searching frame header) features. This commit adds a spi_rx_tx that can handle all cases we need. Change-Id: I6aba3839eb0711d49c143dc0620245c0dfe782d8 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3713 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10armv7/exynos5420: Revise SPI open/close/reset procedure.Hung-Te Lin
The original Exynos SPI open/close procedure was copied from U-Boot SPL with some assumptions that only works in SPL stage. For example, it tries to always work in 4-byte transmission mode with only RX data is swapped, and claims a packet for initial address command (and with incorrect size). This commit revises open/close and reset so only the required SPI registers are configured. Change-Id: Ieba1f03d80a8949c39a6658218831ded39853744 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3712 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10armv7/exynos5420: Provide configuration for SPI0~SPI2.Hung-Te Lin
Fill the SPI device parameters for spi_setup_slave on Exynos 5420. Change-Id: I10b4b9e6cfe46d7bfa34e80e3727c7e7da99ba9d Signed-off-by: Hung-Te Lin <hungte@chromium.org> Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3711 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10armv7/exynos5420: Change SPI module to standard <spi-generic> interface.Hung-Te Lin
The SPI module in Exynos 5420 didn't follow Coreboot's SPI API standard (spi-generic.h) and will be a problem when we want to share SPI drivers. This commit replaces exynos_spi_* by spi_* functions. Note, exynos_spi_read is kept and changed to a static function because its usage is different from the standard API "spi_xfer". Change-Id: I6de301bc6b46a09f87b0336c60247fedbe844ca3 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3710 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10armv7/exynos5420: Clean up unused header and constants in spi.cHung-Te Lin
Remove unused header and constant definition in SPI module. Change-Id: I339e603f48186e4a356e83518b0d0b4c907f11b8 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3709 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10armv7/exynos5420: Revise SPI device list in cpu.hHung-Te Lin
Add SPI0 and SPI2 to Exynos 5 SPI list, and correct structure names. Also removed the un-enumerated devices (SPI_BASE, base_spi()). Change-Id: Ica6d9a41f9619c8c61eab664d5e988dd4a428e09 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3708 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10arm/exynos: Correct SPI session commands.Hung-Te Lin
Some initialization / shutdown commands should be paired correctly in a SPI I/O session. For example, setting CS should be enabled and disabled in each read; and the bus width (byte or word) should be configured only when opening / closing the SPI device. Change-Id: Ie56b1c3a6df7d542f7ea8f1193ac435987f937ba Signed-off-by: Hung-Te Lin <hungte@chromium.org> Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3706 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10exynos5420: i2c: Fix error handling.Gabe Black
The functions which checked the status of a transfer would return success if the bus was no longer occupied, even if it's no longer occupied because the transfer failed. This change modifies those functions to return three possible values, 0 if the transfer isn't done, -1 if there was a fault, and 1 if the transaction completed successfully. Change-Id: Idcc5fdf73cab3c3ece0e96f14113a216db289e05 Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3704 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10exynos5420: Clock the mmc blocks off of the mpll.Gabe Black
The exynos manual suggests hooking the mmc ip blocks to the mpll. They had been set to use a different pll. This changes them over and modifies the divider so that the frequency stays the same. Change-Id: I85103388d6cc2c63d1ca004654fc08fcc8929962 Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3703 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10exynos5420: use speed parameter in i2c_init() for HSI2CDavid Hendricks
This allows us to set different speeds for each HSI2C bus. Change-Id: I50cc257aad9ef50025d0837b0516940b956efc02 Signed-off-by: David Hendricks <dhendrix@chromium.org> Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3701 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10exynos5420: Change some clock settings.Gabe Black
This change adjusts some clock settings so that they match U-Boot. There are three different changes. 1. Change the source for psgen from the oscillator clock to the pclk. 2. Change the pll feeding the SPI busses from epll to mpll, as suggested in the manual. 3. Change the SPI prescaller. Change-Id: Ib54a255bc14fc286629dac86db9b8cf8e75a610b Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3700 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10exynos5420: Fix the way the rate of the input clock for i2c buses is found.Gabe Black
The clock divider was being read from registers incorrectly which meant that the periph rate was wrong. Change-Id: I50efb62849ef29bdfb0efc56c49642d3edca094c Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3699 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10snow: Add flush to UART driver.Hung-Te Lin
Wait for UART FIFO to be ready. (Credit to dhendrix for finding the bits to test with.) Change-Id: Ib6733e422cbc1c61b942bd90d85f88a3f412d6ff Signed-off-by: Hung-Te Lin <hungte@chromium.org> Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3698 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10Exynos5420: Initialize USB PHYStefan Reinauer
... this is needed for libpayload to talk to USB devices. (forward ported from https://gerrit.chromium.org/gerrit/#/c/55554) Change-Id: I5a20864689efd0c0149775e6d85b658e0cc6715c Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3697 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10Exynos5250: Initialize USB PHYStefan Reinauer
... this is needed for libpayload to talk to USB devices. Change-Id: I7eb19003c9e96efb5fa7a3f97c7b15f3ef332687 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3696 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10Exynos: Only compile UART in if serial console is selectedStefan Reinauer
Change-Id: I5cddffc2e524aae7a31a8f94f67e03a5b7e15c82 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3695 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10Exynos5420: add code to make sure resume will work on DRAM.Ronald G. Minnich
Found during a perusal of u-boot changes. It looks important. For more info: http://git.chromium.org/gitweb/?p=chromiumos/third_party/u-boot.git;a=commit;h=56eab63922d2b2380518238ae03e8d69e99af4fe Change-Id: Ida2fe2a98be008a4bdfe594cf00d01a33b511b4f Signed-off-by: Ronald G. Minnich <rminnich@google.com> Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3693 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10Simplify early / bootblock console codeStefan Reinauer
Change-Id: I6b28bb95c7decbe3eed33b5b5a029bee48bbe403 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3691 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10exynos5420: Switch to fixed size types in dmc.h.Gabe Black
The members data structures in dmc.h are intended to have a particular size. Rather than assume that particular types are the right size, we should use types that are guaranteed to be the right size. Also, since the registers are at particular offsets as well, the structures should be packed. Change-Id: I9cc11d7451f92ba3eb85c6be88ecbc62c7a5652d Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3685 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10exynos5420: Revamp the high speed I2C driver.Gabe Black
The previous driver was a bit awkward and not entirely correct. This change primarily replaces the read/write functions with simpler and more robust (hopefully) version. Change-Id: I55f0ad8faec2de520e27577bd6dad9c0118d8171 Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3684 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10Samsung CPUs: Unify KconfigStefan Reinauer
For all other CPUs, we unconditionally include the CPU Kconfig files in the CPU directory, not in the vendor directory. Do the same thing for the Exynos CPUs. This allows us to make CPU dependent changes in the directory of that CPU alone. Also, drop some unused Kconfig variables from the Exynos Kconfig files. Change-Id: I4e4c22a0693988834e619dd33d121bf994ed57e8 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3683 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10exynos5420: update I2C code, add HSI2C/USI supportDavid Hendricks
This updates the low-level I2C code to handle the new high-speed HSI2C/USI inteface. It also outputs a bit more error information when things go wrong. Also adds some more error prints. Timeouts really need to be noted. In hsi2c_wait_for_irq, order the delay so that we do an initial sleep first to avoid an early-test that was kicking us out of the test too soon. We got to the test before the hardware was ready for us. Finally, test clearing the interrupt status register every time we wait for it on the write. Works. Change-Id: I69500eedad58ae0c6405164fbeee89b6a4c6ec6c Signed-off-by: Ronald G. Minnich <rminnich@google.com> Signed-off-by: David Hendricks <dhendrix@chromium.org> Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3681 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10ARM: when setting a GPIO to put, set the value, then the directionRonald G. Minnich
We saw a problem on x86 last year in which setting direction, then value, glitched the output and caused problems. Change this code to set the output, then the direction. Change-Id: I3e1e17ffe82ae270eea539530368a58c6cfe0ebe Signed-off-by: Ronald G. Minnich <rminnich@google.com> Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3679 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10exynox5420: Remove the 5250 clock registers and fix the SPI frequency.Gabe Black
The 5420 clock code still had a data structure in it for the 5250 clock registers which was used by some of the clock functions. That caused some clocks to be configured incorrectly, specifically the i2c clock which was running at about 80KHz instead of about 600KHz as configured by U-Boot. Also, the registers and bit positions used to set up the SPI bus were not consistent with U-Boot, and if the bus clock rate were set to 50MHz, a rate which has historically worked on snow, loading would fail. With these fixes the clock rate can be set to 50MHz and the device boots as much as is expected. I haven't yet measured the actual frequency of the bus to verify that it's now being calculated correctly. Change-Id: Id53448fcb6d186bddb3f889c84ba267135dfbc00 Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3678 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10PIT: memory setupRonald G. Minnich
Tested and working. Gets us to ramstage. Change-Id: Ib9ea4a6c912e8152246aaf4f1f084a4aa1626053 Signed-off-by: Ronald G. Minnich <rminnich@google.com> Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3677 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10exynos5420: add I2C8-10 to clock_get_periph_rate()David Hendricks
This adds entries for I2C8-10 to giant switch statement in clock_get_periph_rate(). It also eliminates the I2C peripheral's usage of clk_bit_info since it's confusing and error-prone. Change-Id: I30dfc4c9a03fbf16d08e44e074189fb9021edb6d Signed-off-by: David Hendricks <dhendrix@chromium.org> Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3676 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10exynos5420: Implement support for the pinmux as functions.Gabe Black
Change-Id: I5e0ec360597cd95cb6510fb32b04d8931e6a33db Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3674 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10exynos5250: De-switch-ify the pinmux configuration code.Gabe Black
The pinmux code for the exynos5250 was all bundled into a single, large function which contained a switch statement that would set up the pins for different peripherals within the SOC. There was also a "flags" parameter, the meaning of which, if any, depended on which peripheral was being set up. There are several problems with that approach. First, the code is inefficient in both time and space. The caller knows which peripheral it wants to set up, but that information is encoded in a constant which has to be unpacked within the function before any action can be taken. If there were a function per peripheral, that information would be implicit. Also, the compiler and linker are forced to include the entire function with all its cases even if most of them are never called. If each peripheral was a function, the unused ones could be garbage collected. Second, it would be possible to try to set up a peripheral which that function doesn't know about, so there has to be additional error checking/handling. If each peripheral had a function, the fact that there was a function to call at all would imply that the call would be understood. Third, the flags parameter is fairly opaque, usually doesn't do anything, and sometimes has to have multiple values embedded in it. By having separate functions, you can have only the parameters you actually want, give them names that make sense, and pass in values directly. Fourth, having one giant function pretends to be a generic, portable API, but in reality, the only way it's useful is to call it with constants which are specific to a particular implementation of that API. It's highly unlikely that a bit of code will need to set up a peripheral but have no idea what that peripheral actually is. Call sights for the prior pinmux API have been updated. Also, pinmux initialization within the i2c driver was moved to be in the board setup code where it really probably belongs. The function block that implements the I2C controller may be shared between multiple SOCs (and in fact is), and those SOCs may have different pinmuxes (which they do). Other places this same sort of change can be made are the pinmux code for the 5420, and the clock configuration code for both the 5250 and the 5420. Change-Id: Ie9133a895e0dd861cb06a6d5f995b8770b6dc8cf Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3673 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10ARM: Separate the early console (romstage) from the bootblock console.Gabe Black
It might be that you want an early console in romstage before RAM is up, but you can't or don't want to support the console all the way back in the bootblock. By making the console in those two different environments configurable seperately that becomes possible. On the 5250 console output as early as the bootblock works, but on the 5420 it only starts working in the ROM stage after clocks have been initialized. Change-Id: I68ae3fcb4d828fa8a328a30001c23c81a4423bb8 Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3671 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10exynos5420: Clear the framebuffer before making it uncacheableStefan Reinauer
If we clear the framebuffer and then flush it back to memory using cache operations, the writes are going to be full cachelines at a time. If we make it uncacheable first, the writes will be serialized writes of whatever sized chunks memset uses, probably 4 bytes or less. Change-Id: I960f87a370e97f9e91236ad796d931573bb3dbb8 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3668 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10exynos5420: Don't disable and re-enable the MMU when uncaching the framebufferStefan Reinauer
At one time it seemed to be necessary to disable and then re-enable the MMU when setting the framebuffer to be uncache-able due to bugs in the MMU management code. Since those bugs have been fixed, this is no longer necessary. Change-Id: I7ce825cf5eaaa95119364d780cba0935752e4632 Signed-off-by: Gabe Black <gabeblack@chromium.org> Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Reviewed-on: http://review.coreboot.org/3667 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10exynos5420: Simplify the graphics code by eliminating the unused color mapStefan Reinauer
The code that allocated space for the framebuffer was adding space for a vestigial color map which was never used. It was also passing around a structure which was used to calculate a single value which was already known when that structure was put together. Eliminate the extra space, and pass the single value instead of the structure. Change-Id: I29bc17488539dbe695908e47f0b80c07e102e17d Signed-off-by: Gabe Black <gabeblack@chromium.org> Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Reviewed-on: http://review.coreboot.org/3666 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10exynos5420: Fix some problems with the clock management code.Gabe Black
The code which figured out the rate of the input clock to a peripheral was doing several things wrong. First, it was using the wrong values when determing what the source of a clock was set to. Second, it was using the wrong offset into that register to find the current source setting. This change fixes the constants which select a clock source which get some more things working, but doesn't attempt to fix the bit position table. Change-Id: Id7482ee1c78cec274353bae3ce2dccb84705c66a Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3665 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10armv7: Reserve space BL1 and checksum header by specifying bootblock offset.Hung-Te Lin
Not all ARM systems need "BL1", and the layout of BL* and bootblock may be different (ex, Exynos 5250 may use a new BL1 with variable length checksum header). To support that better, define the real base address (and ROM offset) of boot block, and then we can post-processing ROM image file by filling data / checksum and any other information. Change-Id: I0e3105e52500b6b457371ad33a9aa546acf28928 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3664 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10exynos5420: Replace the 5250 clock logic with 5420.Gabe Black
The new code is stolen from U-Boot with little or no understanding of how it works. Change-Id: I3de7d25174072f6068d9d4fdaa308c0462296737 Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3658 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10exynos5420: Make the ps_hold_setup function public.Gabe Black
This function had been declared in a public header file, but was marked static when actually defined. Change-Id: Ia551a5a12e7dbaf7bc00861e085695145ab7b91a Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3657 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10Exynos5420: Clean up console codeStefan Reinauer
- Don't initialize console twice in the bootblock - remove printk in memory init that would mess up the UART - unconditionally run console_init() in romstage, as it is also unconditionally run in the bootblock. Change-Id: I983d011c6ca602445f447d17799c1b2a33e8bd1d Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3656 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10exynos5250: Clear the framebuffer before making it uncacheable.Gabe Black
If we clear the framebuffer and then flush it back to memory using cache operations, the writes are going to be full cachelines at a time. If we make it uncacheable first, the writes will be serialized writes of whatever sized chunks memset uses, probably 4 bytes or less. Change-Id: I1b81731cfed00ae091ba6357451ab186d16f559e Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3655 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10exynos5250: Don't disable and re-enable the MMU when uncaching the framebuffer.Gabe Black
At one time it seemed to be necessary to disable and then re-enable the MMU when setting the framebuffer to be uncache-able due to bugs in the MMU management code. Since those bugs have been fixed, this is no longer necessary. Change-Id: I5f7b9bd14dc9929efe1834ec9a258d388b8c94e9 Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3654 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10exynos5250: Simplify the graphics code by eliminating the unused color map.Gabe Black
The code that allocated space for the framebuffer was adding space for a vestigial color map which was never used. It was also passing around a structure which was used to calculate a single value which was already known when that structure was put together. Eliminate the extra space, and pass the single value instead of the structure. Change-Id: Ia6a41cefdf8b29fe7d68f9596a156eced6eb5df8 Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3652 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10exynos5250: When enabling the I2S pins, turn off pull ups/downs.Gabe Black
These pins will be driven by the internal controller which shouldn't have pull ups or downs in the pin fighting with them. Change-Id: I579aed84ace45d8f5f1d3ca64c064d98de842b57 Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3649 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10exynos5420: Replace the 5250 GPIO code with code that should work on 5420.Gabe Black
Change-Id: Iac6615240e94c74037afc801169c32d3ebc4ac03 Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3648 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10ARMv7: Clean up console codeStefan Reinauer
- Guard console_init() with CONFIG_EARLY_CONSOLE in bootblock - Don't initialize console twice in the bootblock - remove printk in memory init that would mess up the UART - unconditionally run console_init() in romstage, as it is also unconditionally run in the bootblock. Change-Id: I8f0d60877433162367074d0e55e01f935fd81f8e Signed-off-by: Stefan Reinauer <reinauer@google.com> Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3647 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10pit: Fix some settings for the exynos5420 CPU.Gabe Black
Some of the settings which were defaulted to or automatically selected for the exynos5420 which were inherited from the exynos5250 were not correct for this SOC. Change-Id: I11ffd8a6b80628405ac493fe2139f79c05d15d7e Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3645 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10pit: Create an exynos5420 directory which is nearly a copy of exynos5250.Gabe Black
This change creates an exynos5420 directory with code that will eventually implement support for the exynos5420 cpu from Samsung. Currently it's a copy of the exynos5250 directory with the name changed. There are going to be some problems where headers in src/cpu/samsung/exynos-common include headers in the exynos5250 directory directly. Change-Id: Ia8d7244310d32499238bbc171c0c668ec48178e1 Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3644 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10ARMv7: De-uboot-ify Exynos5250 GPIO codeStefan Reinauer
The Exynos GPIO code has three different APIs that, unfortunately, were widely used throughout the code base. This patch is cleaning up the mess. Change-Id: I09ccc7819fb892dbace9693c786dacc62f3f8eac Signed-off-by: Stefan Reinauer <reinauer@google.com> Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3643 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10ARMv7: De-uboot-ify Exynos5250 codeStefan Reinauer
When starting the Exynos5250 port, a lot of unneeded u-boot code was imported. This is an attempt to get rid of a lot of unneeded code before the port is used as a basis for further ARM ports. There is a lot more that can be done, including cleaning up the 5250's Kconfig file. Change-Id: I2d88676c436eea4b21bcb62f40018af9fabb3016 Signed-off-by: Stefan Reinauer <reinauer@google.com> Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3642 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10Update 3rdparty hash for latest ARM BL1 binariesStefan Reinauer
Change-Id: Ice28114e5f53f510d305cd85d095044e2f4bd7b2 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/3740 Reviewed-by: Gabe Black <gabeblack@chromium.org> Reviewed-by: David Hendricks <dhendrix@chromium.org> Tested-by: build bot (Jenkins)
2013-07-10samsung/exynos5250: unify codeStefan Reinauer
It turns out that the exynos5-common code previously imported from u-boot is not common code at all but very specific to the 5250 and not compatible with the 5450. Hence, unify the directories exynos5250 and exynos5-common. We will try to factor out common code while progressing with the 5450 port. Change-Id: Iab595e66fcd01eda8365c96fb8bef896f7602f03 Signed-off-by: Stefan Reinauer <reinauer@google.com> Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3641 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10Wield battle axe at ARM portStefan Reinauer
This patch unfortunately incorporates a number of changes, all of which are making future ARM ports easier. - drop cruft that came in with u-boot - move serial console from mainboard Kconfig to Exynos Kconfig - factor out non-board specific wakeup code - move generic bootblock code from mainboard to Exynos - actually call arch_cpu_init() - remove dead code - fix up copyright messages - remove snow_ prefix from a lot of code to reduce the noise when creating a new mainboard based on that code. Change-Id: Ic05326edf5a7e1a691c5ff841a604cb9e351b562 Signed-off-by: Stefan Reinauer <reinauer@google.com> Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3640 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-05-14EXYNOS5250/SNOW: fix the build script. Add a script to get the bl1.Ronald G. Minnich
build-snow got broken when the snow makefile improved. So fix it. While we're at it, create a script like the update-microcode scripts that gets the bl1. I thought about making this a common script but the various names and paths always evolve, leaving me thinking it's not worth it. This script is just a piece of the snow build script. Change-Id: I65c0f8697a978c62fe12533c4f0152d14dbaefda Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: http://review.coreboot.org/3238 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2013-05-07exynos5: select HAVE_MONOTONIC_TIMERDavid Hendricks
We have the monotonic timer implemented on exynos now, and this also enables helpful bootstage prints with timing info. Change-Id: I3baa4c9d70d4b4d059abd5e05eddcabd5258dbfd Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/3210 Reviewed-by: Aaron Durbin <adurbin@google.com> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2013-05-06exynos5250/snow: deprecate time.hDavid Hendricks
This re-introduces 2fde966 (http://review.coreboot.org/#/c/3177/) which was reverted due to unsatisfied dependencies. time.h We Hardly Knew Ye. This deprecates time.h which is currently only used by Exynos5250 and Snow. The original idea was to try and unify some of the various timer interfaces and has been supplanted by the monotonic timer API. timer_us() is now obsolete. timer_start() is now mct_start() and is exposed in exynos5250/clk.h. Change-Id: I8e60105629d9da68ed622e89209b3ef6c8e2445b Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/3201 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-05-05exynos5/5250: Update timer call sites to use monotonic timer APIDavid Hendricks
This goes thru various call sites where we used timer_us() and updates them to use the new monotonic timer API. udelay() changed substantially and now gracefully handles wraparound. Change-Id: Ie2cc86a4125cf0de12837fd7d337a11aed25715c Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/3176 Reviewed-by: Aaron Durbin <adurbin@google.com> Tested-by: build bot (Jenkins)
2013-05-04Revert "exynos5250/snow: deprecate time.h"David Hendricks
This reverts commit 2fde9668b47e74d1bfad2f1688a4481e6b966d04 Somehow this got merged before its dependencies. 3190 must be merged first, followed by 3176. However 3190 will fail while this patch is in. So the situation can't correct itself. Reverting this until the other two go in. Change-Id: I176f37c12711849c96f1889eacad38c00a8142c4 Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/3195 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2013-05-03exynos5250/snow: deprecate time.hDavid Hendricks
time.h We Hardly Knew Ye. This deprecates time.h which is currently only used by Exynos5250 and Snow. The original idea was to try and unify some of the various timer interfaces and has been supplanted by the monotonic timer API. timer_us() is now obsolete. timer_start() is now mct_start() and is exposed in exynos5250/clk.h. Signed-off-by: David Hendricks <dhendrix@chromium.org> Change-Id: I14ebf75649d101491252c9aafea12f73ccf446b5 Reviewed-on: http://review.coreboot.org/3177 Reviewed-by: Aaron Durbin <adurbin@google.com> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-05-03exynos5250: monotonic timer implementation (using MCT)David Hendricks
This implements the new monotonic timer API using the global multi-core timer (MCT). Change-Id: Id56249ff5d3e0f85808f5754954c83c0bc75f1c1 Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/3175 Reviewed-by: Aaron Durbin <adurbin@google.com> Tested-by: build bot (Jenkins)
2013-04-26exynos5250: uncomment $(INTERMEDIATE)David Hendricks
This makes the intermediate rule visible so BL1 gets automatically placed in the final image. Change-Id: Iffb0268e5bbcbe135f2d39863ed64fa302409a22 Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/3141 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2013-04-25google/snow: Add "wakeup" module for suspend/resume.Hung-Te Lin
The "wakeup" procedure will be shared by bootblock and romstage for different types of resume processes. Note, this commit does not include changes in romstage/bootblock to enable suspend/resume feature. Simply adding functions to handle suspend/resume. Verified by successfully building and booting Google/Snow firmware image. Change-Id: I17a256afb99f2f8b5e0eac3393cdf6959b239341 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: http://review.coreboot.org/3129 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-04-25arm/exynos: Allow DRAM controller to be initialized without clearing RAM ↵Hung-Te Lin
content. To support suspend/resume, PHY control must be reset only on normal boot path. So add a new param "mem_reset" to specify that. Verified to boot successfully on Google/Snow. Change-Id: Id49bc6c6239cf71a67ba091092dd3ebf18e83e33 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: http://review.coreboot.org/3128 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-04-23GOOGLE/SNOW: get graphics workingRonald G. Minnich
This adds support for display bring-up on Snow. It includes framebuffer initialization and LCD enable functions. Change-Id: I16e711c97e9d02c916824f621e2313297448732b Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/3116 Tested-by: build bot (Jenkins)
2013-04-23exynos5250: ungate the product ID registerDavid Hendricks
This makes sure that the product ID (PRO_ID) register can be read when the OS kernel is figuring out what kind of CPU it's running on. For historical reference, the original U-Boot code seems to have worked basically by accident here. The hardware has a quirk where by reading the value before gating the IP block keeps the value persistent. U-Boot reads the chip ID early on to distinguish between chip family, but we do not mix code the same way so we do not read the chip ID. Since the value has been read before the clock gating happens, the value remains available for the kernel to use during the decompression stage. We don't want to rely on that behavior when using coreboot. Instead the kernel should gate unused IPs. (credit to Gabe for finding symptom in the kernel) Change-Id: Iaa21e6e718b9000b5558f568020f393779fd208e Signed-off-by: Gabe Black <gabeblack@chromium.org> Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/3121 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2013-04-22GOOGLE/SNOW: fix stupid paren errorRonald G. Minnich
This simple error led to corrupted graphics. How annoying. Change-Id: I2295c0df0f1d16014a603dc5d66bd4d72f3fb7c9 Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: http://review.coreboot.org/3120 Reviewed-by: David Hendricks <dhendrix@chromium.org> Tested-by: build bot (Jenkins)
2013-04-19exynos5: eliminate lcd_base variableDavid Hendricks
The original imported code used "lcdbase" and "lcd_base" which quite predictably caused confusion and bugs. Let's put an end to this little bit of insanity. Change-Id: I4f995482cfbff5f23bb296a1e6d35beccf5f8a91 Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/3114 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins)
2013-04-19exynos5250: get xres and yres out of the device tree and into the panel ↵Ronald G. Minnich
descriptor We neglected to copy xres and yres out; now we do. Change-Id: Icc4a8eb35799d156b11274f71bcfb4a1d10e01e3 Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: http://review.coreboot.org/3111 Reviewed-by: David Hendricks <dhendrix@chromium.org> Tested-by: build bot (Jenkins)
2013-04-19[2/3] exynos5: modify thermal management unit code for corebootDavid Hendricks
This updates the Exynos TMU code for coreboot: - Remove dependency on device tree - Add Makefile entries Change-Id: I55e1b624d7c7b695b1253ec55f6ae3de8dc671bc Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/3107 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins)
2013-04-19[1/3] exynos5: import thermal management unit codeDavid Hendricks
This simply imports the Exynos TMU driver from u-boot. It is not built and thus should not break anything. Change-Id: I7861132fbf97f864e4250ffbda1ef3843f296ddc Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/3106 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins)
2013-04-19exynos5: move power_enable_hw_thermal_trip() prototypeDavid Hendricks
This moves the prototype for power_enable_hw_thermal_trip() to a generic location so it can be used by generalized thermal management code. The implementation will still be CPU-specific. Change-Id: Iae449cb8c72c8441dedaf65b73db9898b4730cef Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/3105 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins)
2013-04-17armv7/exynos5250: Deprecate sdelay in favor of udelayDavid Hendricks
This gets rid of the clock-tick based sdelay in favor of udelay(). udelay() is more consistent and easier to work with, and this allows us to carry one less variation of timers (and headers and sources...). Every 1 unit in the sdelay() argument was assumed to cause a delay of 2 clock ticks (@1.7GHz). So the conversion factor is roughly: sdelay(N) = udelay(((N * 2) / 1.7 * 10^9) * 10^6) = udelay((N * 2) / (1.7 * 10^3)) The sdelay() periods used were: sdelay(100) --> udelay(1) sdelay(0x10000) --> udelay(78) (rounded up to udelay(100)) There was one instance of sdelay(10000), which looked like sort of a typo since sdelay(0x10000) was used elsewhere. sdelay(10000) should approximate to about 12us, so we'll stick with that for now and leave a note. Change-Id: I5e7407865ceafa701eea1d613bbe50cf4734f33e Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/3079 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-04-17Samsung/exynos5250: convert unsigned {int,char} to u32/u8Ronald G. Minnich
The types are (esp. int) are confusing at times as to size. Make them definite as to size. Change-Id: Id7808f1f61649ec0a3403c1afc3c2c3d4302b7fb Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: http://review.coreboot.org/3103 Tested-by: build bot (Jenkins) Reviewed-by: Gabe Black <gabeblack@chromium.org> Reviewed-by: David Hendricks <dhendrix@chromium.org>
2013-04-13exynos5/snow: remove wait_ms arg from dp_controller_init()David Hendricks
This removes the wait_ms argument from the dp_controller_init(). The only delay involved is a constant 60ms delay that happens if everything else goes well. This delay is derived from the LCD spec so there's no reason it should be baked into the controller code. (This patch also has the side-effect of fixing a bug where we were delaying on an undefined value for wait_ms). Change-Id: I03aa19f2ac2f720524fcb7c795e10cc57f0a226e Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/3078 Reviewed-by: Gabe Black <gabeblack@chromium.org> Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-04-13Exynos5250: add a microsecond timerRonald G. Minnich
Add a microsecond timer, its declaration, the function to start it, and its usage. To start it, one calls timer_start(). From that point on, one can call timer_us() to find microseconds since the timer was started. We show its use in the bootblock. You want it started very early. Finally, the delay.h change having been (ironically) delayed, we create time.h and have it hold one declaration, for the timer_us() and timer_start() prototype. We feel that these two functions should become the hardware specific functions, allowing us to finally move udelay() into src/lib where it belongs. Change-Id: I19cbc2bb0089a3de88cfb94276266af38b9363c5 Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: http://review.coreboot.org/3073 Tested-by: build bot (Jenkins)
2013-04-11Exynos5250: Use new chip settings for the cpuRonald G. Minnich
Properly use the chip settings when configuring the CPU, at this point being purely graphics. Change-Id: I9bc2d32c1037653837937b314e4041abc0024835 Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: http://review.coreboot.org/3054 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2013-04-10GOOGLE/SNOW: add edp support to ramstageRonald G. Minnich
Add basic edp support to the ramstage. Not working. Change-Id: I15086e03417edca7426c214e67b51719d8ed9341 Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: http://review.coreboot.org/3055 Tested-by: build bot (Jenkins)
2013-04-10exynos5-common: Enable fimd_bypass and minor cleanupRonald G. Minnich
Basic cleanup, this code still does not work. Change-Id: I84ed9f08fd04cd8eb74cd860e0775d8c602f42d6 Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: http://review.coreboot.org/3049 Tested-by: build bot (Jenkins)
2013-04-10armv7: replace read/write macros with inlinesDavid Hendricks
This enables type checking for safety as to help prevent errors like http://review.coreboot.org/#/c/3038/ . Now compilation fails if the wrong type is passed into readb/readw/readl/writeb/writew/writel or other macros in io.h. This also deprecates readw/writew. The previous definition was 16-bits which is incorrect since wordsize on ARMv7 is 32-bits and there was only 1 instance of writew (#if 0'd anyway). Going forward we should always use read{8,16,32} and write{8,16,32} where N specifies the exact length rather than relying on ambiguous definition of wordsize. Since many macros relied on __raw_*, which were basically the same (minus data memory barrier instructions), this patch also gets rid of __raw_*. There were parts of the code which ended up using these macros consecutively, for example: setbits_le32(&regs->ch_cfg, SPI_CH_RST); clrbits_le32(&regs->ch_cfg, SPI_CH_RST); In such cases the safe versions of readl() and writel() should be used anyway. Note: This also fixes two dubious casts as to avoid breaking compilation. Change-Id: I8850933f68ea3a9b615d00ebd422f7c242268f1c Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/3045 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-04-10exynos5: Re-factor I2C codeDavid Hendricks
This re-factors the Exynos5 I2C code to be simpler and use the new API, and updates users accordingly. - i2c_read() and i2c_write() functions updated to take bus number as an argument. - Get rid of the EEPROM_ADDR_OVERFLOW stuff in i2c_read() and i2c_write(). If a chip needs special handling we should take care of it elsewhere, not in every low-level i2c driver. - All the confusing bus config functions eliminated. No more i2c_set_early_config() or i2c_set_bus() or i2c_get_bus(). All this is handled automatically when the caller does a transaction and specifies the desired bus number. - i2c_probe() eliminated. We're not a command-line utility. - Let the compiler place static variables automatically. We don't need any of this fancy manual data placement. - Remove dead code while we're at it. This stuff was ported early on and much of it was left commented out in case we needed it. Some also includes nested macros which caused gcc to complain. - Clean up #includes (no more common.h, woohoo!), replace debug() with printk(). Change-Id: I8e1f974ea4c6c7db9f33b77bbc4fb16008ed0d2a Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/3044 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-04-09replace device/i2c.h with simpler versionDavid Hendricks
The existing header was imported along with the Exynos code and left mostly unchanged. This is the first patch in a series intended to replace the imported u-boot I2C API with a much simpler and cleaner interface: - We only need to expose i2c_read() and i2c_write() in our public API. Everything else is board/chip-dependent and should remain hidden away. - i2c_read and i2c_write functions will take bus number as an arg and we'll eliminate i2c_get_bus and i2c_set_bus. Those are prone to error and end up cluttering the code since the user needs to save the old bus number, set the new one, do the read/write, and restore the old value (3 added steps to do a simple transaction). - Stop setting default values for board-specific things like SPD and RTC bus numbers (as if we always have an SPD or RTC on I2C). - Death to all the trivial inline wrappers. And in case there was any doubt, we really don't care about the MPC8xx. Though if we did then we would not pollute the public API with its idiosyncrasies. Change-Id: I4410a3c82ed5a6b2e80e3d8c0163464a9ca7c3b0 Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/3043 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-04-08exynos5250: add missing address-of operator in UART driverDavid Hendricks
This adds a missing address-of operator. This was a subtle bug that didn't seem to cause problems at first since the serial console appeared to work. However it caused an imprecise external abort which became apparent later on when aborts were unmasked in the kernel via the CPSR_A bit. (credit goes to Gabe Black for finding this) Signed-off-by: Gabe Black <gabeblack@chromium.org> Signed-off-by: David Hendricks <dhendrix@chromium.org> Change-Id: I80a33b147d92d559fa8fefbe7d5642235deb9aea Reviewed-on: http://review.coreboot.org/3038 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-04-08snow/exynos5250: move board-specific power stuff to mainboard dirDavid Hendricks
This moves highly board-specific code out from the Exynos5250 power_init() into Snow's romstage.c. There's no reason the CPU- specific code should care about which PMIC we are using and which bus it is on. Change-Id: I52313177395519cddcab11225fc23d5e50c4c4e3 Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/3034 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-04-06exynos5250: add a chip.h file for the display register settingsRonald G. Minnich
Display hardware is part of this SOC, and we need to be able to set certain variables in devicetree.cb. This chip file contains the initial things we think we need to set. Change-Id: I16f2d4228c87116dbeb53a3c9f3f359a6444f552 Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: http://review.coreboot.org/3031 Reviewed-by: David Hendricks <dhendrix@chromium.org> Tested-by: build bot (Jenkins)
2013-04-05exynos5-common: get rid of displayport trial codeRonald G. Minnich
This was a first pass at display port support, we have realized that it was ultimately a bad path. The display hardware is intimately tied into a specific cpu and mainboard combination, and the code has to be elsewhere. The devicetree formatting is ugly, but it matters not: it's changing soon. Change-Id: Iddce54f9e7219a7569315565fac65afbbe0edd29 Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: http://review.coreboot.org/3029 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-03-29exynos5250: Add function for configuring L2 cacheDavid Hendricks
This adds a new function to configure L2 cache for the exynos5250 and deprecates the old function. Change-Id: I9562f3301aa1e2911dae3856ab57bb6beec2e224 Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2949 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Gabe Black <gabe.black@gmail.com> Tested-by: build bot (Jenkins)
2013-03-27exynos5250: assign RAM resources in cpu_init()David Hendricks
This moves the ram resource allocation into cpu_init() so that we no longer rely on declaring a domain in devicetree.cb (which is kind of weird for this platform). This does not cause any actual changes to the coreboot memory table, and paves the way for further updates to Snow's devicetree. Change-Id: I141277f59b5d48288f409257bf556a1cfa7a8463 Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2923 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-26Revert "samsung/exynos5: add resource functions for the display port"David Hendricks
This reverts commit 9427ca151e44644238b1b52138894195a9f5175f Looks like we were a bit too anxious to see this one get in. The devicetree.cb change seems to have broken things. coreboot memory table: 0. 0000000050000000-000000005000ffff: RESERVED 1. 00000000bff00000-00000000bfffffff: CONFIGURATION TABLES 2. 0000014004000000-00000140044007ff: RESERVED Before this patch: coreboot memory table: 0. 0000000040000000-00000000bfefffff: RAM 1. 00000000bff00000-00000000bfffffff: CONFIGURATION TABLES Change-Id: I618e4f1976265d56cfd6a61d0c5736c55a0f3cec Reviewed-on: http://review.coreboot.org/2914 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2013-03-26samsung/exynos5: add resource functions for the display portRonald G. Minnich
This does NOT turn on the graphics. The device tree has been changed enough so that, at the very least, the correct functions are called at the correct time, with the correct paramaters. We decided to yank the I2C entries as they did not obvious function and might not even have been correct. Not working, seemingly, but we need to add a 4M resource for memory, and it seems it needs to be fixed at the address shown. This address was chosen from current hardware. We realized that the display code should be part of the cpu -- that's how the hardware works! Change-Id: Ied65a554f833566be817540702f79a02e7b6cb6e Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: http://review.coreboot.org/2615 Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2013-03-19armv7/exynos/snow: new cache maintenance APIDavid Hendricks
This adds a new API for cache maintenance operations. The idea is to be more explicit about operations that are going on so it's easier to manage branch predictor, cache, and TLB cleans and invalidations. Also, this adds some operations that were missing but required early on, such as branch predictor invalidation. Instruction and sync barriers were wrong earlier as well since the imported API assumed we compield with -march=armv5 (which we don't) and was missing wrappers for the native ARMv7 ISB/DSB/DMB instructions. For now, this is a start and it gives us something we can easily use in libpayload for doing things like cleaning and invalidating dcache when doing DMA transfers. TODO: - Set cache policy explicitly before re-enabling. Right now it's left at default. - Finish deprecating old cache maintenance API. - We do an extra icache/dcache flush when going from bootblock to romstage. Change-Id: I7390981190e3213f4e1431f8e56746545c5cc7c9 Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2729 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-14exynos5250: add RAM resource beginning at physical addressDavid Hendricks
The original code attempted to reserve a space in RAM for coreboot to remain resident. This turns out not to be needed, and breaks things for the kernel since the exynos5250-smdk5250 kernel device tree starts RAM at 0x40000000. (This patch was originally by Gabe, I'm just uploading it) Change-Id: I4536edaf8785d81a3ea008216a2d57549ce5edfb Signed-off-by: Gabe Black <gabeblack@chromium.org> Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2698 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins)
2013-03-13exynos5250/snow: enable branch predictionDavid Hendricks
This enables branch prediction. We can probably find a better place to do this, but for now we'll do it in snow's romstage main(). Change-Id: I86c7b6bc9e897a7a432c490fb96a126e81b8ce72 Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2701 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-13exynos5250: Don't set PS_HOLD in bootblock_cpu_initDavid Hendricks
PS_HOLD gets set in exynos' power_init(). Change-Id: Ib08e0afcad23cbd07dc7e3727fd958a1bc868b5a Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2700 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-13exynos5250/snow: call PMIC's power_init() functionDavid Hendricks
Call the power_init() function. We appear to have forgotten about it when deprecating lowlevel_init_subsystems(), but it didn't seem to cause problems until we got to doing more interesting stuff recently. There are some clean-ups to do from the original code, such as not attempting to configure I2C from PMIC code, which we'll get around to in follow-up patches. (Credit to Gabe for spotting this) Change-Id: I6a59379e9323277d0b61469de9abe6d651ac5bfb Signed-off-by: Gabe Black <gabeblack@chromium.org> Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2699 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-07exynos5: add GPIO port enumsDavid Hendricks
This adds an enum for GPIO ports on the Exynos5. To make them useful, they are assigned the absolute MMIO address where a s5p_gpio_bank struct can point to. Change-Id: Ia539ba52d7393501d434ba8fecde01da37b0d8aa Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2602 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-06samsung/exynos5: add display port and framebuffer defines and initializationRonald G. Minnich
These are essential functions for setting up the display port and framebuffer, and also enable such things as aux channel communications. We do some very simple initialization in romstage, mainly set a GPIO so that the graphics is powering up, but the complex parts are done in the ramstage. This mirrors the way in which graphics is done in the x86 size. I've added a first pass at a real device, and put it in the mainboard Kconfig, hoping for corrections. Because startup is so complex, depending on device type, I've created a 'displayport' device that removes some of the complexity and makes the flow *much* clearer. You can actually follow the flow by looking at the code, which is not true on other implementations. Since display port is perhaps the main port used on these chips, that's a reasonable compromise. All parameters of importance are now in the device tree. Change-Id: I56400ec9016ecb8716ec5a5dae41fdfbfff4817a Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: http://review.coreboot.org/2570 Tested-by: build bot (Jenkins)
2013-03-04ARM: remove code that is IMHO a dangerous designRonald G. Minnich
OK, this is tl;dr. But I need to write this in hopes we make sure we don't put code like this into coreboot. Ever. Our excuse in this case is that it was imported, not obviously wrong, and easily changed. It made sense to get it in, make it work, then do a cleanup pass, because changing everything up front is almost impossible to debug. The exynos code has bunch of base register values, e.g. These are base addresses of things that look like a memory-mapped struct. To get these to a pointer, they created the following macro, which creates an inline function. static inline unsigned int samsung_get_base_##device(void) \ { \ return cpu_is_exynos5() ? EXYNOS5_##base : 0; \ } And then invoke it 31 times in a .h file, e.g.: SAMSUNG_BASE(clock, CLOCK_BASE) to create 31 functions. And then use it: struct exynos5_clock *clk = (struct exynos5_clock *)samsung_get_base_clock(); OK, what's wrong with this? It's easier to ask what's right with it. Answer: nothing. I have a long list of what's wrong, and I may leave some things out, but here goes: 1. the "function" can return a NULL if we're not on exynos5. Most uses of the code don't check the return value. 2. And why would this function be running, if we're not on an exynos5? Why compile it in? 3. Note the cast everywhere a samsung_get_base_xxx is used. The function returns an untyped variable, requiring the *user* to get two things right: the cast, and the function invocation. One can replace that _clock(); with _power(); in the code above, and they will be referencing the wrong registers, and they'll never get an error! We have a C compiler; use it to type data. 4. You're generating 31 functions using cpp each and every time the file is included. The C compiler has to parse these each time. It's not at all like a simple cpp macro which is only generated on use. 5. You can't tags or etags this code 6. In fact, any kind of analysis tool will be unable to do anything with this cpp magic. That's only a partial list. So what's the right way to do it? Just make typed constants, viz: Or, since I expect people will want the lower case function syntax, I've left it that way: Now we've got something that is efficient, and we don't even need to protect with any more. Hence this change. We've got something that is type checked, does not require users to cast on each use, will catch simple programming errors, can be analyzed with standard tools, and builds faster. So if we make a mistake: struct exynos5_clock *clk = samsung_get_base_adc(); We'll see it: src/cpu/samsung/exynos5250/clock.c: In function 'get_pll_clk': src/cpu/samsung/exynos5250/clock.c:183:3: error: initialization from incompatible pointer type [-Werror] which we would not have seen before. As a minor benefit, it shaves most of a second off the compilation. Change-Id: Ie67bc4bc038a8dd1837b977d07332d7d7fd6be1f Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: http://review.coreboot.org/2582 Tested-by: build bot (Jenkins)
2013-03-01GPLv2 notice: Unify all files to just use one space in »MA 02110-1301«Paul Menzel
In the file `COPYING` in the coreboot repository and upstream [1] just one space is used. The following command was used to convert all files. $ git grep -l 'MA 02' | xargs sed -i 's/MA 02/MA 02/' [1] http://www.gnu.org/licenses/gpl-2.0.txt Change-Id: Ic956dab2820a9e2ccb7841cab66966ba168f305f Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/2490 Tested-by: build bot (Jenkins) Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
2013-02-20Whitespace: Replace tab character in license text with two spacesPaul Menzel
For whatever reason tabs got inserted in the license header text. Remove one occurrence of that with the following command [1]. $ git grep -l 'MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.'$'\t' | xargs sed -i 's,MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.[ ]*,MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.\ \ ,' [1] http://sed.sourceforge.net/grabbag/tutorials/sedfaq.txt Change-Id: Iaf4ed32c32600c3b23c08f8754815b959b304882 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/2460 Tested-by: build bot (Jenkins) Reviewed-by: Jens Rottmann <JRottmann@LiPPERTembedded.de> Reviewed-by: Cristian Măgherușan-Stanciu <cristi.magherusan@gmail.com>