| Age | Commit message (Expand) | Author |
|---|---|---|
| 2014-08-14 | exynos5: Refactor crazy old U-Boot base address macros away | Julius Werner |
| 2014-08-07 | exynos5420: Set the CLK_DIV_CPERI1 value as per manual | David Hendricks |
| 2014-08-05 | exynos5420: get rid of old exynos5420_config_l2_cache() | David Hendricks |
| 2013-12-21 | exynos5420: Assign corect parent PLLs | David Hendricks |
| 2013-12-21 | exynos5420: Set SPLL to 400MHz | David Hendricks |
| 2013-12-21 | exynos5420: correct the PMS value for CPLL | David Hendricks |
| 2013-12-21 | exynos5420: init APLL at 1800MHz | David Hendricks |
| 2013-12-21 | exynos5xxx: use oscillator clock when changing ARM frequency | David Hendricks |
| 2013-12-21 | Pit: graphics | Ronald G. Minnich |
| 2013-07-10 | PIT: memory setup | Ronald G. Minnich |
| 2013-07-10 | exynos5420: Replace the 5250 clock logic with 5420. | Gabe Black |
| 2013-07-10 | pit: Create an exynos5420 directory which is nearly a copy of exynos5250. | Gabe Black |
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index : coreboot.git | |
| my copy of coreboot | gitea |
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