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2016-06-21intel/model_6ex: Prepare for dynamic CONFIG_RAMTOPKyösti Mälkki
Change-Id: I9bfaa53f8d09962d36df1e86a0edcf100bb08403 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/15229 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-21intel/car/cache_as_ram_ht.inc: Prepare for dynamic CONFIG_RAMTOPKyösti Mälkki
Change-Id: Idb0f621553e76e771a5d6f2d492675ccd989d947 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/15228 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-21intel/car/cache_as_ram.inc: Prepare for dynamic CONFIG_RAMTOPKyösti Mälkki
Change-Id: I02881ce465cb3835a6fa7c06b718aa42d0d327ec Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/15227 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-06-18intel: Fix romstage main() with asmlinkageKyösti Mälkki
Backport from haswell. Change-Id: I585639f8af47bd1d8c606789ca026c6d2d0cc785 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/15225 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-06-18intel/cache_as_ram_ht.inc: Fix includeKyösti Mälkki
Reference to CACHE_AS_RAM was from the days we had romcc boards using socket_mPGA605. Change-Id: If397db83a01adeda4dd18d8b4c6e89bf0984264a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/15224 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-06-18intel cache_as_ram: Fix typo in commentKyösti Mälkki
Change-Id: I2539e490e160e01cab2ad8d2086d2f242a88c640 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/15223 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-06-17intel/model_206ax: Move platform specific definesKyösti Mälkki
Change-Id: I3c517fc55dd333b1a457324f1d69aeb6f70acec2 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/15197 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
2016-06-17Move definitions of HIGH_MEMORY_SAVEKyösti Mälkki
This is more of ACPI S3 resume and x86 definition than CBMEM. Change-Id: Iffbfb2e30ab5ea0b736e5626f51c86c7452f3129 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/15190 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-06-17Fix some cbmem.h includesKyösti Mälkki
Change-Id: I36056af9f2313eff835be805c8479e81d0b742bf Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/15196 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-05-06{cpu,soc}/intel: remove unused smm_init() functionAaron Durbin
There used to be a need for an empty smm_init() function because initialize_cpus() called it even though nothing called initialize_cpus(). However, garbage collection at link time is implemented so there's no reason to provide an empty function to satisfy a symbol that is completely culled during link. Remove it. Change-Id: Ic13c85f1d3d57e38e7132e4289a98a95829f765a Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/14605 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-05-06cpu/intel/haswell: convert to using common MP and SMM initAaron Durbin
In order to reduce duplication of code use the common MP and SMM initialization flow. Change-Id: I80b5b94b62bdd001581eb56513a0d532fffb64e8 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/14596 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@google.com>
2016-05-04cpu/x86: remove BACKUP_DEFAULT_SMM_REGION optionAaron Durbin
Unconditionally provide the backup default SMM area API. There's no reason to guard the symbols behind anything since linker garbage collection is implemented. A board or chipset is free to use the code or not without needing to select an option. Change-Id: I14cf1318136a17f48ba5ae119507918190e25387 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/14561 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-05-02cpu/x86/mp_init: remove unused callback argumentsAaron Durbin
The BSP and AP callback declarations both had an optional argument that could be passed. In practice that functionality was never used so drop it. Change-Id: I47fa814a593b6c2ee164c88d255178d3fb71e8ce Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/14556 Tested-by: build bot (Jenkins) Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-03-10northbridge/intel/i440bx: Unify UDELAY selectionStefan Reinauer
Instead of manually including udelay_io.c in each romstage, select UDELAY_IO for all i440BX boards in the chipset. Change-Id: I411191927f3fba1d0749edcf79378e8013fb195a Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/13781 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-08x86 chipsets: utilize x86_setup_mtrrs_with_detect()Aaron Durbin
For all the chipsets which were performing the following sequence: x86_setup_fixed_mtrrs(); x86_setup_var_mtrrs(cpuid_eax(0x80000008) & 0xff, 2); Replace that with x86_setup_mtrrs_with_detect() since it is equivalent. Change-Id: I9f362dbf38942d675f615d22b9e5770ce65e5a08 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/13936 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
2016-02-26tree wide: Convert "if (CONFIG_.*_TPM.*)" to "if (IS_ENABLED(...))"Denis 'GNUtoo' Carikli
Change-Id: Ib73abb0ada7dfdfab3487c005719e19f51ef1812 Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org> Reviewed-on: https://review.coreboot.org/13779 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-02-14CPU/intel: Add missing license headersDamien Roth
Add missing license headers to files that have no coreboot header. Change-Id: Iaaa04b5dcbd446a2064ac68d501ae8e860486e36 Signed-off-by: Damien Roth <yves.r.roth@gmail.com> Reviewed-on: https://review.coreboot.org/13289 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-12Make MRC vs native a config rather than making a separate chipset for it.Vladimir Serbinenko
Tested by making lenovo x230 configurable despite pretty MRC bugs. Change-Id: Ia2a123f24334f5cd5f42473b7ce7f3d77c0e65b7 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: https://review.coreboot.org/13658 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-10cpu/intel/microcode: allow microcode to be loaded in romstageAaron Durbin
The previous usage of the intel microcode support supported using the library under ROMCC and ramstage. Allow for microcode support to be used in normal C-based romstage as well by: 1. Only using walkcbfs when ROMCC is defined. 2. Only using spinlocks if !__PRE_RAM__ The header file now unconditionally exposes the declarations of the supporting functions. Change-Id: I903578bcb4422b4c050903c53b60372b64b79af1 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/13611 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2015-12-06Remove #ifdef checks on Kconfig symbolsMartin Roth
In coreboot, bool, hex, and int type symbols are ALWAYS defined. Change-Id: I58a36b37075988bb5ff67ac692c7d93c145b0dbc Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12560 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-06fsp_model_406dx: use external microcode .h files for rangeleyMartin Roth
The microcode for the Rangeley chip is supplied as .h files in the Rangeley FSP POSTGOLD4 package. When the rangeley microcode gets put into the blobs directory, this can be reverted and the binary file put into the makefile. Change-Id: I30e7436f26a247bc9431f249becfa5fe8c581be7 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12335 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-02x86/smm: Initialize SMM on some CPUs one-by-oneDamien Zammit
We currently race in SMM init on Atom 230 (and potentially other CPUs). At least on the 230, this leads to a hang on RSM, likely because both hyperthreads mess around with SMBASE and other SMM state variables in parallel without coordination. The same behaviour occurs with Atom D5xx. Change it so first APs are spun up and sent to sleep, then BSP initializes SMM, then every CPU, one after another. Only do this when SERIALIZE_SMM_INITIALIZATION is set. Set the flag for Atom CPUs. Change-Id: I1ae864e37546298ea222e81349c27cf774ed251f Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Signed-off-by: Damien Zammit <damien@zamaudio.com> Reviewed-on: https://review.coreboot.org/6311 Tested-by: build bot (Jenkins) Tested-by: BSI firmware lab <coreboot-labor@bsi.bund.de> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-11-24cpu/intel/socket_FCBGA559: Add new socket for Atom D5xxDamien Zammit
Tested on Intel D510MO board, boots to UART console. Change-Id: I82a630c9836c099d0fcc62e019c20f328a75151d Signed-off-by: Damien Zammit <damien@zamaudio.com> Reviewed-on: http://review.coreboot.org/10066 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-11-20fsp1_0: Remove hardcoded microcode locationsMartin Roth
These are no longer needed. Test: Booted minnowmax. Change-Id: Ie77040f3506464c614760bd4d30280c8113373bd Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: http://review.coreboot.org/12468 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-11-16intel/fsp_model_406dx: Load APs microcode in model_406dx_initDavid Guckian
Load microcode to APs when performing model_406dx_init. The updated fsp1_0 driver calls TempRamInit API with a dummy microcode, so FSP will not handle the microcode load. Change-Id: Ib75f860a34c84bf13c0c6c31ebed13e5787f365e Signed-off-by: David Guckian <david.guckian@intel.com> Reviewed-on: http://review.coreboot.org/12436 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-11-16intel/fsp_rangeley: Load BSP microcode in bootblockDavid Guckian
Load microcode to BSP in bootblock so later on the FSP TempRamInit call will return with success. The updated fsp1_0 driver calls TempRamInit API with dummy microcode, so FSP will not handle the microcode load. If BSP is not loaded with microcode before calling TempRamInit API, the call will fail with error No Valid Microcode Was Found. Change-Id: I9c55acaf3353a759bb0119f0a5402a704ffb2c4a Signed-off-by: David Guckian <david.guckian@intel.com> Reviewed-on: http://review.coreboot.org/12367 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: York Yang <york.yang@intel.com>
2015-11-10cpu/intel: Add socket BGA1284Marc Jones
Add an additional Sandy(Ivy)bridge processor socket. Change-Id: I7eff7183d0c003e61fdda5350579f4d3dec7504d Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/12168 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: York Yang <york.yang@intel.com>
2015-10-31tree: drop last paragraph of GPL copyright headerPatrick Georgi
It encourages users from writing to the FSF without giving an address. Linux also prefers to drop that and their checkpatch.pl (that we imported) looks out for that. This is the result of util/scripts/no-fsf-addresses.sh with no further editing. Change-Id: Ie96faea295fe001911d77dbc51e9a6789558fbd6 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/11888 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-10-31sandybridge: Disable parallel CPU initializationNico Huber
Disable the parallel CPU initialization for model_206ax, that is Sandy Bridge and Ivy Bridge processors. We never did it the way that Intel recommends and it became unreliable with the introduction of SMM_MODULES in commit a3e41c0 Migrate 206ax to SMM_MODULES. Tested by booting kontron/ktqm77 2.6k times into Linux user space. No issues so far. Change-Id: Idffc352341419f22a36bf772534a5e11e711edf1 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: http://review.coreboot.org/12266 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-10-28cpu/intel/fsp_model_206ax: Load microcode in corebootMartin Roth
Intel's FSP 1.0 platforms are moving back to loading microcode in coreboot instead of in the FSP. Update the Ivy Bridge chips to be compatible. Change-Id: I4af155dea51e89ab9595b922c95ceade29a2dc52 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: http://review.coreboot.org/12196 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: York Yang <york.yang@intel.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-10-23cpu/intel: Move Power notification ASL code into `common/acpi`Paul Menzel
Commit 24813c14 (i945: Consolidate acpi/platform.asl) creates the file in the directory `src/cpu/intel/model_6dx/acpi`, although the devices can also use different Intel CPU models like, for example, `intel/model_6ex` on the Lenovo T60. Therefore move the file to the directory `src/cpu/intel/common/acpi` so that other devices, like Intel GM45 based devices, can also include it. Change-Id: I90126b66a4d70468923622a8e3aebadeafcbf96f Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/11880 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-10-22Revert "Remove sandybridge and ivybridge FSP code path"Martin Roth
Please don't remove chipsets and mainboards without discussion and input from the owners. Someone was asking about cougar canyon 2 just a couple of weeks ago - there's obviously still interest. This reverts commit fb50124d22014742b6990a95df87a7a828e891b6. Change-Id: Icd7dcea21fa4a7808b25bb8727020701aeebffc9 Signed-off-by: Martin Roth <martinroth@google.com> Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: http://review.coreboot.org/12128 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-10-15cpu/mtrr.h: Fix macro names for MTRR registersAlexandru Gagniuc
We use UNDERSCORE_CASE. For the MTRR macros that refer to an MSR, we also remove the _MSR suffix, as they are, by definition, MSRs. Change-Id: Id4483a75d62cf1b478a9105ee98a8f55140ce0ef Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/11761 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2015-10-14Revert "Remove FSP Rangeley SOC and mohonpeak board support"Martin Roth
This chip is still being used and should not have been deleted. It's a current intel chip, and doesn't even require an ME binary. This reverts commit 959478a763c16688d43752adbae2c76e7764da45. Change-Id: I78594871f87af6e882a245077b59727e15f8021a Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: http://review.coreboot.org/11860 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc@marcjonesconsulting.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-10-08arch/x86/bootblock: Do not include non-code files in bootblock.SAlexandru Gagniuc
Since we now have more freedom in the bootblock linking step it no longer makes sense to use a monolithic bootblock.S. Code segments must still be included as the order in bootblock.S determines code flow. However, non-code flow related assembly stubs don't need to be directly included in bootblock.S Change-Id: I08e86e92d82bd2138194ed42652f268b0764aa54 Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/11792 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-10-07x86/bootblock: Use LDFLAGS_bootblock to enable garbage collectionAlexandru Gagniuc
The x86 bootblock linking is a mess. The bootblock is treated in a very special manner, and never received the update to link-time garbage collection. On newer x86 platforms, the boot media is no longer memory-mapped. That means we need to do a lot more setup in the bootblock. ROMCC is unsuitable for this task, and walkcbfs only works on memory-mapped CBFS. We need to revise the x86 bootflow for this new case. The approach this patch series takes is to perform CAR setup in the bootblock, and load the following stage (either romstage or verstage) from the boot media. This approach is not new, but has been done on our ARM ports for years. Since we will be adding .c files to the bootblock, it is prudent to use link-time garbage collection. This is also consistent to how we do things on other architectures. Unification FTW! Change-Id: I16b78456df56e0053984a9aca9367e2542adfdc9 Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/11781 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-10-03Remove FSP Rangeley SOC and mohonpeak board supportAlexandru Gagniuc
mohonpeak is the reference board for Rangeley. I doubt anyone uses it or cares about it. We jokingly refer to it as "Moron Peak". It's code with no known users, so we shouldn't be hauling it around for the eventuality that someone might use it in the future. Change-Id: Id3c9fc39e1b98707d96a95f2a914de6bbb31c615 Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/11790 Tested-by: build bot (Jenkins) Reviewed-by: Philipp Deppenwiese <zaolin@das-labor.org>
2015-10-03Remove sandybridge and ivybridge FSP code pathAlexandru Gagniuc
We already have two other code paths for this silicon. Maintaining the FSP path as well doesn't make much sense. There was only one board to use this code, and it's a reference board that I doubt anyone still owns or uses. Change-Id: I4fcfa6c56448416624fd26418df19b354eb72f39 Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/11789 Tested-by: build bot (Jenkins) Reviewed-by: Philipp Deppenwiese <zaolin@das-labor.org>
2015-10-03sandybridge ivybridge: Treat native init as first class citizenAlexandru Gagniuc
This is a sad story. We have three different code paths for sandybridge and ivybridge: proper native path, google MRC path, and, everyone's favorite: Intel FSP path. For the purpose of this patch, the FSP path lives in its own little world, and doesn't concern us. Since MRC was first, when native files and variables were added, they were suffixed with "_native" to separate them from the existing code. This can cause confusion, as the suffix might make the native files seem parasitical. This has been bothering me for many months. MRC should be the parasitical path, especially since we fully support native init, and it works more reliably, on a wider range of hardware. There have been a few board ports that never made it to coreboot.org because MRC would hang. gigabyte/ga-b75m-d3h is a prime example: it did not work with MRC, so the effort was abandoned at first. Once the native path became available, the effort was restarted and the board is now supported. In honor of the hackers and pioneers who made the native code possible, rename things so that their effort is the first class citizen. Change-Id: Ic86cee5e00bf7f598716d3d15d1ea81ca673932f Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/11788 Tested-by: build bot (Jenkins) Reviewed-by: Philipp Deppenwiese <zaolin@das-labor.org>
2015-09-30cpu: microcode: Use microcode stored in binary formatAlexandru Gagniuc
Using a copiler to compile something that's already a binary is pretty stupid. Now that Stefan converted most microcode in blobs to a plain binary, use the binary version. Change-Id: Iecf1f0cdf7bbeb7a61f46a0cd984ba341af787ce Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/11607 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-09-24coreboot: move TS_END_ROMSTAGE to one spotAaron Durbin
While the romstage code flow is not consistent across all mainboards/chipsets there is only one way of running ramstage from romstage -- run_ramstage(). Move the timestamp_add_now(TS_END_ROMSTAGE) to be within run_ramstage(). BUG=chrome-os-partner:44827 BRANCH=None TEST=Built and booted glados. TS_END_ROMSTAGE still present in timestamp table. Change-Id: I4b584e274ce2107e83ca6425491fdc71a138e82c Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11700 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-09-09intel/model_2065x/Kconfig: Don't use LAPIC_MONOTONIC_TIMERMartin Roth
The LAPIC_MONOTONIC_TIMER symbol doesn't do anything in the code unless UDELAY_LAPIC is selected. Since this chip uses UDELAY_TSC, LAPIC_MONOTONIC_TIMER generates a Kconfig warning and should be removed. Change-Id: I5caa60ca7ab9a24d25c184c85184f9492b453706 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: http://review.coreboot.org/11342 Tested-by: build bot (Jenkins) Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
2015-09-04x86: remove cpu_incs as romstage Make variableAaron Durbin
When building up which files to include in romstage there were both 'cpu_incs' and 'cpu_incs-y' which were used to generate crt0.S. Remove the former to settle on cpu_incs-y as the way to be included. BUG=chrome-os-partner:44827 BRANCH=None TEST=Built rambi. No include file changes. Change-Id: I8dc0631f8253c21c670f2f02928225ed5b869ce6 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11494 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-08-25Intel: Remove CACHE_MRC_BIN - 'selected' everywhere in KconfigMartin Roth
The Kconfig symbol CACHE_MRC_BIN was getting forced enabled everywhere it existed. Remove the Kconfig symbol and get rid of the #if statements surrounding the code. This fixes the Kconfig warning for Haswell & Broadwell chips: warning: (NORTHBRIDGE_INTEL_HASWELL && NORTHBRIDGE_INTEL_SANDYBRIDGE && NORTHBRIDGE_INTEL_SANDYBRIDGE_NATIVE && NORTHBRIDGE_INTEL_IVYBRIDGE && NORTHBRIDGE_INTEL_IVYBRIDGE_NATIVE && CPU_SPECIFIC_OPTIONS) selects CACHE_MRC_BIN which has unmet direct dependencies (CPU_INTEL_SOCKET_RPGA988B || CPU_INTEL_SOCKET_RPGA989) Change-Id: Ie0f0726e3d6f217e2cb3be73034405081ce0735a Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: http://review.coreboot.org/11270 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-07-29Add SoC specific microcode update check in ramstageRizwan Qureshi
Some Intel SoCs which support SGX feature, report the microcode patch revision one less than the actual revision. This results in the same microcode patch getting loaded again. Add a SoC specific check to avoid reloading the same patch. BUG=chrome-os-partner:42046 BRANCH=None TEST=Built for glados and tested on RVP3 CQ-DEPEND=CL:286054 Change-Id: Iab4c34c6c55119045947f598e89352867c67dcb8 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: ab2ed73db3581cd432f9bc84acca47f5e53a0e9b Original-Change-Id: I4f7bf9c841e5800668208c11b0afcf8dba48a775 Original-Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/287513 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11055 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2015-07-07x86: Drop -Wa,--divideStefan Reinauer
Fix up all the code that is using / to use >> for divisions instead. Change-Id: I8a6deb0aa090e0df71d90a5509c911b295833cea Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/10819 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-06-10model_2065x: Use common i945-ivy TSEG SMM init.Vladimir Serbinenko
Change-Id: I0302cbaeb45a55a4cfee94692eb7372f2b6b206d Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/10468 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-06-10model_206ax: Fix APIC map when HT is disabled.Vladimir Serbinenko
Change-Id: Idd05a16bd9bd31438437ef229aa87f55da8489fb Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/10467 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-06-10fsp_model_206ax: Use common i945-ivy tseg SMM init.Vladimir Serbinenko
Change-Id: Iac390b565d709b11bc7a6631b11315994b6e2c3c Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/10466 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-06-09stage_cache: use cbmem init hooksAaron Durbin
Instead of having the chipset code make the approrpiate calls at the appropriate places use the cbmem init hooks to take the appropriate action. That way no chipset code needs to be changed in order to support the external stage cache. Change-Id: If74e6155ae86646bde02b2e1b550ade92b8ba9bb Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/10481 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-06-09Create i945-ivy smm tseg init based on ivy code.Vladimir Serbinenko
CPU-side logic is unchanged for this range of CPUs as long as all of them use TSEG (or ASEG, just needs to be consistent). So uplift 206ax code while extracting southbridge and APIC code into separate functions. Change-Id: Ib365681d1da8115922c557fddcc59afc156826da Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/10465 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-06-08Remove empty lines at end of fileElyes HAOUAS
Used command line to remove empty lines at end of file: find . -type f -exec sed -i -e :a -e '/^\n*$/{$d;N;};/\n$/ba' {} \; Change-Id: I816ac9666b6dbb7c7e47843672f0d5cc499766a3 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: http://review.coreboot.org/10446 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-06-05device_ops: add device_t argument to acpi_fill_ssdt_generatorAlexander Couzens
`device_t device` is missing as argument. Every device_op function should have a `device_t device` argument. Change-Id: I7fca8c3fa15c1be672e50e4422d7ac8e4aaa1e36 Signed-off-by: Alexander Couzens <lynxis@fe80.eu> Reviewed-on: http://review.coreboot.org/9598 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-06-04Remove address from GPLv2 headersPatrick Georgi
Follow up for commit b890a12, some contributions brought back a number of FSF addresses, so get rid of them again. Change-Id: Idcd059f05523916f726b94931c2487ab028b7d72 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/10409 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
2015-06-02cbfs: new API and better program loadingAaron Durbin
A new CBFS API is introduced to allow making CBFS access easier for providing multiple CBFS sources. That is achieved by decoupling the cbfs source from a CBFS file. A CBFS source is described by a descriptor. It contains the necessary properties for walking a CBFS to locate a file. The CBFS file is then decoupled from the CBFS descriptor in that it's no longer needed to access the contents of the file. All of this is accomplished using the regions infrastructure by repsenting CBFS sources and files as region_devices. Because region_devices can be chained together forming subregions this allows one to decouple a CBFS source from a file. This also allows one to provide CBFS files that came from other sources for payload and/or stage loading. The program loading takes advantage of those very properties by allowing multiple sources for locating a program. Because of this we can reduce the overhead of loading programs because it's all done in the common code paths. Only locating the program is per source. Change-Id: I339b84fce95f03d1dbb63a0f54a26be5eb07f7c8 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9134 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-05-28smm: Merge configs SMM_MODULES and SMM_TSEGVladimir Serbinenko
SMM_TSEG now implies SMM_MODULES and SMM_MODULES can't be used without SMM_TSEG Remove some newly dead code while on it. Change-Id: I2e1818245170b1e0abbd853bedf856cec83b92f2 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/10355 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-05-28Migrate fsp_206ax to SMM_MODULESVladimir Serbinenko
This gets rid of ugly tseg_relocate for fsp_bd82x6x. This is adaptation of a3e41c089602c58409e8dfd4aceecbdd7d4f4a5b Change-Id: I4e80e6e98d3a6da3e3e480e9368fae1b3ed67cd6 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/10353 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-05-28Migrate 2065x to SMM_MODULESVladimir Serbinenko
This gets rid of ugly tseg_relocate for ibexpeak. This is backport of 29ffa54969414b833de5c61b507b061f920d650b to ibexpeak. Change-Id: I456d85abdbadb2fdccf77ca771e2518cf8b8c536 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/10352 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-05-28Migrate 206ax to SMM_MODULESVladimir Serbinenko
This gets rid of ugly tseg_relocate for bd82x6x. This is backport of 29ffa54969414b833de5c61b507b061f920d650b to bd82x6x. Change-Id: I0f52540851ce8a7edaac257a2aa83d543bb5e530 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/10351 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-05-28intel: Remove pstate_coord_type.Vladimir Serbinenko
Not used anywhere. Change-Id: I9bab092d285aaebdf9283ba08e23197f9785b3a6 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/10329 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Nicolas Reinecke <nr@das-labor.org>
2015-05-27Move TPM code out of chromeosVladimir Serbinenko
This code is not specific to ChromeOS and is useful outside of it. Like with small modifications it can be used to disable TPM altogether. Change-Id: I8c6baf0a1f7c67141f30101a132ea039b0d09819 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/10269 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-05-26acpigen: Remove all explicit length trackingVladimir Serbinenko
Change-Id: I88248d78c01b4b4e42a097889b5f4ddfdac3d966 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/7367 Tested-by: build bot (Jenkins) Reviewed-by: Rudolf Marek <r.marek@assembler.cz>
2015-05-26speedstep: Don't supply weak get_cst_entries.Vladimir Serbinenko
This should be overriden by mobo even if it's no-op override. weak function in this case would only hide real problems. Change-Id: I30dd671eb605b490a51153d00ae308c4bdef3d05 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/7368 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-05-21Remove address from GPLv2 headersPatrick Georgi
As per discussion with lawyers[tm], it's not a good idea to shorten the license header too much - not for legal reasons but because there are tools that look for them, and giving them a standard pattern simplifies things. However, we got confirmation that we don't have to update every file ever added to coreboot whenever the FSF gets a new lease, but can drop the address instead. util/kconfig is excluded because that's imported code that we may want to synchronize every now and then. $ find * -type f -exec sed -i "s:Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, *MA[, ]*02110-1301[, ]*USA:Foundation, Inc.:" {} + $ find * -type f -exec sed -i "s:Foundation, Inc., 51 Franklin Street, Suite 500, Boston, MA 02110-1335, USA:Foundation, Inc.:" {} + $ find * -type f -exec sed -i "s:Foundation, Inc., 59 Temple Place[-, ]*Suite 330, Boston, MA *02111-1307[, ]*USA:Foundation, Inc.:" {} + $ find * -type f -exec sed -i "s:Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.:Foundation, Inc.:" {} + $ find * -type f -a \! -name \*.patch \ -a \! -name \*_shipped \ -a \! -name LICENSE_GPL \ -a \! -name LGPL.txt \ -a \! -name COPYING \ -a \! -name DISCLAIMER \ -exec sed -i "/Foundation, Inc./ N;s:Foundation, Inc.* USA\.* *:Foundation, Inc. :;s:Foundation, Inc. $:Foundation, Inc.:" {} + Change-Id: Icc968a5a5f3a5df8d32b940f9cdb35350654bef9 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/9233 Tested-by: build bot (Jenkins) Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
2015-05-19intel/haswell: Drop MONOTONIC_TIMER_MSRPatrick Georgi
The variable was set on all haswell boards, so we can do it like on broadwell where the MSR based timer is assumed to be around, too. Change-Id: Id48ad7454d4cf83c3b1616b64687cdcfee4baa10 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/10256 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2015-05-13Include back the 306ax microcode again.Vladimir Serbinenko
In ee89435798022021026f511deddf0e3b401ad031 microcode for 306ax was forgotten in migration. Without microcode update my machine experiences random hangs and various misbehaviour. Change-Id: I61c704d88a8a0ed74a16fb3f80cce08e8515e6e2 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/10180 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-05-053rdparty: move to 3rdparty/blobsPatrick Georgi
There's now room for other repositories under 3rdparty. Change-Id: I51b02d8bf46b5b9f3f8a59341090346dca7fa355 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/10109 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-05-053rdparty: Move to blobsPatrick Georgi
To move 3rdparty to 3rdparty/blobs (ie. below itself from git's broken perspective), we need to work around it - since some git implementations don't like the direct approach. Change-Id: I1fc84bbb37e7c8c91ab14703d609a739b5ca073c Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/10108 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-05-05haswell: Link stage_cache_external_region into ramstage, tooSol Boucher
When CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM is set, this function is now linked into the ramstage as well as the romstage, since the former makes calls to it in panther builds. With this commit, it's possible to build panther using the config file from the Chromium OS project[1] if you supply the appropriate Intel descriptor and ME binary blobs and manually set CONFIG_VBOOT_VERIFY_FIRMWARE=n, CONFIG_BUILD_WITH_FAKE_IFD=n, and CONFIG_HAVE_ME_BIN=y. The resulting image is at least able to load a payload, although I only tested with depthcharge, which immediately complained, "vboot handoff pointer is NULL" and gave up the ghost. [1] https://chromium.googlesource.com/chromiumos/overlays/chromiumos-overlay/+/master/sys-boot/coreboot/files/configs/config.panther Change-Id: Id3bb510fa60129a4d36a0117dc33e7aa62d6c742 Signed-off-by: Sol Boucher <solb@chromium.org> Reviewed-on: http://review.coreboot.org/10046 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-05-04cpu: get rid of socket source codeStefan Reinauer
None of the sockets has actual configuration options, so the source for them is only cosmetical boilerplate. Hence, drop it. This reduces the sockets to be selectors for certain CPU types, which will be dropped in future commits, and mainboards will select their CPUs directly rather than through an additional layer of indirection (sockets) Change-Id: I0f52a65838875a73531ef8c92a171bb1a35be96e Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/9797 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
2015-04-30cpu/intel/haswell: remove dependency on socket_rpga989Matt DeVillier
Remove dependency of Haswell on cpu/intel/socket_rpga989 code, which is a carry-over from Sandy Bridge/Ivy Bridge and older coreboot conventions where features were structured around socket types. Add CPU-specific options to Kconfig and required subdirs to Makefile.inc which are curently included with socket_rpga989. TEST=successfully built and booted on google/panther Change-Id: Ic788e2928df107d11ea2d2eca7613490aaed395c Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: http://review.coreboot.org/10037 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-04-28Kconfig whitespace fixesMartin Roth
trivial whitespace fixes. Mostly changing leading spaces to tabs. Change-Id: I0bdfe2059b90725e64adfc0bdde785b4e406969d Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: http://review.coreboot.org/10000 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-28Fix some minor Kconfig issuesMartin Roth
- Remove Kconfig files that are no longer used: src/vencorcode/Kconfig src/soc/marvell/Kconfig - Fix the drivers/sil/Kconfig to point to drivers/sil/3114 which had the same code. - Make sure all Kconfig files have linefeeds at the end. This can cause problems, although it wasn't in this case. - Include cpu/intel/model_65x/Kconfig which was not being included. Change-Id: Ia57a1e0433e302fa9be557525dc966cae57059c9 Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: http://review.coreboot.org/9998 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-24fsp: Move fsp to fsp1_0Marc Jones
Prepare for FSP 1.1 integration by moving the FSP to a FSP 1.0 specific directory. See follow-on patches for sharing of common code. Change-Id: Ic58cb4074c65b91d119909132a012876d7ee7b74 Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/9970 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-04-22coreboot: common stage cacheAaron Durbin
Many chipsets were using a stage cache for reference code or when using a relocatable ramstage. Provide a common API for the chipsets to use while reducing code duplication. Change-Id: Ia36efa169fe6bd8a3dbe07bf57a9729c7edbdd46 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/8625 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-03-28build system: normalize linker script file namesPatrick Georgi
We have .lb, .lds, and .ld in the tree. Go for .ld everywhere. This is inspired by the commit listed below, but rewritten to match upstream, and split in smaller pieces to keep intent clear. Change-Id: I3126af608afe4937ec4551a78df5a7824e09b04b Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Based-On-Change-Id: I50af7dacf616e0f8ff4c43f4acc679089ad7022b Based-On-Signed-off-by: Julius Werner <jwerner@chromium.org> Based-On-Reviewed-on: https://chromium-review.googlesource.com/219170 Reviewed-on: http://review.coreboot.org/9107 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-03-17haswell: Fix monotonic timer integrationStefan Reinauer
In some previous attempt to enable monotonic timers on all platforms, the LAPIC monotonic timer was selected for Haswell devices, despite the fact that LAPIC timers are not used in coreboot on Haswell (See haswell Kconfig) and there already was a monotonic timer implementation enabled that just needed to be added for SMM as well. Change-Id: I6beb2977864e507956636860ed463e1991cea1ed Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/8702 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-03-13cpu/intel/2065x: add define for MSR IA32_FERR_CAPABILITYAlexander Couzens
BIOS Writer's Guide, rev 1.6.0, June 2012: This MSR controls whether and FERR message is sent over the system bus when unmasked x87 exceptions are generated. This feature is not supported from Sandy Bridge processor onwards. Change-Id: I19b260ca4b62f57c26989430693b00b9853bc441 Signed-off-by: Alexander Couzens <lynxis@fe80.eu> Reviewed-on: http://review.coreboot.org/8658 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-03-10x86 cache-as-ram: Remove BROKEN_CAR_MIGRATE optionKyösti Mälkki
This was added to handle cases of Intel FSP platforms that had EARLY_CBMEM_INIT but could not migrate CAR variables to CBMEM. These boards were recently fixed. To support combination of EARLY_CBMEM_INIT without CAR migration was added maintenance effort with little benefits. You had no CBMEM console for romstage and the few timestamps you could store were circulated via PCI scratchpads or CMOS nvram. Change-Id: I5cffb7f2b14c45b67ee70cf48be4d7a4c9e5f761 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/8636 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-02-28cpu/intel: (non-FSP) Remove microcode updates from treeAlexandru Gagniuc
Now that we use the microcode updates in the blobs repository, remove them from the main repo. Since the microcode updates are blobs, it makes more sense to ship them in the blobs repo rather than the main one. The update-microcodes.sh script is also deleted, as a more current version resides in 3rdparty. Change-Id: Iee74a3ede3b5eb684ef0386d270120e70173c1b4 Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/4531 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-02-28cpu/intel (non-FSP): Use microcode from blobs repositoryAlexandru Gagniuc
Now that microcode has been added to blobs, use that one instead of the one included in the tree. Microcode from the tree will be removed in a subsequent patch. Since the microcode updates are blobs, they belong in the blobs repository. This change may introduce a build failure if the "Generate from tree" microcode option is selected, but the blobs repository is not enabled. We have to live with this for now, until microcode is moved to blobs for all CPUs, at which point we may adjust Kconfig accordingly. Leave the FSP cpu alone for now, as that will need approval from SAGE. Change-Id: Ia77ba2e26c083da092449b04ab2323b91a2ca15b Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/4530 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-02-18cpu/intel/model_2065x|nehalem: remove unsupported MSR_PP0/MSR_PP1Alexander Couzens
They seem to have been copy-pasted during the backport from sandybridge. Change-Id: I2277bb90e6da2676b31eb2665b7c15f074e3d4bf Signed-off-by: Alexander Couzens <lynxis@fe80.eu> Reviewed-on: http://review.coreboot.org/8295 Tested-by: build bot (Jenkins) Reviewed-by: Peter Stuge <peter@stuge.se>
2015-02-16acpi: Generate valid ACPI processor objectsTimothy Pearson
The existing code generated invalid ACPI processor objects if the core number was greater than 9. The first invalid object instance was autocorrected by Linux, but subsequent instances conflicted with each other, leading to a failure to boot if more than 10 CPU cores were installed. The modified code will function with up to 99 cores. Change-Id: I62dc0eb61ae2e2b7f7dcf30e9c7de09cd901a81c Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/8422 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-02-11cpu/intel: >= nehalem: add comments to msr finalize'sAlexander Couzens
Improve documentation of lock down MSRs in finalize(). Most of these aren't documented in public MSRs. Change-Id: I4fc47bb9b71bdd7907aae65fc18b419a17ae8547 Signed-off-by: Alexander Couzens <lynxis@fe80.eu> Reviewed-on: http://review.coreboot.org/8294 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Peter Stuge <peter@stuge.se>
2015-02-06FSP & CBMEM: Fix broken cbmem CAR transition.Martin Roth
1) Save the pointer to the FSP HOB list to low memory at address 0x614. This is the same location as CBMEM_RESUME_BACKUP - the two aren't used in the same platform, so overlapping should be OK. I didn't see any documentation that actually said that this location was free to use, and didn't need to be restored after use in S3 resume, but it looks like the DOS boot vector gets loaded juat above this location, so it SHOULD be ok. The alternative is to copy the memory out and store it in cbmem until we're ready to restore it. 2) When a request for the pointer to a CAR variable comes in, pass back the location inside the FSP hob structure. 3) Skip the memcopy of the CAR Data. The CAR variables do not get transitioned back into cbmem, but used out of the HOB structure. 4) Remove the BROKEN_CAR_MIGRATE Kconfig option from the FSP platform. Change-Id: Iaf566dce1b41a3bcb17e4134877f68262b5e113f Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: http://review.coreboot.org/8196 Reviewed-by: Aaron Durbin <adurbin@google.com> Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-01-31intel/model_2065x: update microcodeNicolas Reinecke
Change-Id: I6c13518d2217bc823d409ab800bca011e76e9f25 Signed-off-by: Nicolas Reinecke <nr@das-labor.org> Reviewed-on: http://review.coreboot.org/8277 Tested-by: build bot (Jenkins) Reviewed-by: Philipp Deppenwiese <zaolin@das-labor.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-01-27CBMEM: Always use DYNAMIC_CBMEMKyösti Mälkki
Drop the implementation of statically allocated high memory region for CBMEM. There is no longer the need to explicitly select DYNAMIC_CBMEM, it is the only remaining choice. Change-Id: Iadf6f27a134e05daa1038646d0b4e0b8f9f0587a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/7851 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-01-27CBMEM: Do not use get_top_of_ram() with DYNAMIC_CBMEMKyösti Mälkki
The name was always obscure and confusing. Instead define cbmem_top() directly in the chipset code for x86 like on ARMs. TODO: Check TSEG alignment, it used for MTRR programming. Change-Id: Ibbe5f05ab9c7d87d09caa673766cd17d192cd045 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/7888 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-01-27vboot2: add verstageStefan Reinauer
This reverts the revert commit 5780d6f3876723b94fbe3653c9d87dad6330862e and fixes the build issue that cuased it to be reverted. Verstage will host vboot2 for firmware verification. It's a stage in the sense that it has its own set of toolchains, compiler flags, and includes. This allows us to easily add object files as needed. But it's directly linked to bootblock. This allows us to avoid code duplication for stage loading and jumping (e.g. cbfs driver) for the boards where bootblock has to run in a different architecture (e.g. Tegra124). To avoid name space conflict, verstage symbols are prefixed with verstage_. TEST=Built with VBOOT2_VERIFY_FIRMWARE on/off. Booted Nyan Blaze. BUG=None BRANCH=none Original-Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Original-Change-Id: Iad57741157ec70426c676e46c5855e6797ac1dac Original-Reviewed-on: https://chromium-review.googlesource.com/204376 Original-Reviewed-by: Randall Spangler <rspangler@chromium.org> (cherry picked from commit 27940f891678dae975b68f2fc729ad7348192af3) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I2a83b87c29d98d97ae316091cf3ed7b024e21daf Reviewed-on: http://review.coreboot.org/8224 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-01-03intel/model_206ax: update microcodeNicolas Reinecke
tested on ivy and sandy (t520/t420s & t530) Change-Id: Ie527e8c4804821764ecc42f7495573eff67828f7 Signed-off-by: Nicolas Reinecke <nr@das-labor.org> Reviewed-on: http://review.coreboot.org/7976 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-12-30intel CAR: Fix DCACHE_RAM_BASE for old socketsKyösti Mälkki
When using fixed MTRRs for CAR setup, CONFIG_DCACHE_RAM_BASE is ignored and was not correctly set on affected sockets and boards. It was still referenced in romstage linker script. This was discovered by clang builds failing for cases where DCACHE_RAM_BASE = 0, while gcc builds passed. The actual DCACHE_RAM_BASE programming is base = 0xd0000 - size, as taken from intel/cpu/cache_as_ram.inc. Change-Id: Ied5ab2e9683f12990f1aad48ee15eaf91133121c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/7887 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-12-19intel/truxton: Add dummy cache-as-ram regionKyösti Mälkki
Board has no chance of working without a cache_as_ram.inc, but without a specified CAR region we also break builds. Change-Id: I98e9db38c5e0a7bf4a1b8d2f8a693cc8d0c773b9 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/7863 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-12-16Intel FSP: Move to DYNAMIC_CBMEMKyösti Mälkki
Flag the boards with BROKEN_CAR_MIGRATE, as testing for EARLY_CBMEM_INIT is not enough to disable CBMEM console for romstage on these platforms. To have CBMEM early in ramstage, define get_top_of_ram() on sandy/ivy. Change-Id: Ieefc12099a0e043eb1a7e14bdc7c6e3d209b3d8f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/7468 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Martin Roth <gaumless@gmail.com>
2014-12-05FSP platform microcode: Update to remove Kconfig variableMartin Roth
Move the Kconfig variable into a .h file - this does not need to be in Kconfig. Change-Id: I1db20790ddb32e0eb082503c6c60cbbefa818bb9 Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/7646 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-12-03i945: Consolidate acpi/platform.aslVladimir Serbinenko
Change-Id: Iccb2dda8a427e483c04693e46b00e0bc2452a26b Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/7086 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2014-12-02Replace hlt with halt()Patrick Georgi
There were instances of unneeded arch/hlt.h includes, various hlt() calls that weren't supposed to exit (but might have) and various forms of endless loops around hlt() calls. All these are sorted out now: unnecessary includes are dropped, hlt() is uniformly replaced with halt() (except in assembly, obviously). Change-Id: I3d38fed6e8d67a28fdeb17be803d8c4b62d383c5 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: http://review.coreboot.org/7608 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-11-30Replace hlt() loops with halt()Patrick Georgi
Change-Id: I8486e70615f4c404a342cb86963b5357a934c41d Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: http://review.coreboot.org/7606 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-11-19acpigen: Add and use acpigen_write_method.Vladimir Serbinenko
The sequence of bytes to create a method is used several times in codebase. Put it into a function with logical arguments rather than duplicating magic bytes everywhere. Change-Id: I0e55d8dc7d5e8e92a521c7a83117c470d0614008 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/7347 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-11-15chromeos: provide stub functions for !CONFIG_VBOOT_VERIFY_FIRMWAREAaron Durbin
Instead of checking #if CONFIG_VBOOT_VERIFY_FIRMWARE #else #endif provide empty stub functions for !CONFIG_VBOOT_VERIFY_FIRMWARE. BUG=none BRANCH=baytrail TEST=Built and booted. Original-Change-Id: Id9d1843a0ec47c5a186c9a22ea3e4c13c89ec379 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/184841 (cherry picked from commit f6d95cf4ba6ce1bc0e1df4a0e9f655ad9fea9feb) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: If35ace863243e36399fc40c2802a2f7f2711e83b Reviewed-on: http://review.coreboot.org/7395 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-11-09haswell: Move to implicit length patchingVladimir Serbinenko
Change-Id: I662ba2a08f9a176a84b8318c8004aa5db7239567 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/7327 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>