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path: root/src/cpu/intel
AgeCommit message (Expand)Author
2015-03-13cpu/intel/2065x: add define for MSR IA32_FERR_CAPABILITYAlexander Couzens
2015-03-10x86 cache-as-ram: Remove BROKEN_CAR_MIGRATE optionKyösti Mälkki
2015-02-28cpu/intel: (non-FSP) Remove microcode updates from treeAlexandru Gagniuc
2015-02-28cpu/intel (non-FSP): Use microcode from blobs repositoryAlexandru Gagniuc
2015-02-18cpu/intel/model_2065x|nehalem: remove unsupported MSR_PP0/MSR_PP1Alexander Couzens
2015-02-16acpi: Generate valid ACPI processor objectsTimothy Pearson
2015-02-11cpu/intel: >= nehalem: add comments to msr finalize'sAlexander Couzens
2015-02-06FSP & CBMEM: Fix broken cbmem CAR transition.Martin Roth
2015-01-31intel/model_2065x: update microcodeNicolas Reinecke
2015-01-27CBMEM: Always use DYNAMIC_CBMEMKyösti Mälkki
2015-01-27CBMEM: Do not use get_top_of_ram() with DYNAMIC_CBMEMKyösti Mälkki
2015-01-27vboot2: add verstageStefan Reinauer
2015-01-03intel/model_206ax: update microcodeNicolas Reinecke
2014-12-30intel CAR: Fix DCACHE_RAM_BASE for old socketsKyösti Mälkki
2014-12-19intel/truxton: Add dummy cache-as-ram regionKyösti Mälkki
2014-12-16Intel FSP: Move to DYNAMIC_CBMEMKyösti Mälkki
2014-12-05FSP platform microcode: Update to remove Kconfig variableMartin Roth
2014-12-03i945: Consolidate acpi/platform.aslVladimir Serbinenko
2014-12-02Replace hlt with halt()Patrick Georgi
2014-11-30Replace hlt() loops with halt()Patrick Georgi
2014-11-19acpigen: Add and use acpigen_write_method.Vladimir Serbinenko
2014-11-15chromeos: provide stub functions for !CONFIG_VBOOT_VERIFY_FIRMWAREAaron Durbin
2014-11-09haswell: Move to implicit length patchingVladimir Serbinenko
2014-11-09ibexpeak, bd82x6x: Move to implicit length patchingVladimir Serbinenko
2014-11-08fsp_rangeley: Switch to per-device ACPIVladimir Serbinenko
2014-11-07cpu/intel/fsp_model_406dx: Invaild include pathEdward O'Callaghan
2014-10-29cpu/intel: Add configuration for socket LGA1155Damien Zammit
2014-10-27{arch,cpu,drivers,ec}: Don't hide pointers behind typedefsEdward O'Callaghan
2014-10-19x86 romstage: Move stack just below RAMTOPKyösti Mälkki
2014-10-19haswell baytrail: Enable RELOCATABLE_RAMSTAGEKyösti Mälkki
2014-10-16ACPI: Remove CONFIG_GENERATE_ACPI_TABLESVladimir Serbinenko
2014-09-12cpu/intel/fsp_model_206ax/model_206ax_init.c: Correct commentPaul Menzel
2014-08-30sandybridge: Add native sandybridgeVladimir Serbinenko
2014-08-18cpu/intel/fsp_model_406dx: code cleanupMartin Roth
2014-08-12cpu/intel/XXX/acpi.c: Fix coding style violationMartin Roth
2014-08-10model_106cx: don't blindly set Kconfig settingsAaron Durbin
2014-08-10cpu/intel/model_1067x: avoid null-pointer dereferencePatrick Georgi
2014-08-04cpu/intel: Fix out-of-bounds read due to off-by-one in conditionEdward O'Callaghan
2014-07-30model_206ax_init.c: Trivial - fix indentEdward O'Callaghan
2014-07-30cpu/intel: Add fsp version of model 406dx (Rangeley / Atom C2000)Martin Roth
2014-07-30cpu/intel/model_2065x/model_2065x_init.c: Remove dead codeEdward O'Callaghan
2014-07-29sandy/ivybridge: Native raminit.Vladimir Serbinenko
2014-07-23cpu/intel/fsp_model_206ax/model_206ax_init.c: Use macro `IS_ENABLED()`Paul Menzel
2014-07-19intel/model_2065x: Remove dead code.Vladimir Serbinenko
2014-07-17cpu,Makefile.inc: Trivial - drop trailing blank lines at EOFEdward O'Callaghan
2014-07-10intel/haswell: add vmx support w/Kconfig optionMatt DeVillier
2014-07-08cpu: Trivial - drop trailing blank lines at EOFEdward O'Callaghan
2014-07-05Drop redundant select CACHE_AS_RAMKyösti Mälkki
2014-07-05intel: Make monotonic timer a first class citizenEdward O'Callaghan
2014-06-17intel/model_2065x: Add 20652 microcode.Vladimir Serbinenko
2014-05-30cpu/intel/fsp_model_206ax: change realpath to readlinkMartin Roth
2014-05-17build: separate CPPFLAGS from CFLAGSPatrick Georgi
2014-05-17build: CPPFLAGS is more common than INCLUDESPatrick Georgi
2014-05-13cpu/intel: Add CPU socket rPGA988BZaolin
2014-05-10Replace SERIAL_CPU_INIT with PARALLEL_CPU_INITKyösti Mälkki
2014-05-09cougar_canyon2: Switch CPU/NB/SB to the shared FSP codeMartin Roth
2014-05-06Introduce stage-specific architecture for corebootFurquan Shaikh
2014-05-05haswell: move to mp_init libraryAaron Durbin
2014-05-03Move ARCH_* from board/Kconfig to cpu or soc Kconfig.Furquan Shaikh
2014-04-26Rename coreboot_ram stage to ramstageFurquan Shaikh
2014-04-26Get rid of HAVE_INIT_TIMER config optionFurquan Shaikh
2014-03-20rmodules: use rmodtool to create rmodulesAaron Durbin
2014-03-16Make POST device configurable.Idwer Vollering
2014-02-25Remove CACHE_ROM.Vladimir Serbinenko
2014-02-20intel/model_2065x: Fix APICID generation.Vladimir Serbinenko
2014-02-16haswell: backup the default SMM region on resumeAaron Durbin
2014-02-15coreboot: infrastructure for different ramstage loadersAaron Durbin
2014-02-12PCI: Drop includes under cpuKyösti Mälkki
2014-02-06usbdebug: Drop obsolete codeKyösti Mälkki
2014-02-01cpu/intel/model_2065x: Add model 20652Vladimir Serbinenko
2014-01-30cpu/intel: allow non-packaged scoped turbo settingAaron Durbin
2014-01-30coreboot: config to cache ramstage outside CBMEMAaron Durbin
2014-01-30vboot: provide empty vboot_verify_firmware()Aaron Durbin
2014-01-28intel: fix microcode compilation failure in bootblockAaron Durbin
2014-01-26src/cpu: Fix spelling of MTTR to MTRRPaul Menzel
2014-01-23intel/microcode: Remove leftover MICROCODE_INCLUDE_PATH.Vladimir Serbinenko
2014-01-16cpu/intel: Remove dummy terminators from microcode blobsAlexandru Gagniuc
2014-01-16cpu/intel: Make all Intel CPUs load microcode from CBFSAlexandru Gagniuc
2014-01-15nehalem/sandy/ivy/haswell: Enable WRPROT cache for all of flashKyösti Mälkki
2014-01-15Re-declare CACHE_ROM_SIZE as aligned ROM_SIZE for MTRRKyösti Mälkki
2014-01-11intel/fsp: Fix microcode includingPatrick Georgi
2013-12-21haswell: Update microcode revisionDuncan Laurie
2013-12-17cpu/intel: Do not rely on CBFS microcode having a terminatorAlexandru Gagniuc
2013-12-13cpu: Rename CPU_MICROCODE_IN_CBFS to SUPPORT_CPU_UCODE_IN_CBFSAlexandru Gagniuc
2013-12-12haswell: Export functions for CPU family+model and steppingDuncan Laurie
2013-12-12haswell: Update ULT microcode to rev 14hDuncan Laurie
2013-12-07haswell: VR controller configurationAaron Durbin
2013-12-07haswell: Misc power management setup and fixesDuncan Laurie
2013-12-05cpu: Remove BOARD_MICROCODE_CBFS_GENERATE Kconfig optionAlexandru Gagniuc
2013-12-04Add the Intel FSP 206ax CPU core supportMarc Jones
2013-12-01slippy/falco/peppy: Fix SPD GPIO initialization.Aaron Durbin
2013-11-25haswell: check for clean resetAaron Durbin
2013-11-24haswell: Update ULT microcode to 0x10Duncan Laurie
2013-11-24haswell: Remove limit on package C-stateDuncan Laurie
2013-11-24haswell: split microcode between ULT and non-ULTAaron Durbin
2013-11-24haswell: Update ULT microcode to rev 'a'Duncan Laurie
2013-11-24haswell: Configure PCH power sharing for ULTDuncan Laurie
2013-11-24haswell: calibrate 24MHz clock against BCLKAaron Durbin
2013-11-24haswell: configure c-statesAaron Durbin
2013-11-24haswell: Put each logical processor in its own P-state domainDuncan Laurie
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