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path: root/src/cpu/intel
AgeCommit message (Expand)Author
2013-03-18haswell: move definition of CORE_THREAD_COUNT_MSRAaron Durbin
2013-03-18haswell: Use SMM ModulesAaron Durbin
2013-03-17x86 intel: Add Firmware Interface Table supportAaron Durbin
2013-03-14haswell: Add ULT CPUID and updated microcodeDuncan Laurie
2013-03-14haswell: Properly Guard Engergy Policy by CPUIDAaron Durbin
2013-03-14haswell: Add initial support for Haswell platformsAaron Durbin
2013-03-07Fix socket LGA775Kyösti Mälkki
2013-03-01GPLv2 notice: Unify all files to just use one space in »MA 02110-1301«Paul Menzel
2013-02-14sconfig: rename lapic_cluster -> cpu_clusterStefan Reinauer
2013-02-11Intel: Replace MSR 0xcd with MSR_FSB_FREQPatrick Georgi
2013-02-09speedstep: Deduplicate some MSR identifiersPatrick Georgi
2013-02-09document Intel VMX locking behaviorMike Frysinger
2013-01-30Extend CBFS to support arbitrary ROM source media.Hung-Te Lin
2012-11-27Get rid of drivers classPatrick Georgi
2012-11-13Add spinlock to serialize Intel microcode updatesStefan Reinauer
2012-11-13Fix CONFIG_MAX_CPU set to 1 CPU build problemStefan Reinauer
2012-11-12ivybridge: Catch unknown CPU revisionsStefan Reinauer
2012-11-12Initialize the VMX MSRMarc Jones
2012-11-12Revert "Remove code that enables/disables VMX in coreboot on chromebooks."Marc Jones
2012-11-12sandybridge: Correct reporting of cores and threadsStefan Reinauer
2012-11-07Leave power control registers unlockedSameer Nanda
2012-11-06cpu/intel/model_1067x: Add proper c-state/p-state/thermal supportNico Huber
2012-11-06intel/socket_BGA956: enable speedstep, CAR, MMX, SSEPatrick Georgi
2012-11-05Overhaul speedstep codeNico Huber
2012-11-05Fix some indentation flaws and break very long linesNico Huber
2012-11-02Correct FSB reading in speedstep ACPINico Huber
2012-11-01Merge cpu/intel/acpi.h into cpu/intel/speedstep.hNico Huber
2012-10-30Add support for socket LGA775Stefan Tauner
2012-10-07Fix typo in mPGA603 socketKyösti Mälkki
2012-10-07Remove chip.h files without config structureKyösti Mälkki
2012-09-05buildsystem: Make CPU microcode updating more configurableAlexandru Gagniuc
2012-08-27Intel model_106cx: change CAR to HT-capableKyösti Mälkki
2012-08-22Auto-declare chip_operationsKyösti Mälkki
2012-08-09Synchronize rdtsc instructionsStefan Reinauer
2012-08-03Intel CPUs: Fix counting of CPU coresKyösti Mälkki
2012-07-31Revert "Use broadcast SIPI to startup siblings"Sven Schnelle
2012-07-31Revert "remove CONFIG_SERIAL_CPU_INIT"Sven Schnelle
2012-07-26CPU: Add option to set TCC activation offsetDuncan Laurie
2012-07-26ACPI: Add a method to notify OS to re-read _PPCDuncan Laurie
2012-07-26ACPI: Add function to write _PPC using NVSDuncan Laurie
2012-07-26Drop CONFIG_CPU_MODEL_NAME and fix CPU name displayed in logsStefan Reinauer
2012-07-26Enable Microcode in CBFS for all SandyBridge/IvyBridge systemsStefan Reinauer
2012-07-25Fix comment to reference IvyBridge, tooStefan Reinauer
2012-07-25Include SandyBridge Microcode when IvyBridge is enabledStefan Reinauer
2012-07-25Fix date output in Microcode updateStefan Reinauer
2012-07-24CPU: Set flex ratio to nominal TDP ratio in bootblockDuncan Laurie
2012-07-24CPU: Update ivybridge PP1 current limit valueDuncan Laurie
2012-07-24CPU: Add basic support for Nominal Configurable TDPDuncan Laurie
2012-07-24Config changes to support microcode in CBFSVadim Bendebury
2012-07-24Add microcode blob processingVadim Bendebury
2012-07-24Add code to read Intel microcode from CBFSVadim Bendebury
2012-07-24Rename microcode include file to be model agnosticVadim Bendebury
2012-07-24Properly identify ACPI C3 states in _CST table.Duncan Laurie
2012-07-24Remove code that enables/disables VMX in coreboot on chromebooks.Ronald G. Minnich
2012-07-04Intel cpus: Extend cache to cover complete Flash DeviceKyösti Mälkki
2012-07-04Intel model_106cx: change CAR to model_6exKyösti Mälkki
2012-07-04Intel cpus: delete dead CAR code and whitespace fixesKyösti Mälkki
2012-07-04Intel cpus: use CPU_ADDR_BITS from Kconfig during CARKyösti Mälkki
2012-07-02remove CONFIG_SERIAL_CPU_INITSven Schnelle
2012-07-02Use broadcast SIPI to startup siblingsSven Schnelle
2012-07-02Intel CPUs: execute microcode update only once per coreKyösti Mälkki
2012-06-19Enable Intel PECI on Model 6fx CPUsSven Schnelle
2012-05-29Drop config variable CPU_MODEL_INDEXStefan Reinauer
2012-05-08Clean up #ifsPatrick Georgi
2012-05-03Fix register corruption during Intel Microcode updateStefan Reinauer
2012-05-02Don't include console.h in microcode.c when compiling with ROMCCStefan Reinauer
2012-04-30Fix up Sandybridge C state generation codeStefan Reinauer
2012-04-30Rework ACPI CST table generationStefan Reinauer
2012-04-26microcode: print date of microcode and unify outputStefan Reinauer
2012-04-26Revamp Intel microcode update codeStefan Reinauer
2012-04-25Replace cache control magic numbers with symbolsPatrick Georgi
2012-04-06Fix support for RAM-less multi-processor initKyösti Mälkki
2012-04-05Add support for Intel Sandybridge CPUStefan Reinauer
2012-04-03Add support for Intel Turbo Boost featureStefan Reinauer
2012-04-02Apply cache-as-ram conditionally on socket mPGA604Kyösti Mälkki
2012-03-31Whitespace fixesPatrick Georgi
2012-03-31Intel cpus: get MAXPHYADDR at runtime for new CARKyösti Mälkki
2012-03-31Intel cpus: add hyper-threading CPU support to new CARKyösti Mälkki
2012-03-31Intel cpus: improve CPU compatibility of new CARKyösti Mälkki
2012-03-31Intel cpus: apply some good programming practices in new CARKyösti Mälkki
2012-03-31Intel cpus: cache actual size of the Flash ROM deviceKyösti Mälkki
2012-03-31Intel cpus: copy model_6ex CAR codeKyösti Mälkki
2012-03-25Intel cpus: Fix deadlock on hyper-threading initKyösti Mälkki
2012-03-17Intel cpus: Include CAR from socketKyösti Mälkki
2012-02-16Intel cpus: use CPU_PHYSMASK_HI define in CARKyösti Mälkki
2012-02-15Intel model_106cx: Use symbolic names for MTRR bitsKyösti Mälkki
2012-02-10Intel cpus: apply un-written naming rulesKyösti Mälkki
2012-02-09Add Intel Socket LGA771Sven Schnelle
2012-01-10MTRR: get physical address size from CPUIDSven Schnelle
2012-01-09ACPI: mark empty get_cst_entries() weakSven Schnelle
2011-11-01Remove XIP_ROM_BASEPatrick Georgi
2011-10-30Fix slow CAR execution introduced by 7c7d87182feb78cb2bc02fb3558bef56a41682c9Rudolf Marek
2011-10-28Get rid of the old romstage-as-bootblock ROM layoutPatrick Georgi
2011-10-28Get rid of AUTO_XIP_ROM_BASEPatrick Georgi
2011-10-25SPEEDSTEP: write _CST tablesSven Schnelle
2011-10-18Activate older Xeon P4 microcodesKyösti Mälkki
2011-09-09Crank up CPU speed on Intel Core and Core2 CPUsPatrick Georgi
2011-08-04cpu/intel/slot_1: Init L2 cache on SECC(2) CPUs.Keith Hui
2011-05-03Enable caching for ROM area in model_6ex/cache_as_ram.incSven Schnelle
2011-04-21more ifdef -> if fixesStefan Reinauer
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