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2020-01-09drivers/pc80/rtc: Separate {get|set}_option() prototypesKyösti Mälkki
Long-term plan is to support loading runtime configuration from SPI flash as an alternative, so move these prototypes outside pc80/. Change-Id: Iad7b03dc985550da903d56b3deb5bd736013f8f1 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38192 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-27cpu/intel/microcode: Apply more strict guard for assembly filesKyösti Mälkki
Change-Id: I8243be7c9a57402b2ac1cfa1c0552990d4a4ba74 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37891 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-12-26src/x86|cpu/intel: Hardcode FIT and IDMarshall Dawson
Revert two of the changes made in "arch|cpu/x86: Add Kconfig option for x86 reset vector" I6a814f7179ee4251aeeccb2555221616e944e03d The Intel FIT pointer and the ID section should be offsets from the top of flash, and aren't inherently tied to the reset vector or to bootblock. Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Change-Id: I2c9d5e2b2c4248c999d493a72d90cfddd92197cf Reviewed-on: https://review.coreboot.org/c/coreboot/+/37877 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Martin Roth <martinroth@google.com>
2019-12-19arch/x86,soc/intel: Drop RESET_ON_INVALID_RAMSTAGE_CACHEKyösti Mälkki
If stage cache is enabled, we should not allow S3 resume to load firmware from non-volatile memory. This also adds board reset for failing to load postcar from stage cache. Change-Id: Ib6cc7ad0fe9dcdf05b814d324b680968a2870f23 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37682 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-12-19src: Remove unused 'include <arch/cpu.h>'Elyes HAOUAS
Change-Id: Iaa236f07aed52ccb8c4839047894a14a9446a109 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36080 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-12-19src: Use '#include <smp/node.h>' when appropriateElyes HAOUAS
Change-Id: Icdd6b49751763ef0edd4c57e855cc1d042dc6d4d Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36373 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-12-18src: Remove unused 'include <pc80/mc146818rtc.h>'Elyes HAOUAS
Change-Id: I72d7b83ef8c7f9b5b4b4376839279eff9b0a5f8f Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37484 Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-17cpu/intel: Remove ROMCC header guards and codeElyes HAOUAS
Intel's platforms use a GCC compiled bootblock. Change-Id: I779d7115fee75df9356873e9cc66d43280821812 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37758 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-12-14bootblock: Provide some common prototypesKyösti Mälkki
The split of bootblock initialisation to cpu, northbridge and southbridge is not specific to intel at all, create new header <arch/bootblock.h> as AMD will want some of these too. Change-Id: I702cc6bad4afee4f61acf58b9155608b28eb417e Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37429 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-12-06arch|cpu/x86: Add Kconfig option for x86 reset vectorMarshall Dawson
Prepare for an implementation supporting the reset vector in RAM and not the traditional 0xfffffff0. Add a Kconfig symbol that can be used in place of hardcoded values. Change-Id: I6a814f7179ee4251aeeccb2555221616e944e03d Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37485 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-12-02src/: Remove g_ prefixes and _g suffixes from variablesPatrick Georgi
These were often used to distinguish CAR_GLOBAL variables that weren't directly usable. Since we're getting rid of this special case, also get rid of the marker. This change was created using coccinelle and the following script: @match@ type T; identifier old =~ "^(g_.*|.*_g)$"; @@ old @script:python global_marker@ old << match.old; new; @@ new = old if old[0:2] == "g_": new = new[2:] if new[-2:] == "_g": new = new[:-2] coccinelle.new = new @@ identifier match.old, global_marker.new; @@ - old + new @@ type T; identifier match.old, global_marker.new; @@ - T old; + T new; @@ type T; identifier match.old, global_marker.new; @@ - T old + T new = ...; There were some manual fixups: Some code still uses the global/local variable naming scheme, so keep g_* there, and some variable names weren't completely rewritten. Change-Id: I4936ff9780a0d3ed9b8b539772bc48887f8d5eed Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37358 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2019-11-29cpu/intel/common/fsb.c: Drop CAR_GLOBAL_MIGRATION supportArthur Heymans
Change-Id: I151090c8d7f670f121dc7e4cbebfd720034fde33 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37051 Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-25cpu/intel/slot_1: Move to C_ENVIRONMENT_BOOTBLOCKArthur Heymans
Console is not yet enabled in bootblock. This will be done in a different CL. Change-Id: Ic751d42a1969fb79fb50366f766d8796846a0bc4 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36774 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-11-25Kconfig: Drop the C_ENVIRONMENT_BOOTBLOCK symbolArthur Heymans
The romcc bootblock will be deprecated soon and most platforms use C_ENVIRONMENT_BOOTBLOCK already. This patch drops the CONFIG_C_ENVIRONMENT_BOOTBLOCK symbol and adds CONFIG_ROMCC_BOOTBLOCK where needed. Change-Id: I773a76aade623303b7cd95ebe9b0411e5a7ecbaf Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37154 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2019-11-25Drop superfluous C_ENVIRONMENT_BOOTBLOCK checksArthur Heymans
Some guarding is not needed because the linker drops the code, other guarding is not needed because all platforms using the code now have C_ENVIRONMENT_BOOTBLOCK. Change-Id: I3b1a94e709aa291e1156c854874d7bf461981f32 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37157 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-11-23Kconfig: comply to Linux 5.3's Kconfig language rulesPatrick Georgi
Kconfig became stricter on what it accepts, so accomodate before updating to a new release. Change-Id: I92a9e9bf0d557a7532ba533cd7776c48f2488f91 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37156 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2019-11-22cpu/intel/gen1/smmrelocate: Fix stale commentArthur Heymans
Change-Id: I91ed5f7cbcfa5c510bb8e74049ec860397d7dbba Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36659 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-11-22intel/smm: Provide common smm_relocation_paramsKyösti Mälkki
Pull in all copies of smm_relocation_params structs defined for intel platforms. Pull in all the inlined MSR accessors to the header file. Change-Id: I39c6cffee95433aea1a3c783b869eedfff094413 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34840 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-11-21Kconfig: Remove not found sourcesElyes HAOUAS
Change-Id: I3691a4162eecbd48321348e136f72b73da74e225 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37078 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-21nb/sb/cpu: Drop Intel Rangeley supportArthur Heymans
Relocatable ramstage, postcar stage and C_ENVIRONMENT_BOOTBLOCK are now mandatory features, which this platform lacks. Change-Id: I41589118579988617677cf48af5401bc35b23e05 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36980 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2019-11-20cpu/intel/car: Add EC software sync to Intel romstageTim Wawrzynczak
Perform EC software sync in romstage, before memory training is started. Because the ChromeOS EC will not currently perform USB-PD negotiation until it jumps to running its RW code, this allows the system to get access to more power earlier in the boot flow. This is guarded by CONFIG_VBOOT_EARLY_EC_SYNC. BUG=b:112198832 BRANCH=none TEST=EC software sync works in update and non-update case. No significant effect on boot time (~6 ms). Change-Id: I31f3407a2afcbf288461fab1397f965f025bc07c Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36211 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-18nb/intel/sandybridge: Set up console in bootblockArthur Heymans
Change-Id: Ia041b63201b2a4a2fe6ab11e3497c460f88061d1 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36784 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-11-18nb/intel/sandybridge: Move to C_ENVIRONMENT_BOOTBLOCKArthur Heymans
There is some overlap between romstage and bootblock. LPC setup and BAR initialization is now done twice. The rationale is that the romstage should not depend too much on the bootblock, since it can reside in a RO fmap region. Enabling the console will be done in a followup patch. Change-Id: I4d0ba29111a5df6f19033f5ce95adcc0d9adc1fd Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36783 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-11-15nb/intel/x4x: Move to C_ENVIRONMENT_BOOTBLOCKArthur Heymans
There is some overlap between things done in bootblock and romstage like setting BARs. Change-Id: Icd1de34c3b5c0f36f2a5249116d1829ee3956f38 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36759 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-15nb/intel/i945: Move to C_ENVIRONMENT_BOOTBLOCKArthur Heymans
Console init in bootblock will be done in a separate CL. Change-Id: Ia2405013f262d904aa82be323e928223dbb4296c Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36795 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-12arch/x86/car.ld: Rename suffix _start/_endArthur Heymans
This is more in line with how linker symbol for regions are defined. Change-Id: I0bd7ae59a27909ed0fd38e6f7193816cb57e76af Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36695 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-11-08arch/x86: Drop some __SMM__ guardsKyösti Mälkki
Change-Id: I64063bbae5b44f1f24566609a7f770c6d5f69fac Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36637 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-11-07Rangeley: Fix incorrect BCLKKyösti Mälkki
Not all Rangeley SKUs have a fixed 100MHz BCLK. As per BIOS Writer's Guide, BCLK is available in MSR_FSB_FREQ 0xCD[1:0]. Using fixed BCLK was causing wrong values of core frequencies in _PSS table for SKUs that do not have BCLK=100MHz. Change-Id: Id8e0244fab0283b74870950cb00a95aab2a7201f Signed-off-by: Hannah Williams <hannah.williams@dell.com> Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35348 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-05intel/i440bx: Switch to UDELAY_TSC and TSC_MONOTONIC_TIMERKyösti Mälkki
Note that due to UNKNOWN_TSC_RATE, each stage will have a slow run of calibrate_tsc_with_pit(). This is easy enough to fix with followup implementation of tsc_freq_mhz() for the cpu. Change-Id: I0f5e16993e19342dfc4801663e0025bb4cee022a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36525 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-04cpu/intel/car/p4-netburst: Remove delay loopsKyösti Mälkki
While commented as 10 ms + 250 us, those delay loops actually accounted for a total of 840 ms. And they seem unnecessary as followup code has potentially infinite retries when polling for status changes. Tested on aopen/dxplplusu, dual-socket P4 Xeon HT model_f2x. Change-Id: Ib7d1d66ed29c62d97073872f0b7809d719ac2324 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36595 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-11-04cpu/intel/smm/gen1: Deal with SMM save state compatibilityArthur Heymans
Change-Id: I92326e3e0481d750cb9c90f717ed748000e33ad3 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36587 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-11-03cpu/x86/tsc: Flip and rename TSC_CONSTANT_RATE to UNKNOWN_TSC_RATEKyösti Mälkki
The x86 timers are a bit of a mess. Cases where different stages use different counters and timestamps use different counters from udelays. The original intention was to only flip TSC_CONSTANT_RATE Kconfig to NOT_CONSTANT_TSC_RATE. The name would be incorrect though, those counters do run with a constant rate but we just lack tsc_freq_mhz() implementation for three platforms. Note that for boards with UNKNOWN_TSC_RATE=y, each stage will have a slow run of calibrate_tsc_with_pit(). This is easy enough to fix with followup implementation of tsc_freq_mhz() for the platforms. Implementations with LAPIC_MONOTONIC_TIMER typically will not have tsc_freq_mhz() implemented and default to UNKNOWN_TSC_RATE. However, as they don't use TSC for udelay() the slow calibrate_tsc_with_pit() is avoided. Because x86/tsc_delay.tsc was using two different guards and nb/via/vx900 claimed UDELAY_TSC, but pulled UDELAY_IO implementation, we also switch that romstage to use UDELAY_TSC. Change-Id: I1690cb80295d6b006b75ed69edea28899b674b68 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33928 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-11-02cpu/intel/core2: Cache XIP romstage with C_ENVIRONMENT_BOOTBLOCK.Arthur Heymans
Tested on Thinkpad X200: the romstage execution speeds are back to pre-C_ENVIRONMENT_BOOTBLOCK levels. Change-Id: Id0b50d2f56e7cc0e055cdc8b9aa28794327eca28 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35994 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-31cpu/x86: make set_msr_bit publicly availableMichael Niewöhner
Haswell and model_2065 implement a static set_msr_bit helper which should be publicly available instead. Move it to cpu/x86. Change-Id: I68b314c917f15fc6e5351de1c539d5a3ae646df8 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36338 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-28nb/intel/gm45: Add C_ENVIRONMENT_BOOTBLOCK supportArthur Heymans
The i82801ix_early_init is now called both in the bootblock and romstage. The rationale behind setting this up twice is to ensure bootblock-romstage compatibility in the future if for instance VBOOT is used. This moves the console init to the bootblock. The romstage now runs uncached. Adding a prog_run hooks to set up an MTRR to cache the romstage will be done in a followup patch. The default size of 64KiB is not modified for the bootblock as trying to fit both EHCI and SPI flash debugging needs a more space and 64KiB is the next power of 2 size that fits it. TESTED on Thinkpad X200. Change-Id: I8f59736cb54377973215f35e35d2cbcd1d82c374 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35992 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-10-28cpu/intel/car: Correctly cache the bootblock with C_ENVIRONMENT_BOOTBLOCKArthur Heymans
With CONFIG_C_ENVIRONMENT_BOOTBLOCK it makes more sense to rely on the size of the bootblock over CONFIG_XIP_ROM_SIZE. To make this work, only powers of 2 are allowed as bootblock size. Change-Id: Ic8104ca9c51e4d2eccdb277e4c2111d2da662f3e Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35990 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-10-28src: Remove unused '#include <cpu/cpu.h>'Elyes HAOUAS
Change-Id: Ibcb1cafe36c255b4c5bd0a4faeedb95e91048709 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36372 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-10-24cpu/intel/common: Enable GetSec leaves for Intel TXTPatrick Rudolph
Similar to VMX and SMX also enable all GetSec leaves for Intel TXT. Change-Id: I89620c2a98cfceaa785b1a798fafbf35cc99a0b2 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36092 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2019-10-13nb/intel/nehalem: Move to C_ENVIRONMENT_BOOTBLOCKArthur Heymans
A few notable changes: - Microcode init is done in assembly during the CAR init. - The DCACHE_BSP_STACK_SIZE is set to 0x2000, which is the same size against which the romstage stack guards protected. - The romstage mainboard_lpc_init() hook is removed in favor of the existing bootblock_mainboard_early_init(). Change-Id: Iccd7ceaa35db49e170bfb901bbff1c1a11223c63 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35951 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-10-06cpu/intel/model_2065x/bootblock: Remove dead codeArthur Heymans
This codepath is never takes as it checks if the CPU is at least ivybridge. Change-Id: Id064385f0c8bb0b094714129df6d8ba36c87a307 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35810 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-10-03cpu/intel/: Fix regression with smmrelocateKyösti Mälkki
Fix regression with commit d53fd70 intel/smm/gen1: Use smm_subregion(). The bitmask on SMRR register parameter was inverted for selected models. Change-Id: Ia572ca3bdd4da371985691b5d249f998382fbe48 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35780 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Bill XIE <persmule@hardenedlinux.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-10-01cpu/intel/common: Move intel_ht_sibling() to common folderPatrick Rudolph
Make intel_ht_sibling() available on all platforms. Will be used in MP init to only write "Core" MSRs from one thread on HyperThreading enabled platforms, to prevent race conditions and resulting #GP if MSRs are written twice or are already locked. Change-Id: I5d000b34ba4c6536dc866fbaf106b78e905e3e35 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35619 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-09-30console: Declare empty printk() for __ROMCC__Kyösti Mälkki
The typical do { } while (0) did not work, so provide empty stub function instead. Change-Id: Ieb0c33b082b4c4453d29d917f46561c0e672d09a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35588 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-09-26cpu/intel/: Clean up microcode update from __PRE_RAM__Kyösti Mälkki
Change-Id: Ib12985dd9a12495533a82be556405f975a0abe27 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35587 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-09-24intel/cpu: Switch older models to TSC_MONOTONIC_TIMERKyösti Mälkki
The implementation of udelay() with LAPIC timers existed first, as we did not have calculations implemented for TSC frequency. Change-Id: If510bcaadee67e3a5792b3fc7389353b672712f9 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34200 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-24cpu/intel: Use CPU_INTEL_COMMON_TIMEBASEKyösti Mälkki
Change-Id: I0e7159039751a88d86b6c343be5f085e6e15570a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31342 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-09-24intel/socket_mPGA604: Enable TSC_CONSTANT_RATEKyösti Mälkki
We can use intel/common implementation for tsc_freq_mhz(). Change-Id: I728732896ad61465fcf0f5b25a6bafd23bca235e Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34199 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-24cpu/intel/common: Fix invalid MSR accessKyösti Mälkki
Fix regression from commit ecea916 cpu/intel/common: Extend FSB detection to cover TSC MSR_EBC_FREQUENCY_ID (0x2c) was not defined for affected CPU models and rdmsr() caused reset loops. Implementations deviate from public documentation. Change to IA32_PERF_STATUS (0x198) already used in i945/udelay.c to detect FSB to TSC multiplier. Change-Id: I7a91da221920a7e7bfccb98d76115b5c89e3b52e Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35548 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-09-19cpu/intel/common: Extend FSB detection to cover TSCKyösti Mälkki
Use the same CPUID switch block to resolve the multiplier to derive TSC from FSB/BCLK frequency. Do not return 0 as base frequency. Change-Id: Ib7f1815b3fac7a610f7203720d526eac152a1648 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31340 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-19cpu/x86/lapic: Refactor timer_fsb()Kyösti Mälkki
Common apic_timer code in cpu/x86 should not depend on intel header files. Change-Id: Ib099921d4b8e561daea47219385762bb00fc4548 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34091 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-19cpu/intel/common: Add CPU_INTEL_COMMON_TIMEBASEKyösti Mälkki
To add a common tsc_freq_mhz() implementation, we need to guard againts soc-specific duplicate definitions. Change-Id: I37a34651d9e7d823ad5689d30739294358a97e31 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31341 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: David Guckian Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-15cpu/intel/microcode: Make microcode lib available in bootblockRizwan Qureshi
Make microcode lib available in bootblock. Now that microcode.c is compiled in bootlock no need to include it explicitly, hence remove its references. Change-Id: I419da6af70222902e3ca39fc2133d5dc8558e053 Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35278 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-13intel/haswell: Remove some __PRE_RAM__ useKyösti Mälkki
Change-Id: I167e9a171af4fe7997ebb76cdfa22a4578817a55 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35380 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-10AUTHORS: Move src/cpu/intel copyrights into AUTHORS fileMartin Roth
As discussed on the mailing list and voted upon, the coreboot project is going to move the majority of copyrights out of the headers and into an AUTHORS file. This will happen a bit at a time, as we'll be unifying license headers at the same time. Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: I39f52764dc377c25953ef5dba16982a0b4637cdb Reviewed-on: https://review.coreboot.org/c/coreboot/+/35181 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Guckian Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-09-02security/intel: Add TXT infrastructurePatrick Rudolph
* Add Kconfig to enable TXT * Add possibility to add BIOS and SINIT ACMs * Set default BIOS ACM alignment * Increase FIT space if TXT is enabled The following commits depend on the basic Kconfig infrastructure. Intel TXT isn't supported until all following commits are merged. Change-Id: I5f0f956d2b7ba43d4e7e0062803c6d8ba569a052 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34585 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2019-08-28intel/haswell: Use smm_subregion()Kyösti Mälkki
Change-Id: Idfb13ab03d4d4ae764bdda62a29848db9d8dcd81 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34737 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-28intel/haswell,broadwell: Rename EMRR to PRMRRKyösti Mälkki
The MSRs were already named as PRMRR in broadwell, just mismatching with the rest of the code. All later devices use the names PRMRR and UNCORE_PRMRR for these MSRs. Reflect the name change in structures and local variables. Change-Id: Id825ba2c083d0def641dd9bf02d3b671d85b1e35 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34825 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-28intel/smm/gen1: Use smm_subregion()Kyösti Mälkki
Change-Id: I371ed41f485b3143e47f091681198d6674928897 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34740 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-26intel/car: Use common TS_START_ROMSTAGEKyösti Mälkki
This timestamp also got unintentionally removed from some boards as they were transformed to use common romstage entry. Change-Id: I12be278a674f9a2ea073b170a223c41c7fc01a94 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34970 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-26lib/bootblock: Add simplified entry with basetimeKyösti Mälkki
This allows for minor optimization as num_timestamps becomes a constant zero for a function with local scope. The loop with calls to timestamp_add() gets removed from bootblock. Change-Id: Id230075c0e76fe377b6ea8c8ddf8318e07d29b91 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34972 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-08-26soc/intel: Use common romstage codeKyösti Mälkki
This provides stack guards with checking and common entry into postcar. The code in cpu/intel/car/romstage.c is candidate for becoming architectural so function prototype is moved to <arch/romstage.h>. Change-Id: I4c5a9789e7cf3f7f49a4a33e21dac894320a9639 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34893 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-22arch/x86: Add <arch/romstage.h>Kyösti Mälkki
Start with moving all postcar_frame related function declarations here from <arch/cpu.h>. Change-Id: I9aeef07f9009e44cc08927c85fe1862edf5c70dc Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34911 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-21cpu/intel/car: Make stack guards more useful on C_ENV_BOOTBLOCKArthur Heymans
With C_ENVIRONMENT_BOOTBLOCK, CONFIG_DCACHE_BSP_STACK_SIZE needs to be set to define a stack region that can be shared over all stages using CAR. It makes sense to use that Kconfig option's value instead of a hardcoded value. This will result in less false positives when the stack size is big, for instance with FSP using the coreboot stack. In many configurations with C_ENVIRONMENT_BOOTBLOCK the stack_base is at the base of CAR. If the stack grows too large it operates out of CAR, typically resulting in a hang. Therefore the stack guards are extended to cover 256 bytes at the base to at least provide a warning when the romstage is dangerously close of running out of stack. Change-Id: I2ce1dda4d1f254e6c36de4d3fea26e12c34195ff Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34976 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-08-20devicetree: Remove duplicate chip_ops declarationsKyösti Mälkki
These are only referenced inside auto-generated static.c files, and util/sconfig also generates the declarations automatically from source file pathnames. Change-Id: Id324790755095c36fbeb73a4d8f9d01cdf6409cb Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34979 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-18cpu/intel: Enter romstage without BISTKyösti Mälkki
When entry to romstage is via cpu/intel/car/romstage.c BIST has not been passed down the path for sometime. Change-Id: I345975c53014902269cee21fc393331d33a84dce Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34908 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-08-15intel/smm: Define struct ied_header just onceKyösti Mälkki
Change-Id: I6fc083aa30d05c11c1b6db7b3facacf5ae857c92 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34855 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-08-15soc/intel: Rename some SMM support functionsKyösti Mälkki
Rename southbridge_smm_X to smm_southbridge_X. Rename most southcluster_smm_X to smm_southbridge_X. Change-Id: I4f6f9207ba32cf51d75b9ca9230e38310a33a311 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34856 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-15intel/smm/gen1: Rename header fileKyösti Mälkki
Change-Id: I258fccc5e1db0bedb641c8af8cb9727954d4d7c1 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34869 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-08-15cpu/x86/smm: Promote smm_memory_map()Kyösti Mälkki
Change-Id: I909e9b5fead317928d3513a677cfab25e3c42f64 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34792 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-15arch/x86: Add postcar_frame_common_mtrrs()Kyösti Mälkki
As most platforms will share the subset of enabling both low RAM WB and high ROM WP MTRRs, provide them with a single function. Add possibility for the platform to skip these if required. Change-Id: Id1f8b7682035e654231f6133a42909a36e3e15a1 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34809 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-15cpu/intel: Refactor platform_enter_postcar()Kyösti Mälkki
There are benefits in placing the postcar_frame structure in .bss and returning control to romstage_main(). Change-Id: I0418a2abc74f749203c587b2763c5f8a5960e4f9 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34808 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-08-15cpu/intel: Replace bsp_init_and_start_aps()Kyösti Mälkki
Change-Id: I7176efdd1000789a093a1b4e243b4b150e6bb06f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34864 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-15intel/smm/gen1: Split alternative SMRR register functionKyösti Mälkki
The non-alternative one will have inlined version available with the new header. Change-Id: I208ac84fdf5d8041a1901cc2331769cd3a8d6bea Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34839 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-08-13cpu/x86: Separate save_state struct headersKyösti Mälkki
Any platform should need just one of these. Change-Id: Ia0ff8eff152cbd3d82e8b372ec662d3737078d35 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34820 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-11intel/haswell: Move platform_enter_postcar()Kyösti Mälkki
Do this for consistency with remaining cpu/intel sources. Also wipe out some spurious includes. Change-Id: I1adde58966eae9205703b87e7aa17c50e5791a85 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34807 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-08-08lib/stage_cache: Refactor Kconfig optionsKyösti Mälkki
Add explicit CBMEM_STAGE_CACHE option. Rename CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM to TSEG_STAGE_CACHE. Platforms with SMM_TSEG=y always need to implement stage_cache_external_region(). It is allowed to return with a region of size 0 to effectively disable the cache. There are no provisions in Kconfig to degrade from TSEG_STAGE_CACHE to CBMEM_STAGE_CACHE. As a security measure CBMEM_STAGE_CACHE default is changed to disabled. AGESA platforms without TSEG will experience slower S3 resume speed unless they explicitly select the option. Change-Id: Ibbdc701ea85b5a3208ca4e98c428b05b6d4e5340 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34664 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-08-07intel/nehalem,sandybridge: Move stage_cache support functionKyösti Mälkki
Let garbage-collection take care of stage_cache_external_region() if it is no needed and move implementation to a suitable file already building for needed stages. Remove aliasing CONFIG_RESERVED_SMM_SIZE as RESERVED_SMM_SIZE and (unused) aliasing of CONFIG_IED_REGION_SIZE as IED_SIZE. Change-Id: Idf00ba3180d8c3bc974dd3c5ca5f98a6c08bf34d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34672 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-03intel/haswell: Move stage_cache support functionKyösti Mälkki
Let garbage-collection take care of stage_cache_external_region() if it is no needed and move implementation to a suitable file already building for needed stages. Remove aliasing CONFIG_RESERVED_SMM_SIZE as RESERVED_SMM_SIZE. Change-Id: Ie6fcc40fba14575e8ee058f45a1a359a05f00aca Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34668 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-07-21src/cpu/intel: Add sanity check for cpu turbo mode capabilityJohn Zhao
It is proper to check cpu turbo mode capability after it is selected to be enabled. If processor exhibits the presence of hardware support for turbo, turbo global state will be updated with TURBO_ENABLE. Otherwise, TURBO_UNAVAILABLE is applied to turbo global state. TEST=Validated turbo state on GLK and WHL devices. Change-Id: Ib1bc37fb339b4a0bb6a7cdc6cd4391575b22b55a Signed-off-by: John Zhao <john.zhao@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34145 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-13intel/haswell: Replace monotonic timerKyösti Mälkki
Remove implementation of 24 MHz clock, available only on Haswell ULT SKUs. Use TSC_MONOTONIC_TIMER instead for all boards. Change-Id: Ic4aeb084d1b0913368f5eaa46e1bd68411435517 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34114 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-07-13cpu/x86: Move smm_lock() prototypeKyösti Mälkki
The function implementations are in local platform scopes. Change-Id: I7a3025398b15fe6d2c5a13cdb65f3e62a49c0bc6 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34151 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-10cpu/x86: Remove obsolete smm_init_completion()Kyösti Mälkki
This is not used together with PARALLEL_MP and SMM_TSEG. Platforms with SMM_ASEG continue to have their local implementation doing the same thing. Change-Id: I13a2f164804330c93240bff7f048e0a162b3ae25 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34154 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-09arch/x86: Flip HAVE_MONOTONIC_TIMER defaultKyösti Mälkki
Change-Id: Id56139a3d0840684b13179821a77bc8ae28e05ae Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34113 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-07-09cpu/x86: Flip SMM_TSEG defaultKyösti Mälkki
This is only a qualifier between TSEG and ASEG. Change-Id: I8051df92d9014e3574f6e7d5b6f1d6677fe77c82 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34135 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-07-09cpu/x86: Declare SMM_ASEGKyösti Mälkki
This is really an inverse of SMM_TSEG to flag platforms that should potentially move away from ASEG implementation. Change-Id: I3b9007c55c75a59a9e6acc0a0e701300f7d21f87 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34134 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-07-09cpu/intel: Drop SMM_TSEG conditionalKyösti Mälkki
SMM_TSEG is a qualifier between TSEG and ASEG memory region. ASEG is deprecated and not supported for these CPUs in coreboot codebase. Change-Id: I0602e04957a390473a2449e1c5ff951f9fdff73b Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34133 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-07-09arch/x86: Avoid HAVE_SMI_HANDLER conditional with smm-classKyösti Mälkki
Build of the entire smm-class is skipped if we have HAVE_SMI_HANDLER=n. Change-Id: I10b4300ddd18b1673c404b45fd9642488ab3186c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34125 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Lance Zhao <lance.zhao@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-08intel/socket_mPGA604: Enable TSC_MONOTONIC_TIMERKyösti Mälkki
Change-Id: I3ca2b7752905209e8db6b1dc74b930445676792e Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34111 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-07-08intel/nehalem: Move TSC_MONOTONIC_TIMERKyösti Mälkki
Change-Id: Ib7f2f7773d0eef5ac4e277b44ee9114aa6729527 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34110 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-07-04arch/x86: Adjust size of postcar stackKyösti Mälkki
With VBOOT=y && VBOOT_MEASURED_BOOT=y message digest will be allocated from the stack and 1 KiB reserve used with the recent platforms was no longer sufficient. The comment of LZMA scratchpad consuming stack was obsolete for postcar, so these can be reduced to same 4 KiB. Change-Id: Iba1fb5bfad6946f316feac2d8c998a782142a56a Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33775 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2019-07-01Use 3rdparty/intel-microcodeArthur Heymans
Instead of maintaining this in 3rdparty/blobs use the 3rdparty/intel-microcode which is maintained by Intel. This allows for some finegrained control where family+model span multiple targets. Microcode updates present in 3rdparty/blobs/soc/intel/{baytrail,broadwell} are left out since those contain updates not present in the Intel repo. Those are presumably early CPU samples that did not end up in products. The following MCU are get a new revision: old: sig 0x000306c3, pf_mask 0x32, 2018-04-02, rev 0x0025, size 23552 sig 0x00040651, pf_mask 0x72, 2018-04-02, rev 0x0024, size 22528 sig 0x000206a7, pf_mask 0x12, 2018-04-10, rev 0x002e, size 12288 sig 0x000306a9, pf_mask 0x12, 2018-04-10, rev 0x0020, size 13312 sig 0x000706a1, pf_mask 0x01, 2018-05-22, rev 0x0028, size 73728 sig 0x000506c9, pf_mask 0x03, 2018-05-11, rev 0x0032, size 16384 sig 0x000506ca, pf_mask 0x03, 2018-05-11, rev 0x000c, size 14336 sig 0x000806e9, pf_mask 0xc0, 2018-03-24, rev 0x008e, size 98304 sig 0x000906e9, pf_mask 0x2a, 2018-03-24, rev 0x008e, size 98304 sig 0x000906ea, pf_mask 0x22, 2018-05-02, rev 0x0096, size 97280 sig 0x000906eb, pf_mask 0x02, 2018-03-24, rev 0x008e, size 98304 sig 0x00050665, pf_mask 0x10, 2018-04-20, rev 0xe00000a, size 18432 sig 0x000506e3, pf_mask 0x36, 2018-04-17, rev 0x00c6, size 99328 sig 0x000906e9, pf_mask 0x2a, 2018-03-24, rev 0x008e, size 98304 sig 0x000406e3, pf_mask 0xc0, 2018-04-17, rev 0x00c6, size 99328 new: sig 0x000306c3, pf_mask 0x32, 2019-02-26, rev 0x0027, size 23552 sig 0x00040651, pf_mask 0x72, 2019-02-26, rev 0x0025, size 21504 sig 0x000206a7, pf_mask 0x12, 2019-02-17, rev 0x002f, size 12288 sig 0x000306a9, pf_mask 0x12, 2019-02-13, rev 0x0021, size 14336 sig 0x000706a1, pf_mask 0x01, 2019-01-02, rev 0x002e, size 73728 sig 0x000506c9, pf_mask 0x03, 2019-01-15, rev 0x0038, size 17408 sig 0x000506ca, pf_mask 0x03, 2019-03-01, rev 0x0016, size 15360 sig 0x000806e9, pf_mask 0xc0, 2019-04-01, rev 0x00b4, size 99328 sig 0x000906e9, pf_mask 0x2a, 2019-04-01, rev 0x00b4, size 99328 sig 0x000906ea, pf_mask 0x22, 2019-04-01, rev 0x00b4, size 98304 sig 0x000906eb, pf_mask 0x02, 2019-04-01, rev 0x00b4, size 99328 sig 0x00050665, pf_mask 0x10, 2019-03-23, rev 0xe00000d, size 19456 sig 0x000506e3, pf_mask 0x36, 2019-04-01, rev 0x00cc, size 100352 sig 0x000906e9, pf_mask 0x2a, 2019-04-01, rev 0x00b4, size 99328 sig 0x000406e3, pf_mask 0xc0, 2019-04-01, rev 0x00cc, size 100352 Change-Id: Idcfb3c3c774e0b47637e1b5308c28002aa044f1c Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33554 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-07-01intel/fsp_rangeley: Use fixed FSB/BCLK value 100 MHzKyösti Mälkki
Prior to commit d731a24 src/cpu/intel: Set get_ia32_fsb function common value of 200 was silently used as a default for fsp_rangeley (model_406dx) in cpu/x86/lapic/apic_timer:set_timer_fsb(). After the commit, get_ia32_fsb() returns -2, eventually resulting with divide-by-zero in timer_monotonic_get(), as get_timer_fsb() returns 0. Add Rangeley CPUID model 0x4d to get_ia32_fsb() as a fix, using BCLK = 100 MHz based on the comments in northbridge/intel/fsp_rangeley/udelay.c Change-Id: I306f85dba9b1e91539fc0ecc9b2ae9d54f82be6c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33822 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2019-06-22src/cpu: Use 'include <stdlib.h>' when appropriateElyes HAOUAS
Change-Id: I44346594bc106eed73a1268b82f026b69e5f4512 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32821 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-06-21cpu: Add missing #include <commonlib/helpers.h>Elyes HAOUAS
ALIGN and ALIGN_UP needs 'helpers.h' Change-Id: Ib3a9e0d6caff69f4b0adb54364b47cc6ac52a610 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33658 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-06-21cpu/intel/haswell: Link monotonic_timer.c in early stagesArthur Heymans
This is needed for SPI flash console in bootblock/romstage/postcar. Change-Id: I18253cc028e87cd31879d722a6d788917e9c97b3 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33191 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-06-21cpu/intel/haswell: Link tsc_freq.c in the bootblockArthur Heymans
This provides tsc_freq_mhz implementation. Change-Id: Ic6a84336f89a37aa412a9cc8c375fbd41dc09cf2 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33176 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2019-06-21cpu/intel/{haswell,model_206{5,a}x}: Use MSR_CORE_THREAD_COUNT for msr at 0x35Elyes HAOUAS
Regarding 64 and IA-32 Architectures Software Developer’s Manual, the register name of the msr at 0x35 is MSR_CORE_THREAD_COUNT. Change-Id: I5134619dc3a42187ddd5f46c85873c4278229e27 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33015 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-05-27sb/intel/common/smi.c: Remove unused functionsArthur Heymans
Since all targets using sb/intel/common and cpu/intel/smm/gen1 are now using PARALLEL_MP, some code is not used anymore. Change-Id: Ibdc2bb0f1412366b945813efbc1b6451d27f376f Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/30019 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-05-27cpu/intel/model_2065x: Put stage cache in TSEGArthur Heymans
TSEG is not accessible in ring 0 after it is locked in ramstage, in contrast with cbmem which remains accessible. Assuming SMM does not touch the cache this is a good region to cache stages. Change-Id: I89cbfb6ece62f554ac676fe686115e841d2c1e40 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/26298 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-05-27cpu/intel/model_2065x: Use parallel MP initArthur Heymans
TESTED on Thinkpad X201 with a i7 CPU M620 CPU (hyperthread dual core). Boots ~28ms faster. Change-Id: I56b352f9d76ee58f5c82cd431a4e0fa206f848a0 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/26297 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-16 23:55:09 +0000