| Age | Commit message (Expand) | Author |
|---|
| 2019-01-15 | cpu/intel/socket_FCBGA559: Use the non-evict cache as ram setup | Arthur Heymans |
| 2019-01-14 | cpu/intel/gen1/smmrelocate: Check for sanity on SMRR | Arthur Heymans |
| 2019-01-14 | cpu/intel/car/non-evict: Update microcode in CAR setup | Arthur Heymans |
| 2019-01-13 | aopen/dxplplusu: Switch to C_ENVIRONMENT_BOOTBLOCK | Kyösti Mälkki |
| 2019-01-13 | arch/x86: Drop Kconfig AP_SIPI_VECTOR | Kyösti Mälkki |
| 2019-01-13 | cpu/intel/car/p4: Update microcode in CAR setup | Arthur Heymans |
| 2019-01-11 | cpu/intel/microcode: Support update before CAR entry | Arthur Heymans |
| 2019-01-10 | 3rdparty/blobs: Update for current Intel microcode | Nico Huber |
| 2019-01-10 | Untangle CBFS microcode updates | Nico Huber |
| 2019-01-09 | cpu/intel: Use the common code to initialize the romstage timestamps | Arthur Heymans |
| 2019-01-09 | cpu/intel/common: Fix generated exception if not supported VMX | Elyes HAOUAS |
| 2019-01-09 | cpu/intel/microcode_asm.S: Fix reading cpuid(1) and checking PF | Arthur Heymans |
| 2019-01-08 | arch/x86: Link walkcbfs.S instead of including it | Arthur Heymans |
| 2019-01-08 | cpu/intel/car/bootblock.c: Report BIST failures | Arthur Heymans |
| 2019-01-08 | cpu/intel/car: Enable use of C_ENVIRONMENT_BOOTBLOCK | Arthur Heymans |
| 2019-01-08 | cpu/intel/car: Prepare for C_ENVIRONMENT_BOOTBLOCK | Kyösti Mälkki |
| 2019-01-06 | device: Use pcidev_on_root() | Kyösti Mälkki |
| 2019-01-05 | cpu/intel/common: improve debug output | Matt DeVillier |
| 2019-01-03 | nb/intel/haswell: Add support for PEG | Tristan Corrick |
| 2018-12-31 | src/cpu/microcode: Add code to update microcode in assembly | Arthur Heymans |
| 2018-12-30 | arch/x86: Add CAR stack location symbols | Kyösti Mälkki |
| 2018-12-30 | cpu/intel/car: Drop remains of setup_stack_and_mtrrs() | Kyösti Mälkki |
| 2018-12-28 | src/cpu/intel/model_f4x: Update cpu_table | Elyes HAOUAS |
| 2018-12-28 | arch/x86: SSE2 implies SSE support | Kyösti Mälkki |
| 2018-12-28 | soc/intel: Drop romstage_after_car() | Kyösti Mälkki |
| 2018-12-24 | car/non-evict/exit_car.S: Use tabs instead of white spaces | Elyes HAOUAS |
| 2018-12-21 | car/non-evict/cache_as_ram.S: Use tabs instead of spaces | Arthur Heymans |
| 2018-12-20 | cpu/intel/common: decouple IA32_FEATURE_CONTROL lock from set_vmx() | Matt DeVillier |
| 2018-12-18 | cpu: Remove unneeded include <pc80/mc146818rtc.h> | Elyes HAOUAS |
| 2018-12-13 | cpuid: Add helper function for cpuid(1) functions | Subrata Banik |
| 2018-12-03 | cpu/intel/fsp_model_406dx: Drop dead microcode reference | Nico Huber |
| 2018-12-03 | nb/intel/i945: Use common SMM_TSEG code | Arthur Heymans |
| 2018-11-30 | cpu/intel/common: Use a common acpi/cpu.asl file | Arthur Heymans |
| 2018-11-30 | cpu/intel/fsp_model_406dx: Rework acpi/cpu.asl | Arthur Heymans |
| 2018-11-30 | cpu/intel/model_206{5,a}x: Rework acpi/cpu.asl | Arthur Heymans |
| 2018-11-30 | cpu/intel/haswell: Rework acpi/cpu.asl | Arthur Heymans |
| 2018-11-29 | arch/x86/acpigen.c: Add a method to notify all CPU cores | Arthur Heymans |
| 2018-11-21 | src/cpu/intel/Kconfig: Remove dead source | Elyes HAOUAS |
| 2018-11-19 | northbridge/intel/fsp_*: Remove legacy SoCs | zaolin |
| 2018-11-19 | cpu/intel/socket_mFCPGA478/Kconfig: Add MODEL_6{9,D}X | Elyes HAOUAS |
| 2018-11-16 | src: Remove unneeded include <cbfs.h> | Elyes HAOUAS |
| 2018-11-15 | src/cpu: Remove dead sourced lines | Elyes HAOUAS |
| 2018-11-12 | src: Remove unneeded include "{arch,cpu}/cpu.h" | Elyes HAOUAS |
| 2018-11-01 | cpu/intel/haswell: Only change the slow ramp rate for ULT CPUs | Tristan Corrick |
| 2018-11-01 | cpu/intel/haswell: Allow use of TSC for the monotonic timer | Tristan Corrick |
| 2018-11-01 | cpu/intel/haswell: Add the CPUID for Haswell C0 CPUs | Tristan Corrick |
| 2018-10-30 | src: Add missing include <stdint.h> | Elyes HAOUAS |
| 2018-10-24 | cpu/intel/smm: Don't make assumptions on TSEG_SIZE | Arthur Heymans |
| 2018-10-22 | intel: Use CF9 reset (part 1) | Patrick Rudolph |
| 2018-10-11 | src: Move common IA-32 MSRs to <cpu/x86/msr.h> | Elyes HAOUAS |
| 2018-10-11 | src: Replace MSR addresses with macros | Elyes HAOUAS |
| 2018-10-08 | Move compiler.h to commonlib | Nico Huber |
| 2018-10-05 | src: Fix MSR_PKG_CST_CONFIG_CONTROL register name | Elyes HAOUAS |
| 2018-10-04 | cpu/intel/car: Fix typo | Elyes HAOUAS |
| 2018-09-28 | src/*: normalize Google copyright headers | Patrick Georgi |
| 2018-09-26 | cpu/intel/model_206ax: detect number of MCE banks | Dan Elkouby |
| 2018-09-18 | cpu/*/car: fix ancient URL explaining XIP range run-time calculation | Stefan Tauner |
| 2018-08-20 | cpu/intel/common: add function to init cppc_config | Matt Delco |
| 2018-08-17 | intel/socket_mPGA604: Keep only model f2x | Kyösti Mälkki |
| 2018-08-13 | src: Get rid of non-local header treated as local | Elyes HAOUAS |
| 2018-08-13 | cpu/intel/car: Align the stack to 16 bytes before romstage_main | Arthur Heymans |
| 2018-08-09 | src/cpu: Fix typo | Elyes HAOUAS |
| 2018-08-09 | cpu/intel/smm: Make sure SMRR base is aligned to SMRR size | Arthur Heymans |
| 2018-07-30 | nb/intel/gm45: Use common code for SMM in TSEG | Arthur Heymans |
| 2018-07-30 | cpu/intel/smm/gen1: Use correct MSR for model_6fx and model_1067x | Arthur Heymans |
| 2018-07-30 | cpu/intel/microcode: Add helper functions to get microcode info | Rizwan Qureshi |
| 2018-07-28 | nb/intel/sandybridge: Move CPU report to cpu folder | Patrick Rudolph |
| 2018-07-28 | intel/sandybridge: Don't hardcode platform type | Patrick Rudolph |
| 2018-07-25 | drivers/tpm: Add TPM ramstage driver for devices without vboot. | Philipp Deppenwiese |
| 2018-07-24 | cpu/x86/mtrr.h: Rename MSR SMRR_PHYS_x to IA32_SMRR_PHYSx | Arthur Heymans |
| 2018-07-09 | src/{arch,commonlib,cpu}: Use "foo *bar" instead of "foo* bar" | Elyes HAOUAS |
| 2018-06-27 | cpu/intel/p4-netburst: skip caching rom on model_fxx | Arthur Heymans |
| 2018-06-27 | x86/car: Replace reference of copy_and_run location | Kyösti Mälkki |
| 2018-06-21 | Revert "sb/intel/{bd82x6,ibexpeak}: Move RCBA macros to a common location" | Arthur Heymans |
| 2018-06-17 | nb/intel/i440bx: Switch to POSTCAR_STAGE | Kyösti Mälkki |
| 2018-06-17 | cpu/intel/car/p3: Use variable MTRR count | Kyösti Mälkki |
| 2018-06-17 | cpu/intel/slot_1: Switch to different CAR setup | Kyösti Mälkki |
| 2018-06-17 | cpu/intel/car: Remove obsolete files | Kyösti Mälkki |
| 2018-06-14 | cpu/intel/haswell: Use the common intel romstage_main function | Arthur Heymans |
| 2018-06-06 | arch/x86: Make RELOCATABLE_RAMSTAGE the default | Kyösti Mälkki |
| 2018-06-06 | cpu/intel/model_{6xx,f2x,f3x,f4x}: Remove unneeded include | Elyes HAOUAS |
| 2018-06-05 | cpu/intel/haswell: Switch to POSTCAR_STAGE | Arthur Heymans |
| 2018-06-05 | cpu/intel/model_2065x: Switch to POSTCAR_STAGE | Arthur Heymans |
| 2018-06-05 | cpu/intel/model_206ax: Switch to POSTCAR_STAGE | Arthur Heymans |
| 2018-06-05 | cpu/intel/car/non-evict: Improve a few things | Arthur Heymans |
| 2018-06-05 | cpu/intel/car/non-evict: Prepare for some POSTCAR_STAGE support | Arthur Heymans |
| 2018-06-05 | nb/intel/gm45: Switch to POSTCAR_STAGE | Arthur Heymans |
| 2018-06-05 | nb/intel/x4x: Switch to POSTCAR_STAGE | Arthur Heymans |
| 2018-06-05 | nb/intel/pineview: Switch to POSTCAR_STAGE | Arthur Heymans |
| 2018-06-05 | nb/intel/i945: Switch to POSTCAR_STAGE | Arthur Heymans |
| 2018-06-05 | cpu/intel/car/core2: Improve a few things | Arthur Heymans |
| 2018-06-05 | cpu/intel/car/core2: Prepare for POSTCAR_STAGE support | Arthur Heymans |
| 2018-06-04 | security/tpm: Unify the coreboot TPM software stack | Philipp Deppenwiese |
| 2018-06-02 | intel/socket_mPGA604 intel/e7505: Switch to POSTCAR_STAGE | Kyösti Mälkki |
| 2018-06-02 | cpu/intel/car: Prepare for some POSTCAR_STAGE support | Kyösti Mälkki |
| 2018-06-02 | aopen/dxplplusu intel/e7505: Move to EARLY_CBMEM_INIT | Kyösti Mälkki |
| 2018-06-01 | src/cpu: Remove unneeded includes | Elyes HAOUAS |
| 2018-05-31 | {cpu,drivers,nb,soc}/intel: Use CACHE_ROM_BASE where appropriate | Nico Huber |
| 2018-05-24 | Remove leftover Intel CPU support | Kyösti Mälkki |
| 2018-05-01 | Fix freeze during chipset lockdown on Nehalem | Matthias Gazzari |
