| Age | Commit message (Expand) | Author |
|---|---|---|
| 2018-06-05 | nb/intel/gm45: Switch to POSTCAR_STAGE | Arthur Heymans |
| 2018-06-05 | cpu/intel/car/core2: Prepare for POSTCAR_STAGE support | Arthur Heymans |
| 2016-12-18 | intel cache-as-ram: Move DCACHE_RAM_BASE | Kyösti Mälkki |
| 2016-11-08 | cpu/intel/socket_mPGA478MN: Add socket P | Arthur Heymans |
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index : coreboot.git | |
| my copy of coreboot | User & |
| summaryrefslogtreecommitdiff |