| Age | Commit message (Expand) | Author |
|---|---|---|
| 2021-01-28 | cpu/intel/socket_LGA775: Align CAR DCACHE_RAM_BASE to SIZE | Arthur Heymans |
| 2021-01-21 | cpu/intel/socket_LGA775: Increase DCACHE_RAM_SIZE | Elyes HAOUAS |
| 2019-11-25 | Drop superfluous C_ENVIRONMENT_BOOTBLOCK checks | Arthur Heymans |
| 2019-11-15 | nb/intel/x4x: Move to C_ENVIRONMENT_BOOTBLOCK | Arthur Heymans |
| 2018-06-05 | nb/intel/x4x: Switch to POSTCAR_STAGE | Arthur Heymans |
| 2018-06-02 | cpu/intel/car: Prepare for some POSTCAR_STAGE support | Kyösti Mälkki |
| 2016-12-10 | cpu/intel/lga775: Do not select model_6ex CPU | Arthur Heymans |
| 2016-06-21 | intel/model_6ex: Prepare for dynamic CONFIG_RAMTOP | Kyösti Mälkki |
| 2016-06-21 | intel/car/cache_as_ram_ht.inc: Prepare for dynamic CONFIG_RAMTOP | Kyösti Mälkki |
| 2016-06-18 | intel/cache_as_ram_ht.inc: Fix include | Kyösti Mälkki |
| 2015-05-04 | cpu: get rid of socket source code | Stefan Reinauer |
| 2013-03-07 | Fix socket LGA775 | Kyösti Mälkki |
| 2012-10-30 | Add support for socket LGA775 | Stefan Tauner |
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index : coreboot.git | |
| my copy of coreboot | User & |
| summaryrefslogtreecommitdiff |