| Age | Commit message (Expand) | Author |
|---|---|---|
| 2018-06-05 | nb/intel/gm45: Switch to POSTCAR_STAGE | Arthur Heymans |
| 2018-06-05 | cpu/intel/car/core2: Prepare for POSTCAR_STAGE support | Arthur Heymans |
| 2016-12-18 | intel cache-as-ram: Move DCACHE_RAM_BASE | Kyösti Mälkki |
| 2016-06-21 | intel/model_6ex: Prepare for dynamic CONFIG_RAMTOP | Kyösti Mälkki |
| 2015-09-04 | x86: remove cpu_incs as romstage Make variable | Aaron Durbin |
| 2015-05-04 | cpu: get rid of socket source code | Stefan Reinauer |
| 2014-07-05 | Drop redundant select CACHE_AS_RAM | Kyösti Mälkki |
| 2012-11-06 | intel/socket_BGA956: enable speedstep, CAR, MMX, SSE | Patrick Georgi |
| 2012-10-07 | Remove chip.h files without config structure | Kyösti Mälkki |
| 2012-08-22 | Auto-declare chip_operations | Kyösti Mälkki |
| 2012-02-10 | Intel cpus: apply un-written naming rules | Kyösti Mälkki |
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index : coreboot.git | |
| my copy of coreboot | User & |
| summaryrefslogtreecommitdiff |