coreboot.git - my copy of coreboot

Age	Commit message (Expand)	Author
2023-10-20	x86: Add pre-memory stages CBFS cache scratchpad support	Jeremy Compostella
2023-10-05	cpu/intel/socket_BGA956: Double DCACHE_RAM_SIZE to 64 kB	Arthur Heymans
2023-08-06	cpu: Add SPDX license headers to Makefiles	Martin Roth
2023-08-04	cpu: Get rid of CPU_SPECIFIC_OPTIONS	Elyes Haouas
2023-05-25	cpu/Kconfig: Remove MMX config option	Arthur Heymans
2022-11-21	cpu/intel/socket_*: Clean up Kconfig files	Elyes Haouas
2021-10-26	cpu/x86: Introduce and use `CPU_X86_LAPIC`	Felix Held
2021-10-26	cpu/intel/*/Kconfig: move selection of CPU_X86_CACHE_HELPER	Felix Held
2021-10-26	cpu/x86: Introduce `CPU_X86_CACHE_HELPER`	Felix Held
2021-10-25	cpu,soc/x86: always include cpu/x86/mtrr on x86 CPUs/SoCs	Felix Held
2021-09-08	cpu/x86/tsc: Deduplicate Makefile logic	Angel Pons
2021-06-07	cpu/intel/hyperthreading: Build only for selected models	Kyösti Mälkki
2021-05-18	cpu/x86: Only include smm code if CONFIG_HAVE_SMI_HANDLER=y	Arthur Heymans
2020-06-15	gm45 boards: Factor out MAX_CPUS	Angel Pons
2019-10-28	nb/intel/gm45: Add C_ENVIRONMENT_BOOTBLOCK support	Arthur Heymans
2018-06-05	nb/intel/gm45: Switch to POSTCAR_STAGE	Arthur Heymans
2018-06-05	cpu/intel/car/core2: Prepare for POSTCAR_STAGE support	Arthur Heymans
2016-12-18	intel cache-as-ram: Move DCACHE_RAM_BASE	Kyösti Mälkki
2016-06-21	intel/model_6ex: Prepare for dynamic CONFIG_RAMTOP	Kyösti Mälkki
2015-09-04	x86: remove cpu_incs as romstage Make variable	Aaron Durbin
2015-05-04	cpu: get rid of socket source code	Stefan Reinauer
2014-07-05	Drop redundant select CACHE_AS_RAM	Kyösti Mälkki
2012-11-06	intel/socket_BGA956: enable speedstep, CAR, MMX, SSE	Patrick Georgi
2012-10-07	Remove chip.h files without config structure	Kyösti Mälkki
2012-08-22	Auto-declare chip_operations	Kyösti Mälkki
2012-02-10	Intel cpus: apply un-written naming rules	Kyösti Mälkki