| Age | Commit message (Expand) | Author |
|---|---|---|
| 2019-10-28 | nb/intel/gm45: Add C_ENVIRONMENT_BOOTBLOCK support | Arthur Heymans |
| 2018-06-05 | nb/intel/gm45: Switch to POSTCAR_STAGE | Arthur Heymans |
| 2018-06-05 | cpu/intel/car/core2: Prepare for POSTCAR_STAGE support | Arthur Heymans |
| 2016-06-21 | intel/model_6ex: Prepare for dynamic CONFIG_RAMTOP | Kyösti Mälkki |
| 2015-09-04 | x86: remove cpu_incs as romstage Make variable | Aaron Durbin |
| 2015-05-04 | cpu: get rid of socket source code | Stefan Reinauer |
| 2012-11-06 | intel/socket_BGA956: enable speedstep, CAR, MMX, SSE | Patrick Georgi |
| 2012-02-10 | Intel cpus: apply un-written naming rules | Kyösti Mälkki |
 |
index : coreboot.git | |
| my copy of coreboot | gitea |
| aboutsummaryrefslogtreecommitdiff |