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2016-12-18intel cache-as-ram: Move DCACHE_RAM_BASEKyösti Mälkki
Having same memory region set as both WRPROT and WRBACK using MTRRs is undefined behaviour. This could happen if we allow DCACHE_RAM_BASE to be located within CBFS in SPI flash memory and XIP romstage is at the same location. As SPI master by default decodes all of top 16MiB below 4GiB, initial cache-as-ram line fills may have actually read from SPI flash even in the case DCACHE_RAM_BASE was below the nominal 4GiB - ROM_SIZE. There are no reasons to have this as board-specific setting. Change-Id: I2cce80731ede2e7f78197d9b0c77c7e9957a81b5 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17806 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-22intel model_106cx: Include CAR from socket directoryKyösti Mälkki
Since the socket layer is implemented with this CPU model, there could potentially be multiple CPU models included. There can be only one cache_as_ram include, so select it directly within the socket directory. Change-Id: Ia52bb152276eddfd1fb33ddb7f5d153ab8e8163c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/15757 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-05-04cpu: get rid of socket source codeStefan Reinauer
None of the sockets has actual configuration options, so the source for them is only cosmetical boilerplate. Hence, drop it. This reduces the sockets to be selectors for certain CPU types, which will be dropped in future commits, and mainboards will select their CPUs directly rather than through an additional layer of indirection (sockets) Change-Id: I0f52a65838875a73531ef8c92a171bb1a35be96e Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/9797 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
2014-07-17cpu,Makefile.inc: Trivial - drop trailing blank lines at EOFEdward O'Callaghan
Change-Id: I7e8866d76d7f286e10160d7dc4f21f01a913bfee Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/6286 Tested-by: build bot (Jenkins) Reviewed-by: Idwer Vollering <vidwer@gmail.com>
2014-07-05Drop redundant select CACHE_AS_RAMKyösti Mälkki
The few remaining boards without CAR override this with select ROMCC. Change-Id: Ifd5223e67f6a2dadb47846bdaab40b1be763cf69 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/6172 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-03-01GPLv2 notice: Unify all files to just use one space in »MA 02110-1301«Paul Menzel
In the file `COPYING` in the coreboot repository and upstream [1] just one space is used. The following command was used to convert all files. $ git grep -l 'MA 02' | xargs sed -i 's/MA 02/MA 02/' [1] http://www.gnu.org/licenses/gpl-2.0.txt Change-Id: Ic956dab2820a9e2ccb7841cab66966ba168f305f Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/2490 Tested-by: build bot (Jenkins) Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
2012-10-07Remove chip.h files without config structureKyösti Mälkki
Also deletes files not included in build: src/southbridge/amd/cimx/sb700/chip_name.c src/southbridge/amd/cimx/sb800/chip_name.c src/southbridge/amd/cimx/sb900/chip_name.c Change-Id: I2068e3859157b758ccea0ca91fa47d09a8639361 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/1473 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Marc Jones <marcj303@gmail.com>
2012-08-22Auto-declare chip_operationsKyösti Mälkki
The name is derived directly from the device path. Change-Id: If2053d14f0e38a5ee0159b47a66d45ff3dff649a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/1471 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
2011-01-27oops. this is weird. CAR addresses should be specified in the socket and not inStefan Reinauer
the board. I thought we did this ages ago. Also push CAR BASE further down so it won't conflict with a 32mbit flash part. Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6299 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-09-30Rename build system variables to be more intuitive, andPatrick Georgi
at the same time let the user specify sources instead of object files: - objs becomes ramstage-srcs - initobjs becomes romstage-srcs - driver becomes driver-srcs - smmobj becomes smm-srcs The user servicable parts are named accordingly: ramstage-y, romstage-y, driver-y, smm-y Also, the object file names are properly renamed now, using .ramstage.o, .romstage.o, .driver.o, .smm.o suffixes consistently. Remove stubbed out via/epia-m700 dsdt/ssdt files - they didn't easily fit in the build system and aren't useful anyway. Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de> Acked-by: Stefan Reinauer <stepan@coreystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5886 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-09-27This patch moves one of the CAR configs to the socket from the singleWarren Turkal
mainboard that uses it. Signed-off-by: Warren Turkal <wt@penguintechs.org> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5868 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-02-07newconfig is no more.Patrick Georgi
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5089 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-01-18Move all IOAPIC selection to southbridges, and remove themPatrick Georgi
from mainboards. Some adaptations were necessary after the IOAPIC cleanup, so this should fix the build. Fix intel/d945gclf build, which was missing some ACPI component. Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5039 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-11-04Fix up typo in Socket 441 CPUs, and add a few (trivial) Kconfig files for them.Stefan Reinauer
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4908 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-28Add some missing license headers, consistency fixes for others (trivial).Uwe Hermann
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4881 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-28preliminary Intel D945GCLF Atom+i945 support.Stefan Reinauer
ram init fails, as the i945 driver currently only supports the mobile version of the chipset.. Not sure how much sense it makes to check this in, but since it's a nice and cheap board, maybe someone wants to work on this. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4879 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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