coreboot.git - my copy of coreboot

Age	Commit message (Expand)	Author
2018-08-09	cpu/intel/smm: Make sure SMRR base is aligned to SMRR size	Arthur Heymans
2018-07-30	nb/intel/gm45: Use common code for SMM in TSEG	Arthur Heymans
2018-07-30	cpu/intel/smm/gen1: Use correct MSR for model_6fx and model_1067x	Arthur Heymans
2018-07-24	cpu/x86/mtrr.h: Rename MSR SMRR_PHYS_x to IA32_SMRR_PHYSx	Arthur Heymans
2018-04-11	Revert "model_206ax: Use parallel MP init"	Arthur Heymans
2018-04-11	model_206ax: Use parallel MP init	Arthur Heymans
2018-04-10	cpu/intel/sandybridge: Put stage cache into TSEG	Arthur Heymans
2017-08-19	intel/smm/gen1: Backup default SMM area	Kyösti Mälkki
2017-07-13	Rename __attribute__((packed)) --> __packed	Stefan Reinauer
2017-06-28	cpu/*: Add whitespace around '<<'	Elyes HAOUAS
2017-03-16	cpu/intel: Wrap lines at 80 columns	Lee Leahy
2017-03-16	cpu/intel: Fix brace issues detected by checkpatch.pl	Lee Leahy
2017-03-16	cpu/intel: Indent with tabs	Lee Leahy
2016-10-11	cpu/intel/smm: Use CONFIG_SMM_TSEG_SIZE	Nico Huber
2016-02-14	CPU/intel: Add missing license headers	Damien Roth
2015-10-31	tree: drop last paragraph of GPL copyright header	Patrick Georgi
2015-10-15	cpu/mtrr.h: Fix macro names for MTRR registers	Alexandru Gagniuc
2015-06-09	Create i945-ivy smm tseg init based on ivy code.	Vladimir Serbinenko