Age | Commit message (Expand) | Author |
2015-05-21 | Remove address from GPLv2 headers | Patrick Georgi |
2014-12-30 | intel CAR: Fix DCACHE_RAM_BASE for old sockets | Kyösti Mälkki |
2014-07-17 | cpu,Makefile.inc: Trivial - drop trailing blank lines at EOF | Edward O'Callaghan |
2014-07-08 | cpu: Trivial - drop trailing blank lines at EOF | Edward O'Callaghan |
2014-07-05 | Drop redundant select CACHE_AS_RAM | Kyösti Mälkki |
2014-01-16 | cpu/intel: Make all Intel CPUs load microcode from CBFS | Alexandru Gagniuc |
2013-07-11 | cpu: Fix spelling | Martin Roth |
2013-03-01 | GPLv2 notice: Unify all files to just use one space in »MA 02110-1301« | Paul Menzel |
2012-10-07 | Remove chip.h files without config structure | Kyösti Mälkki |
2012-08-22 | Auto-declare chip_operations | Kyösti Mälkki |
2011-08-04 | cpu/intel/slot_1: Init L2 cache on SECC(2) CPUs. | Keith Hui |
2010-10-16 | Move support for Deschutes Slot 1 CPUs (model_65x) into its own directory. | Keith Hui |
2010-10-15 | Drop unused DCACHE_RAM_BASE from intel/car/cache_as_ram.inc-using sockets. | Uwe Hermann |
2010-10-13 | Move out Katmai Slot 1 CPUs (model_67x) from model_6xx to model_67x. | Keith Hui |
2010-10-12 | Add missing include of model_6bx for slot_1. | Keith Hui |
2010-10-06 | Convert all Intel 440BX boards to Cache-as-RAM (CAR). | Uwe Hermann |
2010-09-30 | Rename build system variables to be more intuitive, and | Patrick Georgi |
2010-05-14 | license header fixes | Nils Jacobs |
2010-03-05 | Add proper Slot 1 CPU support code/infrastructure. | Keith Hui |