| Age | Commit message (Expand) | Author |
|---|
| 2020-09-21 | src/cpu: Drop unneeded empty lines | Elyes HAOUAS |
| 2020-06-04 | cpu/intel/slot_1: Select 16KiB bootblock if console is enabled | Keith Hui |
| 2020-05-18 | src: Remove leading blank lines from SPDX header | Elyes HAOUAS |
| 2020-05-11 | treewide: Remove "this file is part of" lines | Patrick Georgi |
| 2020-05-10 | src/cpu: Replace GPLv2 long form headers with SPDX header | Elyes HAOUAS |
| 2020-05-09 | src/: Replace GPL boilerplate with SPDX headers | Patrick Georgi |
| 2020-05-06 | treewide: replace GPLv2 long form headers with SPDX header | Patrick Georgi |
| 2020-05-06 | treewide: Move "is part of the coreboot project" line in its own comment | Patrick Georgi |
| 2020-03-03 | cpu/intel/slot_1: Cache romstage XIP execution | Arthur Heymans |
| 2019-11-25 | cpu/intel/slot_1: Move to C_ENVIRONMENT_BOOTBLOCK | Arthur Heymans |
| 2019-11-25 | Kconfig: Drop the C_ENVIRONMENT_BOOTBLOCK symbol | Arthur Heymans |
| 2019-11-05 | intel/i440bx: Switch to UDELAY_TSC and TSC_MONOTONIC_TIMER | Kyösti Mälkki |
| 2019-11-03 | cpu/x86/tsc: Flip and rename TSC_CONSTANT_RATE to UNKNOWN_TSC_RATE | Kyösti Mälkki |
| 2019-09-10 | AUTHORS: Move src/cpu/intel copyrights into AUTHORS file | Martin Roth |
| 2019-07-09 | arch/x86: Flip HAVE_MONOTONIC_TIMER default | Kyösti Mälkki |
| 2019-07-09 | cpu/x86: Flip SMM_TSEG default | Kyösti Mälkki |
| 2018-11-12 | src: Remove unneeded include "{arch,cpu}/cpu.h" | Elyes HAOUAS |
| 2018-06-17 | nb/intel/i440bx: Switch to POSTCAR_STAGE | Kyösti Mälkki |
| 2018-06-17 | cpu/intel/slot_1: Switch to different CAR setup | Kyösti Mälkki |
| 2018-06-01 | src/cpu: Remove unneeded includes | Elyes HAOUAS |
| 2017-09-12 | cpu/intel/slot_1: Increase CAR size to 8KiB | Keith Hui |
| 2017-03-16 | cpu/intel: Wrap lines at 80 columns | Lee Leahy |
| 2017-03-16 | cpu/intel: Fix brace issues detected by checkpatch.pl | Lee Leahy |
| 2017-03-16 | cpu/intel: Fix the spacing issues | Lee Leahy |
| 2017-03-16 | cpu/intel: Indent with tabs | Lee Leahy |
| 2016-11-08 | intel post-car: Split legacy sockets | Kyösti Mälkki |
| 2016-08-01 | Remove non-ascii & unprintable characters | Martin Roth |
| 2016-06-21 | intel/car/cache_as_ram.inc: Prepare for dynamic CONFIG_RAMTOP | Kyösti Mälkki |
| 2015-10-31 | tree: drop last paragraph of GPL copyright header | Patrick Georgi |
| 2015-09-04 | x86: remove cpu_incs as romstage Make variable | Aaron Durbin |
| 2015-05-21 | Remove address from GPLv2 headers | Patrick Georgi |
| 2014-12-30 | intel CAR: Fix DCACHE_RAM_BASE for old sockets | Kyösti Mälkki |
| 2014-07-17 | cpu,Makefile.inc: Trivial - drop trailing blank lines at EOF | Edward O'Callaghan |
| 2014-07-08 | cpu: Trivial - drop trailing blank lines at EOF | Edward O'Callaghan |
| 2014-07-05 | Drop redundant select CACHE_AS_RAM | Kyösti Mälkki |
| 2014-01-16 | cpu/intel: Make all Intel CPUs load microcode from CBFS | Alexandru Gagniuc |
| 2013-07-11 | cpu: Fix spelling | Martin Roth |
| 2013-03-01 | GPLv2 notice: Unify all files to just use one space in »MA 02110-1301« | Paul Menzel |
| 2012-10-07 | Remove chip.h files without config structure | Kyösti Mälkki |
| 2012-08-22 | Auto-declare chip_operations | Kyösti Mälkki |
| 2011-08-04 | cpu/intel/slot_1: Init L2 cache on SECC(2) CPUs. | Keith Hui |
| 2010-10-16 | Move support for Deschutes Slot 1 CPUs (model_65x) into its own directory. | Keith Hui |
| 2010-10-15 | Drop unused DCACHE_RAM_BASE from intel/car/cache_as_ram.inc-using sockets. | Uwe Hermann |
| 2010-10-13 | Move out Katmai Slot 1 CPUs (model_67x) from model_6xx to model_67x. | Keith Hui |
| 2010-10-12 | Add missing include of model_6bx for slot_1. | Keith Hui |
| 2010-10-06 | Convert all Intel 440BX boards to Cache-as-RAM (CAR). | Uwe Hermann |
| 2010-09-30 | Rename build system variables to be more intuitive, and | Patrick Georgi |
| 2010-05-14 | license header fixes | Nils Jacobs |
| 2010-03-05 | Add proper Slot 1 CPU support code/infrastructure. | Keith Hui |
