| Age | Commit message (Expand) | Author |
|---|---|---|
| 2012-01-10 | MTRR: get physical address size from CPUID | Sven Schnelle |
| 2011-08-04 | cpu/intel/slot_1: Init L2 cache on SECC(2) CPUs. | Keith Hui |
| 2010-10-18 | update intel microcode files. | Stefan Reinauer |
| 2010-10-16 | Move support for Deschutes Slot 1 CPUs (model_65x) into its own directory. | Keith Hui |
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index : coreboot.git | |
| my copy of coreboot | User & |
| summaryrefslogtreecommitdiff |