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path: root/src/cpu/intel/model_206ax
AgeCommit message (Expand)Author
2013-02-09speedstep: Deduplicate some MSR identifiersPatrick Georgi
2013-02-09document Intel VMX locking behaviorMike Frysinger
2012-11-27Get rid of drivers classPatrick Georgi
2012-11-13Fix CONFIG_MAX_CPU set to 1 CPU build problemStefan Reinauer
2012-11-12ivybridge: Catch unknown CPU revisionsStefan Reinauer
2012-11-12Initialize the VMX MSRMarc Jones
2012-11-12Revert "Remove code that enables/disables VMX in coreboot on chromebooks."Marc Jones
2012-11-12sandybridge: Correct reporting of cores and threadsStefan Reinauer
2012-11-07Leave power control registers unlockedSameer Nanda
2012-11-01Merge cpu/intel/acpi.h into cpu/intel/speedstep.hNico Huber
2012-09-05buildsystem: Make CPU microcode updating more configurableAlexandru Gagniuc
2012-08-22Auto-declare chip_operationsKyösti Mälkki
2012-08-09Synchronize rdtsc instructionsStefan Reinauer
2012-07-31Revert "Use broadcast SIPI to startup siblings"Sven Schnelle
2012-07-31Revert "remove CONFIG_SERIAL_CPU_INIT"Sven Schnelle
2012-07-26CPU: Add option to set TCC activation offsetDuncan Laurie
2012-07-26ACPI: Add a method to notify OS to re-read _PPCDuncan Laurie
2012-07-26ACPI: Add function to write _PPC using NVSDuncan Laurie
2012-07-26Drop CONFIG_CPU_MODEL_NAME and fix CPU name displayed in logsStefan Reinauer
2012-07-26Enable Microcode in CBFS for all SandyBridge/IvyBridge systemsStefan Reinauer
2012-07-25Fix comment to reference IvyBridge, tooStefan Reinauer
2012-07-25Include SandyBridge Microcode when IvyBridge is enabledStefan Reinauer
2012-07-24CPU: Set flex ratio to nominal TDP ratio in bootblockDuncan Laurie
2012-07-24CPU: Update ivybridge PP1 current limit valueDuncan Laurie
2012-07-24CPU: Add basic support for Nominal Configurable TDPDuncan Laurie
2012-07-24Config changes to support microcode in CBFSVadim Bendebury
2012-07-24Add code to read Intel microcode from CBFSVadim Bendebury
2012-07-24Rename microcode include file to be model agnosticVadim Bendebury
2012-07-24Properly identify ACPI C3 states in _CST table.Duncan Laurie
2012-07-24Remove code that enables/disables VMX in coreboot on chromebooks.Ronald G. Minnich
2012-07-04Intel cpus: Extend cache to cover complete Flash DeviceKyösti Mälkki
2012-07-04Intel cpus: use CPU_ADDR_BITS from Kconfig during CARKyösti Mälkki
2012-07-02remove CONFIG_SERIAL_CPU_INITSven Schnelle
2012-07-02Use broadcast SIPI to startup siblingsSven Schnelle
2012-05-29Drop config variable CPU_MODEL_INDEXStefan Reinauer
2012-04-30Fix up Sandybridge C state generation codeStefan Reinauer
2012-04-26Revamp Intel microcode update codeStefan Reinauer
2012-04-25Replace cache control magic numbers with symbolsPatrick Georgi
2012-04-05Add support for Intel Sandybridge CPUStefan Reinauer
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