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2021-02-14cpu/intel/model_206ax: Drop c-state table indirectionAngel Pons
Accessing it directly allows proper bounds-checking. Change-Id: I2582a7edf5fba28febe570bddccacb85a3269684 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49801 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-01soc/intel/*: Get rid of custom microcode cachingPatrick Rudolph
Get rid of custom microcode caching in MPinit and SGX code and use the caching introduced in intel_microcode_find() instead. Change-Id: If3ccd4dcff221c88839ffeafa812f4c38cede63f Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49897 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-01-15cpu/intel/*init: Remove obsolete cache enablePatrick Rudolph
The caches have already been enabled during MP-init, so these function calls are redundant. Remove them. Change-Id: Ia9be1a3388d8e7c73c35a1c68b3dd5bc488658c2 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49383 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-01-15cpu/x86/mpinit: Serialize microcode updates for HT threadsPatrick Rudolph
This change affects Intel CPUs only. As most platforms are doing uCode update using FIT, they aren't affected by this code either. Update microcode in MP-init using a single spinlock when running on a Hyper-Threading enabled CPU on pre FIT platforms. This will slow down the MP-init boot flow. Intel SDM and various BWGs specify to use a semaphore to update microcode on one thread per core on Hyper-Threading enabled CPUs. Due to this complex code would be necessary to determine the core #ID, initializing and picking the right semaphore out of CONFIG_MAX_CPUS / 2. Instead use the existing global spinlock already present in MPinit code. Assuming that only pre-FIT platforms with Hyper-Threading enabled and at most 8 threads will ever run into this condition, the boot delay is negligible. This change is a counterproposal to the previous published patch series being much more unsophisticated. Change-Id: I27bf5177859c12e92d6ce7a2966c965d7262b472 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49303 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-11-09cpu/intel/model_206ax: Get CPU frequencies for SMBIOS type 4Michał Żygowski
Calculate the frequencies based on the appropriate MSRs and pass them to SMBIOS tables generator. Ivybridge microarchitecture does not yet implement CPUID 16H leaf used to obtain the required frequencies. TEST=Intel Core i7-3770, TianoCore UEFI payload displays the CPU frequency correctly equal 3.4GHz in Boot Manager Menu, dmidecode shows correct frequencies according to Intel ARK, 3.4GHz base and 3.9GHz turbo Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: Iefbae6111d39107eacac7e61654311646c6981eb Reviewed-on: https://review.coreboot.org/c/coreboot/+/47058 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-24{cpu,soc}/intel: deduplicate cpu codeMichael Niewöhner
Move a whole bunch of copy-pasta code from soc/intel/{bdw,skl,cnl,icl, tgl,ehl,jsl,adl} and cpu/intel/{hsw,model_*} to cpu/intel/common. This change just moves the code. Rework is done in CB:46588. Change-Id: Ib0cc834de8492d59c423317598e1c11847a0b1ab Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46274 Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-21{cpu,soc}/intel: replace AES-NI locking by common implemenation callMichael Niewöhner
Deduplicate code by using the new common cpu code implementation of AES-NI locking. Change-Id: I7ab2d3839ecb758335ef8cc6a0c0c7103db0fa50 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46278 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-10-20cpu/intel/model_{2065x,206ax}: fix AES-NI lockingMichael Niewöhner
MSR_FEATURE_CONFIG, which is used for locking AES-NI, is core-scoped, not package-scoped. Thus, move locking from SMM to core init, where the code gets executed once per core. Change-Id: I3a6f7fc95ce226ce4246b65070726087eb9d689c Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46535 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-09-21src/cpu: Drop unneeded empty linesElyes HAOUAS
Change-Id: I116b15c83fcc5d69d3f80a2e6cf0fb085064d9a6 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44604 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-06-16sb,soc/intel: Replace smm_southbridge_enable_smi()Kyösti Mälkki
Change-Id: I8a2e8b0c104d9e08f07aeb6a2c32106480ace3e5 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41961 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-05-11treewide: Remove "this file is part of" linesPatrick Georgi
Stefan thinks they don't add value. Command used: sed -i -e '/file is part of /d' $(git grep "file is part of " |egrep ":( */\*.*\*/\$|#|;#|-- | *\* )" | cut -d: -f1 |grep -v crossgcc |grep -v gcov | grep -v /elf.h |grep -v nvramtool) The exceptions are for: - crossgcc (patch file) - gcov (imported from gcc) - elf.h (imported from GNU's libc) - nvramtool (more complicated header) The removed lines are: - fmt.Fprintln(f, "/* This file is part of the coreboot project. */") -# This file is part of a set of unofficial pre-commit hooks available -/* This file is part of coreboot */ -# This file is part of msrtool. -/* This file is part of msrtool. */ - * This file is part of ncurses, designed to be appended after curses.h.in -/* This file is part of pgtblgen. */ - * This file is part of the coreboot project. - /* This file is part of the coreboot project. */ -# This file is part of the coreboot project. -# This file is part of the coreboot project. -## This file is part of the coreboot project. --- This file is part of the coreboot project. -/* This file is part of the coreboot project */ -/* This file is part of the coreboot project. */ -;## This file is part of the coreboot project. -# This file is part of the coreboot project. It originated in the - * This file is part of the coreinfo project. -## This file is part of the coreinfo project. - * This file is part of the depthcharge project. -/* This file is part of the depthcharge project. */ -/* This file is part of the ectool project. */ - * This file is part of the GNU C Library. - * This file is part of the libpayload project. -## This file is part of the libpayload project. -/* This file is part of the Linux kernel. */ -## This file is part of the superiotool project. -/* This file is part of the superiotool project */ -/* This file is part of uio_usbdebug */ Change-Id: I82d872b3b337388c93d5f5bf704e9ee9e53ab3a9 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41194 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-02acpi: Move ACPI table support out of arch/x86 (3/5)Furquan Shaikh
This change moves all ACPI table support in coreboot currently living under arch/x86 into common code to make it architecture independent. ACPI table generation is not really tied to any architecture and hence it makes sense to move this to its own directory. In order to make it easier to review, this change is being split into multiple CLs. This is change 3/5 which basically is generated by running the following command: $ git grep -iIl "arch/acpi" | xargs sed -i 's/arch\/acpi/acpi\/acpi/g' BUG=b:155428745 Change-Id: I16b1c45d954d6440fb9db1d3710063a47b582eae Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40938 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2020-04-04src/cpu: Use SPDX for GPL-2.0-only filesAngel Pons
Done with sed and God Lines. Only done for C-like code for now. Change-Id: I2adf28d805fe248d55a9514f74c38280c0ad9a78 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40049 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2020-03-04cpu/intel/model_206ax: Lock MSR on all coresPatrick Rudolph
Lock MSR MSR_PKG_CST_CONFIG_CONTROL on all cores, not only the one handling APM_CNT_FINALIZE. Tested on HP Z220: FWTS no longer reports this as an issue. Change-Id: I174d6c6c74fbba47992084cc44ebddf84eeeabd1 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39199 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-12-18src: Remove unused 'include <pc80/mc146818rtc.h>'Elyes HAOUAS
Change-Id: I72d7b83ef8c7f9b5b4b4376839279eff9b0a5f8f Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37484 Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-10AUTHORS: Move src/cpu/intel copyrights into AUTHORS fileMartin Roth
As discussed on the mailing list and voted upon, the coreboot project is going to move the majority of copyrights out of the headers and into an AUTHORS file. This will happen a bit at a time, as we'll be unifying license headers at the same time. Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: I39f52764dc377c25953ef5dba16982a0b4637cdb Reviewed-on: https://review.coreboot.org/c/coreboot/+/35181 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Guckian Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-08-15soc/intel: Rename some SMM support functionsKyösti Mälkki
Rename southbridge_smm_X to smm_southbridge_X. Rename most southcluster_smm_X to smm_southbridge_X. Change-Id: I4f6f9207ba32cf51d75b9ca9230e38310a33a311 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34856 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-15intel/smm/gen1: Rename header fileKyösti Mälkki
Change-Id: I258fccc5e1db0bedb641c8af8cb9727954d4d7c1 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34869 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-08-15cpu/intel: Replace bsp_init_and_start_aps()Kyösti Mälkki
Change-Id: I7176efdd1000789a093a1b4e243b4b150e6bb06f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34864 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-21cpu/intel/{haswell,model_206{5,a}x}: Use MSR_CORE_THREAD_COUNT for msr at 0x35Elyes HAOUAS
Regarding 64 and IA-32 Architectures Software Developer’s Manual, the register name of the msr at 0x35 is MSR_CORE_THREAD_COUNT. Change-Id: I5134619dc3a42187ddd5f46c85873c4278229e27 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33015 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-23src: include <assert.h> when appropriateElyes HAOUAS
Change-Id: Ib843eb7144b7dc2932931b9e8f3f1d816bcc1e1a Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/26796 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: David Guckian
2019-03-20src: Use 'include <string.h>' when appropriateElyes HAOUAS
Drop 'include <string.h>' when it is not used and add it when it is missing. Also extra lines removed, or added just before local includes. Change-Id: Iccac4dbaa2dd4144fc347af36ecfc9747da3de20 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31966 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-03-04arch/x86/acpi: Remove obsolete acpi_gen_regaddr resv fieldElyes HAOUAS
Since ACPI v2.c, this field is access_size. Currently, coreboot is using ACPI v3,so we can drop '.resv' field. Change-Id: I7b3b930861669bb05cdc8e81f6502476a0568fe0 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/31701 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-01-22cpu/intel/model_206ax: Use parallel MP initArthur Heymans
This patch adds a few southbridge calls needed for parallel MP init. Moves the smm_relocate() function to smm/gen1/smi.h, since that is where this function is defined now. Tested on Thinkpad X220, shaves off ~30ms on a 2 core, 4 threads CPU. Change-Id: Ia1d547ed4a3cb6746a0222c3e54e94e5848b0dd7 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/25618 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-12-20cpu/intel/common: decouple IA32_FEATURE_CONTROL lock from set_vmx()Matt DeVillier
Newer CPUs/SoCs need to configure other features via the IA32_FEATURE_CONTROL msr, such as SGX, which cannot be done if the msr is already locked. Create separate functions for setting the vmx flag and lock bit, and rename existing function to indicate that the lock bit will be set in addition to vmx flag (per Kconfig). This will allow Skylake/Kabylake (and others?) to use the common VMX code without breaking SGX, while ensuring no change in functionality to existing platforms which current set both together. Test: build/boot each affected platform, ensure no change in functionality Change-Id: Iee772fe87306b4729ca012cef8640d3858e2cb06 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/30229 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: David Guckian Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-12-13cpuid: Add helper function for cpuid(1) functionsSubrata Banik
This patch introduces 3 helper function for cpuid(1) : 1. cpu_get_cpuid() -> to get processor id (from cpuid.eax) 2. cpu_get_feature_flags_ecx -> to get processor feature flag (from cpuid.ecx) 3. cpu_get_feature_flags_edx -> to get processor feature flag (from cpuid.edx) Above 3 helper functions are targeted to replace majority of cpuid(1) references. Change-Id: Ib96a7c79dadb1feff0b8d58aa408b355fbb3bc50 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/30123 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-10-11src: Move common IA-32 MSRs to <cpu/x86/msr.h>Elyes HAOUAS
Use "cpu/x86/msr.h" for common IA-32 MSRs and correct IA-32 MSRs names. Change-Id: Ida7f2d608c55796abf9452f190a58802e498302d Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/28752 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-05src: Fix MSR_PKG_CST_CONFIG_CONTROL register nameElyes HAOUAS
Change-Id: I492224b6900b9658d54c8cf486ef5d64b299687f Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/28871 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
2018-09-26cpu/intel/model_206ax: detect number of MCE banksDan Elkouby
My CPU (3770k) supports 9 MCE banks, but the code is hardcoded to reset only 7. This causes Linux to spuriously log errors during boot and S3 resume. Fix this by reading the real value from the right MSR. Change-Id: Id05645009259fd77b4de49bde518361eeae46617 Signed-off-by: Dan Elkouby <streetwalkermc@gmail.com> Reviewed-on: https://review.coreboot.org/28443 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tristan Corrick <tristan@corrick.kiwi> Reviewed-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-07-28nb/intel/sandybridge: Move CPU report to cpu folderPatrick Rudolph
Change-Id: Ie973923b90eca0bfabd474fed85a6cc33fce7e19 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/27666 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-07-28intel/sandybridge: Don't hardcode platform typePatrick Rudolph
* Add a function to return CPU platform ID bits * Add a function to return platform type ** Platform id is 4 on Lenovo T430 (mobile) ** Platform id is 1 on HP8200 (desktop) * Use introduced method to handle platform specific code * Use enum for platform type * Report platform ID Change-Id: Ifbfc64c8cec98782d6efc987a4d4d5aeab1402ba Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/22530 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-04-11Revert "model_206ax: Use parallel MP init"Arthur Heymans
This reverts commit 5fbe788bae15f0d24d56011e8eb8b48c107b7b05. This commit was submitted without its parent being submitted, resulting in coreboot not building. Change-Id: I87497093ccf6909b88e3a40d5f472afeb7f2c552 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/25616 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-04-11model_206ax: Use parallel MP initArthur Heymans
This patch adds a few southbridge calls needed for parallel MP init. Moves the smm_relocate() function to smm/gen1/smi.h, since that is where this function is defined now. Tested on Thinkpad X220, shaves of ~30ms on a 2 core, 4 threads CPU. Change-Id: Iacd7bfedfccbc09057e1b7ca3bd03d44a888871d Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/23432 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-11-23Constify struct cpu_device_id instancesJonathan Neuschäfer
There is currently no case where a struct cpu_device_id instance needs to be modified. Thus, declare all instances as const. Change-Id: I5ec7460b56d75d255b3451d76a46df76a51d6365 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/22526 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-19arch/x86: Clean up CONFIG_SMP and MAX_CPUS testKyösti Mälkki
Change-Id: I7c138758707f87c0d7a827b6887c7752d3714cde Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21088 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-06-28cpu/intel: add IS_ENABLED() around Kconfig symbol referencesMartin Roth
Some of these can be changed from #if to if(), but that will happen in a follow-on commmit. Change-Id: Ie685bbbb1cbf06d32631ea40ad120b6f45374b2e Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/20336 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-03-16cpu/intel: Add int to unsignedLee Leahy
Fix the following warning detected by checkpatch.pl: WARNING: Prefer 'unsigned int' to bare use of 'unsigned' TEST=Build and run on Galileo Gen2 Change-Id: I207713a3370e5a9abed4535187aa2aaeef502d6f Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/18848 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-03-16cpu/intel: Fix the spacing issuesLee Leahy
Fix the following errors and warnings detected by checkpatch.pl: ERROR: spaces required around that '=' (ctx:VxV) ERROR: space required after that ',' (ctx:VxV) ERROR: space prohibited after that open parenthesis '(' ERROR: space prohibited before that close parenthesis ')' ERROR: need consistent spacing around '-' (ctx:WxV) ERROR: spaces required around that '>' (ctx:VxV) ERROR: need consistent spacing around '>>' (ctx:WxV) ERROR: need consistent spacing around '<<' (ctx:VxW) ERROR: spaces required around that '||' (ctx:VxV) ERROR: "foo * bar" should be "foo *bar" ERROR: "(foo*)" should be "(foo *)" WARNING: space prohibited between function name and open parenthesis '(' WARNING: storage class should be at the beginning of the declaration TEST=Build and run on Galileo Gen2 Change-Id: I6602fbc8602171ab6c2f3b6c204558ad2c811179 Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/18847 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-03-16cpu/intel: Indent with tabsLee Leahy
Fix the following error and warning detected by checkpatch.pl: ERROR: code indent should use tabs where possible WARNING: please, no space before tabs TEST=Build and run on Galileo Gen2 Change-Id: I5bcd82561ef5856e99055d46528dcf3a283d2310 Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/18846 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-12-27cpu/intel/common: Add/Use common function to set virtualizationMatt DeVillier
Migrate duplicated enable_vmx() method from multiple CPUs to common folder. Add common virtualization option for CPUs which support it. Note that this changes the default to enable virtualization on CPUs that support it. Change-Id: Ib110bed6c9f5508e3f867dcdc6f341fc50e501d1 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/17874 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins)
2016-08-23src/cpu: Capitalize CPU, APIC and IOAPIC typo fixElyes HAOUAS
Change-Id: I82e0736dc6b44cfcc57cdfdc786c85c4b6882260 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16276 Tested-by: build bot (Jenkins) Reviewed-by: Omar Pakker
2016-07-31src/cpu: Capitalize CPUElyes HAOUAS
Change-Id: I58d5c16de796a91fa14d8db78722024266c09a94 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/15934 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-08x86 chipsets: utilize x86_setup_mtrrs_with_detect()Aaron Durbin
For all the chipsets which were performing the following sequence: x86_setup_fixed_mtrrs(); x86_setup_var_mtrrs(cpuid_eax(0x80000008) & 0xff, 2); Replace that with x86_setup_mtrrs_with_detect() since it is equivalent. Change-Id: I9f362dbf38942d675f615d22b9e5770ce65e5a08 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/13936 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
2015-10-31tree: drop last paragraph of GPL copyright headerPatrick Georgi
It encourages users from writing to the FSF without giving an address. Linux also prefers to drop that and their checkpatch.pl (that we imported) looks out for that. This is the result of util/scripts/no-fsf-addresses.sh with no further editing. Change-Id: Ie96faea295fe001911d77dbc51e9a6789558fbd6 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/11888 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-06-10model_206ax: Fix APIC map when HT is disabled.Vladimir Serbinenko
Change-Id: Idd05a16bd9bd31438437ef229aa87f55da8489fb Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/10467 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-06-09Create i945-ivy smm tseg init based on ivy code.Vladimir Serbinenko
CPU-side logic is unchanged for this range of CPUs as long as all of them use TSEG (or ASEG, just needs to be consistent). So uplift 206ax code while extracting southbridge and APIC code into separate functions. Change-Id: Ib365681d1da8115922c557fddcc59afc156826da Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/10465 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-05-21Remove address from GPLv2 headersPatrick Georgi
As per discussion with lawyers[tm], it's not a good idea to shorten the license header too much - not for legal reasons but because there are tools that look for them, and giving them a standard pattern simplifies things. However, we got confirmation that we don't have to update every file ever added to coreboot whenever the FSF gets a new lease, but can drop the address instead. util/kconfig is excluded because that's imported code that we may want to synchronize every now and then. $ find * -type f -exec sed -i "s:Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, *MA[, ]*02110-1301[, ]*USA:Foundation, Inc.:" {} + $ find * -type f -exec sed -i "s:Foundation, Inc., 51 Franklin Street, Suite 500, Boston, MA 02110-1335, USA:Foundation, Inc.:" {} + $ find * -type f -exec sed -i "s:Foundation, Inc., 59 Temple Place[-, ]*Suite 330, Boston, MA *02111-1307[, ]*USA:Foundation, Inc.:" {} + $ find * -type f -exec sed -i "s:Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.:Foundation, Inc.:" {} + $ find * -type f -a \! -name \*.patch \ -a \! -name \*_shipped \ -a \! -name LICENSE_GPL \ -a \! -name LGPL.txt \ -a \! -name COPYING \ -a \! -name DISCLAIMER \ -exec sed -i "/Foundation, Inc./ N;s:Foundation, Inc.* USA\.* *:Foundation, Inc. :;s:Foundation, Inc. $:Foundation, Inc.:" {} + Change-Id: Icc968a5a5f3a5df8d32b940f9cdb35350654bef9 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/9233 Tested-by: build bot (Jenkins) Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
2014-10-27{arch,cpu,drivers,ec}: Don't hide pointers behind typedefsEdward O'Callaghan
Change-Id: Id88bb4367d6045f6fbf185f0562ac72c04ee5f84 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: http://review.coreboot.org/7146 Tested-by: build bot (Jenkins)
2014-08-04cpu/intel: Fix out-of-bounds read due to off-by-one in conditionEdward O'Callaghan
If power_limit_1_time > 129 is false then power_limit_1_time can have a value of up to 129 leading to an out-of-bounds illegal read indexing the power_limit_time_sec_to_msr[] array. Thankfully all call sites have been doing the right thing up until now so the issue has not been visible. Change-Id: Ic029d1af7fe43ca7da271043c2b08fe3088714af Found-by: Coverity Scan Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/6478 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-07-08cpu: Trivial - drop trailing blank lines at EOFEdward O'Callaghan
Change-Id: I9004f34ba0c13b4489b26ac8c1476d00a6c6d01d Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/6207 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-02-12PCI: Drop includes under cpuKyösti Mälkki
The files affected do not make any PCI configuration calls. If they did, the more correct includes would be pci_ops.h, pci_defs.h and pci_ids.h. Change-Id: I3e7f009371be6ea50318eaabf0c15500cb3f1210 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5200 Reviewed-by: Aaron Durbin <adurbin@google.com> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins)
2013-07-11cpu: Fix spellingMartin Roth
Change-Id: I69c46648de0689e9bed84c7726906024ad65e769 Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/3729 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-11usbdebug: Drop old includesKyösti Mälkki
Change-Id: I4786bff41fef924c72087c354e394bdc1996cadc Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3764 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-06-14usbdebug: Drop temporary disables of log outputKyösti Mälkki
With this patch, output on usbdebug also includes the section of MTRR setups for every CPU. This makes usbdebug output almost identical with that of serial port and CBMEM console. Tested with model_206ax. Also tested previously on model_f2x which does not have these disable/enable calls in model_f2x_init() without detected issues. Change-Id: Idfd0e93439907b17255633658195d698feab3895 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3423 Reviewed-by: Aaron Durbin <adurbin@google.com> Tested-by: build bot (Jenkins)
2013-02-09speedstep: Deduplicate some MSR identifiersPatrick Georgi
In particular: MSR_PMG_CST_CONFIG_CONTROL MSR_PMG_IO_BASE_ADDR MSR_PMG_IO_CAPTURE_ADDR Change-Id: Ief2697312f0edf8c45f7d3550a7bedaff1b69dc6 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/2337 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-02-09document Intel VMX locking behaviorMike Frysinger
Add a comment explaining that the existing lock bit logic is correct and "as designed" even though the manual states otherwise. This way people don't have to "just know" what is going on. Change-Id: I14e6763abfe339e034037b73db01d4ee634bb34d Signed-off-by: Mike Frysinger <vapier@chromium.org> Reviewed-on: http://review.coreboot.org/2326 Tested-by: build bot (Jenkins) Reviewed-by: Peter Stuge <peter@stuge.se>
2012-11-13Fix CONFIG_MAX_CPU set to 1 CPU build problemStefan Reinauer
There are some function dependancies that didn't work when MAX_CPU was set to 1 and the build would fail. Change-Id: I033a42056f7b48a40316e03772ed89ad9cb013fe Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/1819 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins)
2012-11-12ivybridge: Catch unknown CPU revisionsStefan Reinauer
Adding an entry for 0x306a0 will make sure that all CPUs with CPUIDs 0x306aX will execute the driver (analog to Sandybridge behavior) Change-Id: I0353f3a48ecfd41274fdf6ee302c7d34482f1b5b Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1783 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-12Initialize the VMX MSRMarc Jones
The VMX MSR may come up with random values and needs to be initialized to zero. This was done incorrectly in finalize_smm. It must be done on a per core basis in the general CPU init. This touches all Sandybridge and Ivybridge configs. Change-Id: I015352d0f8e2ebe55ac0a5e9c5bbff83bd2ff86b Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/1794 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-11-12Revert "Remove code that enables/disables VMX in coreboot on chromebooks."Marc Jones
The MSR for VMX can start with a random value and needs to be cleared by coreboot. I am reverting this change, as it handles almost everything and doing a follow-on change to fix the improper clearing of the MSR. Change-Id: Ibad7a27b03f199241c52c1ebdd2b6d4e81a18a4e Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/1793 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-11-12sandybridge: Correct reporting of cores and threadsStefan Reinauer
The reporting of cores and threads in the system was a bit ambiguous. This patch makes it clearer. Change-Id: Ia05838a53f696fbaf78a1762fc6f4bf348d4ff0e Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1786 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-07-31Revert "Use broadcast SIPI to startup siblings"Sven Schnelle
This reverts commit 042c1461fb777e583e5de48edf9326e47ee5595f. It turned out that sending IPIs via broadcast doesn't work on Sandybridge. We tried to come up with a solution, but didn't found any so far. So revert the code for now until we have a working solution. Change-Id: I7dd1cba5a4c1e4b0af366b20e8263b1f6f4b9714 Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/1381 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-07-26CPU: Add option to set TCC activation offsetDuncan Laurie
The default TCC activation offset is 0, which means TCC activation starts at Tj_max. For devices with limited cooling ability it may be desired to lower TCC activation. This adds an option that can be declared in the devicetree to set the TCC activation to a non-zero value. Enable tcc_offset=15 in devicetree.cb and build/boot the BIOS and check that the value is set in the MSR: > and $(shr $(rdmsr 0 0x1a2) 24) 0xf 0xf Change-Id: I88f6857b40fd354f70fa9d5d9c1d8ceaea6dfcd1 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/1343 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-07-26Enable Microcode in CBFS for all SandyBridge/IvyBridge systemsStefan Reinauer
Change-Id: Idee4facc18e0be60906d2a2f0e99bd39de8d7247 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1332 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-07-24CPU: Update ivybridge PP1 current limit valueDuncan Laurie
The BWG says ivybridge current limit for PP1 is 50A. Verify the PP1 current limit value on link device: > echo $(( ( $(rdmsr 0 0x602) & 0x1fff ) >> 3 )) 50 Change-Id: I946269d21ef605f2525fe03993f569d69128294b Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/1305 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-07-24CPU: Add basic support for Nominal Configurable TDPDuncan Laurie
Ivybridge B0+ CPUs are capable of supporting multiple TDP levels. This complicates the default case because now the registers that were reporting max non-turbo ratio are reporting that value for the highest possible TDP level. For now this change just forces everything to use the Nominal TDP values instead of the higher (or lower) levels. - When building P-state tables, determine the P[1] (max non turbo) ratio based on the Nominal ratio if available. - Set the turbo activation ratio to the Nominal max ratio. - Mirror the power level settings in new MCHBAR register after they are written, which happens after BIOS_RESET_CPL is set. - Set the current ratio to Nominal ratio at boot. 1) Verify that P-state table is generated properly with P[0]=1801MHz (ratio 0x1C) and P[1]=1800MHz (ratio 0x12) PSS: 1801MHz power 17000 control 0x1c00 status 0x1c00 PSS: 1800MHz power 17000 control 0x1200 status 0x1200 2) Verify power limits in MCHBAR match PKG_POWER_LIMIT: > rdmsr 0 0x610 0x800080aa00dc8088 > mmio_read32 0xfed159a4 0x000080aa > mmio_read32 0xfed159a0 0x00dc8088 3) Verify turbo activation ratio is set to nominal ratio: > rdmsr 0 0x64c 0x0000000000000012 4) Check that proper ratio was set at boot on one core only: > grep 'frequency set to' /sys/firmware/log model_x06ax: frequency set to 1800 model_x06ax: frequency set to 1800 model_x06ax: frequency set to 1800 model_x06ax: frequency set to 1800 Change-Id: I592e60a7740f31b140986a8269dca91b4adbb270 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/1304 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-07-24Add code to read Intel microcode from CBFSVadim Bendebury
When CONFIG_MICROCODE_IN_CBFS is enabled, find the microcode blob in CBFS and pass it to intel_update_microcode() instead of using the compiled in array. CBFS accesses in pre-RAM and 'normal' environments are provided through different API. Change-Id: I35c1480edf87e550a7b88c4aadf079cf3ff86b5d Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: http://review.coreboot.org/1296 Tested-by: build bot (Jenkins)
2012-07-24Rename microcode include file to be model agnosticVadim Bendebury
In preparation to support CBFS hosted microcode blobs, this change renames the wrapper include file containing the microcode to be independent of CPU model. Change-Id: If1a4963a52e5037a3a3495b90708ffc08b23f4c1 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: http://review.coreboot.org/1294 Tested-by: build bot (Jenkins)
2012-07-24Remove code that enables/disables VMX in coreboot on chromebooks.Ronald G. Minnich
There are several reasons for this: 1. It's a core setting, not a platform setting, which is bizarre. But, we disable vmx via an SMI, and that only happens on core 0. Hence, the code did not correctly make the same settings on all cores- one had them disabled, the others were in an unknown state. When (e.g.) kvm started on a vmx-enabled core, then moved to a vmx-disabled core, the processor would reset *very* quickly. Changing this would be messy. 2. On the CPU on link, there is something about trying to set the lock bit that is getting a GPF. 3. It's the wrong place and time to set it. Once controlled, they can't be changed in the kernel. The kernel is what should control this feature, not the BIOS, as we have learned time and time again. If somebody is in as root and can start a VM, you have a lot more to worry about than someone starting a guest virtual machine. Change-Id: I4f36093f1b68207251584066ccb9a6bcfeec767e Signed-off-by: Ronald G. Minnich <rminnich@chromium.org> Reviewed-on: http://review.coreboot.org/1276 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-07-02Use broadcast SIPI to startup siblingsSven Schnelle
The current code for initializing AP cpus has several shortcomings: - it assumes APIC IDs are sequential - it uses only the BSP for determining the AP count, which is bad if there's more than one physical CPU, and CPUs are of different type Note that the new code call cpu->ops->init() in parallel, and therefore some CPU code needs to be changed to address that. One example are old Intel HT enabled CPUs which can't do microcode update in parallel. Change-Id: Ic48a1ebab6a7c52aa76765f497268af09fa38c25 Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/1139 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-04-05Add support for Intel Sandybridge CPUStefan Reinauer
Change-Id: I9f37e291c00c0640c6600d8fdd6dcc13c3e5b8d5 Signed-off-by: Duncan Laurie <dlaurie@google.com> Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/855 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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