coreboot.git - my copy of coreboot

Age	Commit message (Expand)	Author
2013-02-09	speedstep: Deduplicate some MSR identifiers	Patrick Georgi
2013-02-09	document Intel VMX locking behavior	Mike Frysinger
2012-11-13	Fix CONFIG_MAX_CPU set to 1 CPU build problem	Stefan Reinauer
2012-11-12	ivybridge: Catch unknown CPU revisions	Stefan Reinauer
2012-11-12	Initialize the VMX MSR	Marc Jones
2012-11-12	Revert "Remove code that enables/disables VMX in coreboot on chromebooks."	Marc Jones
2012-11-12	sandybridge: Correct reporting of cores and threads	Stefan Reinauer
2012-07-31	Revert "Use broadcast SIPI to startup siblings"	Sven Schnelle
2012-07-26	CPU: Add option to set TCC activation offset	Duncan Laurie
2012-07-26	Enable Microcode in CBFS for all SandyBridge/IvyBridge systems	Stefan Reinauer
2012-07-24	CPU: Update ivybridge PP1 current limit value	Duncan Laurie
2012-07-24	CPU: Add basic support for Nominal Configurable TDP	Duncan Laurie
2012-07-24	Add code to read Intel microcode from CBFS	Vadim Bendebury
2012-07-24	Rename microcode include file to be model agnostic	Vadim Bendebury
2012-07-24	Remove code that enables/disables VMX in coreboot on chromebooks.	Ronald G. Minnich
2012-07-02	Use broadcast SIPI to startup siblings	Sven Schnelle
2012-04-05	Add support for Intel Sandybridge CPU	Stefan Reinauer