coreboot.git - my copy of coreboot

Age	Commit message (Expand)	Author
2014-05-06	Introduce stage-specific architecture for coreboot	Furquan Shaikh
2014-05-03	Move ARCH_* from board/Kconfig to cpu or soc Kconfig.	Furquan Shaikh
2014-04-26	Rename coreboot_ram stage to ramstage	Furquan Shaikh
2014-04-26	Get rid of HAVE_INIT_TIMER config option	Furquan Shaikh
2014-02-20	intel/model_2065x: Fix APICID generation.	Vladimir Serbinenko
2014-02-12	PCI: Drop includes under cpu	Kyösti Mälkki
2014-02-01	cpu/intel/model_2065x: Add model 20652	Vladimir Serbinenko
2014-01-23	intel/microcode: Remove leftover MICROCODE_INCLUDE_PATH.	Vladimir Serbinenko
2014-01-16	cpu/intel: Remove dummy terminators from microcode blobs	Alexandru Gagniuc
2014-01-15	nehalem/sandy/ivy/haswell: Enable WRPROT cache for all of flash	Kyösti Mälkki
2014-01-15	Re-declare CACHE_ROM_SIZE as aligned ROM_SIZE for MTRR	Kyösti Mälkki
2013-12-13	cpu: Rename CPU_MICROCODE_IN_CBFS to SUPPORT_CPU_UCODE_IN_CBFS	Alexandru Gagniuc
2013-11-23	Rename SANDYBRIDGE_BCLK to NEHALEM_BCLK in 2065x.	Vladimir Serbinenko
2013-11-23	Remove MRC variables from 2065x CAR init.	Vladimir Serbinenko
2013-11-21	Fix error message on wrong compiles of 2065x	Vladimir Serbinenko
2013-11-13	intel/2065x: Use TSC for udelay()	Vladimir Serbinenko
2013-07-11	cpu: Fix spelling	Martin Roth
2013-07-11	usbdebug: Drop old includes	Kyösti Mälkki
2013-07-10	usbdebug: Put ehci_debug_info in CAR_GLOBAL	Kyösti Mälkki
2013-06-14	usbdebug: Drop temporary disables of log output	Kyösti Mälkki
2013-06-13	Add support for Intel Nehalem CPU	Vladimir Serbinenko