aboutsummaryrefslogtreecommitdiff
path: root/src/cpu/intel/model_2065x
AgeCommit message (Expand)Author
2018-11-12src: Remove unneeded include "{arch,cpu}/cpu.h"Elyes HAOUAS
2018-10-11src: Move common IA-32 MSRs to <cpu/x86/msr.h>Elyes HAOUAS
2018-10-05src: Fix MSR_PKG_CST_CONFIG_CONTROL register nameElyes HAOUAS
2018-08-09src/cpu: Fix typoElyes HAOUAS
2018-06-21Revert "sb/intel/{bd82x6,ibexpeak}: Move RCBA macros to a common location"Arthur Heymans
2018-06-05cpu/intel/model_2065x: Switch to POSTCAR_STAGEArthur Heymans
2018-06-05cpu/intel/car/non-evict: Prepare for some POSTCAR_STAGE supportArthur Heymans
2018-05-01Fix freeze during chipset lockdown on NehalemMatthias Gazzari
2018-04-30cpu/intel: Get rid of device_tElyes HAOUAS
2018-04-11Revert "model_206ax: Use parallel MP init"Arthur Heymans
2018-04-11model_206ax: Use parallel MP initArthur Heymans
2018-04-09intel/nehalem post-car: Use postcar_frame for MTRR setupKyösti Mälkki
2018-02-27sb/intel/{bd82x6,ibexpeak}: Move RCBA macros to a common locationArthur Heymans
2017-11-23Constify struct cpu_device_id instancesJonathan Neuschäfer
2017-08-19arch/x86: Clean up CONFIG_SMP and MAX_CPUS testKyösti Mälkki
2017-06-28cpu/intel: add IS_ENABLED() around Kconfig symbol referencesMartin Roth
2017-06-07Use more secure HTTPS URLs for coreboot sitesPaul Menzel
2017-03-16cpu/intel: Add int to unsignedLee Leahy
2017-03-16cpu/intel: Fix the spacing issuesLee Leahy
2017-03-16cpu/intel: Indent with tabsLee Leahy
2016-12-27cpu/intel/common: Add/Use common function to set virtualizationMatt DeVillier
2016-11-11intel cache-as-ram: Unify stack setupKyösti Mälkki
2016-08-23src/cpu: Capitalize CPU, APIC and IOAPIC typo fixElyes HAOUAS
2016-07-31src/cpu: Capitalize CPUElyes HAOUAS
2016-07-22intel car: Unify postcodesKyösti Mälkki
2016-07-22intel car: Unify whitespace and comment fixesKyösti Mälkki
2016-06-22Ignore RAMTOP for MTRRsKyösti Mälkki
2016-06-22intel/model_2065x: Prepare for dynamic CONFIG_RAMTOPKyösti Mälkki
2016-06-17Fix some cbmem.h includesKyösti Mälkki
2016-03-08x86 chipsets: utilize x86_setup_mtrrs_with_detect()Aaron Durbin
2015-10-31tree: drop last paragraph of GPL copyright headerPatrick Georgi
2015-10-15cpu/mtrr.h: Fix macro names for MTRR registersAlexandru Gagniuc
2015-09-30cpu: microcode: Use microcode stored in binary formatAlexandru Gagniuc
2015-09-09intel/model_2065x/Kconfig: Don't use LAPIC_MONOTONIC_TIMERMartin Roth
2015-09-04x86: remove cpu_incs as romstage Make variableAaron Durbin
2015-07-07x86: Drop -Wa,--divideStefan Reinauer
2015-06-10model_2065x: Use common i945-ivy TSEG SMM init.Vladimir Serbinenko
2015-06-08Remove empty lines at end of fileElyes HAOUAS
2015-06-05device_ops: add device_t argument to acpi_fill_ssdt_generatorAlexander Couzens
2015-06-04Remove address from GPLv2 headersPatrick Georgi
2015-05-28smm: Merge configs SMM_MODULES and SMM_TSEGVladimir Serbinenko
2015-05-28Migrate 2065x to SMM_MODULESVladimir Serbinenko
2015-05-28intel: Remove pstate_coord_type.Vladimir Serbinenko
2015-05-26acpigen: Remove all explicit length trackingVladimir Serbinenko
2015-05-21Remove address from GPLv2 headersPatrick Georgi
2015-05-053rdparty: move to 3rdparty/blobsPatrick Georgi
2015-05-053rdparty: Move to blobsPatrick Georgi
2015-03-13cpu/intel/2065x: add define for MSR IA32_FERR_CAPABILITYAlexander Couzens
2015-02-28cpu/intel: (non-FSP) Remove microcode updates from treeAlexandru Gagniuc
2015-02-28cpu/intel (non-FSP): Use microcode from blobs repositoryAlexandru Gagniuc
2015-02-18cpu/intel/model_2065x|nehalem: remove unsupported MSR_PP0/MSR_PP1Alexander Couzens
2015-02-11cpu/intel: >= nehalem: add comments to msr finalize'sAlexander Couzens
2015-01-31intel/model_2065x: update microcodeNicolas Reinecke
2015-01-27vboot2: add verstageStefan Reinauer
2014-12-02Replace hlt with halt()Patrick Georgi
2014-11-19acpigen: Add and use acpigen_write_method.Vladimir Serbinenko
2014-11-09ibexpeak, bd82x6x: Move to implicit length patchingVladimir Serbinenko
2014-10-27{arch,cpu,drivers,ec}: Don't hide pointers behind typedefsEdward O'Callaghan
2014-10-19x86 romstage: Move stack just below RAMTOPKyösti Mälkki
2014-10-16ACPI: Remove CONFIG_GENERATE_ACPI_TABLESVladimir Serbinenko
2014-08-12cpu/intel/XXX/acpi.c: Fix coding style violationMartin Roth
2014-07-30cpu/intel/model_2065x/model_2065x_init.c: Remove dead codeEdward O'Callaghan
2014-07-19intel/model_2065x: Remove dead code.Vladimir Serbinenko
2014-07-08cpu: Trivial - drop trailing blank lines at EOFEdward O'Callaghan
2014-07-05intel: Make monotonic timer a first class citizenEdward O'Callaghan
2014-06-17intel/model_2065x: Add 20652 microcode.Vladimir Serbinenko
2014-05-10Replace SERIAL_CPU_INIT with PARALLEL_CPU_INITKyösti Mälkki
2014-05-06Introduce stage-specific architecture for corebootFurquan Shaikh
2014-05-03Move ARCH_* from board/Kconfig to cpu or soc Kconfig.Furquan Shaikh
2014-04-26Rename coreboot_ram stage to ramstageFurquan Shaikh
2014-04-26Get rid of HAVE_INIT_TIMER config optionFurquan Shaikh
2014-02-20intel/model_2065x: Fix APICID generation.Vladimir Serbinenko
2014-02-12PCI: Drop includes under cpuKyösti Mälkki
2014-02-01cpu/intel/model_2065x: Add model 20652Vladimir Serbinenko
2014-01-23intel/microcode: Remove leftover MICROCODE_INCLUDE_PATH.Vladimir Serbinenko
2014-01-16cpu/intel: Remove dummy terminators from microcode blobsAlexandru Gagniuc
2014-01-15nehalem/sandy/ivy/haswell: Enable WRPROT cache for all of flashKyösti Mälkki
2014-01-15Re-declare CACHE_ROM_SIZE as aligned ROM_SIZE for MTRRKyösti Mälkki
2013-12-13cpu: Rename CPU_MICROCODE_IN_CBFS to SUPPORT_CPU_UCODE_IN_CBFSAlexandru Gagniuc
2013-11-23Rename SANDYBRIDGE_BCLK to NEHALEM_BCLK in 2065x.Vladimir Serbinenko
2013-11-23Remove MRC variables from 2065x CAR init.Vladimir Serbinenko
2013-11-21Fix error message on wrong compiles of 2065xVladimir Serbinenko
2013-11-13intel/2065x: Use TSC for udelay()Vladimir Serbinenko
2013-07-11cpu: Fix spellingMartin Roth
2013-07-11usbdebug: Drop old includesKyösti Mälkki
2013-07-10usbdebug: Put ehci_debug_info in CAR_GLOBALKyösti Mälkki
2013-06-14usbdebug: Drop temporary disables of log outputKyösti Mälkki
2013-06-13Add support for Intel Nehalem CPUVladimir Serbinenko