summaryrefslogtreecommitdiff
path: root/src/cpu/intel/haswell/haswell.h
AgeCommit message (Expand)Author
2020-05-11treewide: Remove "this file is part of" linesPatrick Georgi
2020-04-04src/cpu: Use SPDX for GPL-2.0-only filesAngel Pons
2019-12-19src: Remove unused 'include <arch/cpu.h>'Elyes HAOUAS
2019-09-13intel/haswell: Remove some __PRE_RAM__ useKyösti Mälkki
2019-09-10AUTHORS: Move src/cpu/intel copyrights into AUTHORS fileMartin Roth
2019-08-18cpu/intel: Enter romstage without BISTKyösti Mälkki
2019-08-15soc/intel: Rename some SMM support functionsKyösti Mälkki
2019-08-15cpu/intel: Replace bsp_init_and_start_aps()Kyösti Mälkki
2019-08-03intel/haswell: Move stage_cache support functionKyösti Mälkki
2019-07-13cpu/x86: Move smm_lock() prototypeKyösti Mälkki
2019-06-21cpu/intel/{haswell,model_206{5,a}x}: Use MSR_CORE_THREAD_COUNT for msr at 0x35Elyes HAOUAS
2018-10-11src: Move common IA-32 MSRs to <cpu/x86/msr.h>Elyes HAOUAS
2018-10-05src: Fix MSR_PKG_CST_CONFIG_CONTROL register nameElyes HAOUAS
2018-06-14cpu/intel/haswell: Use the common intel romstage_main functionArthur Heymans
2018-06-05cpu/intel/haswell: Switch to POSTCAR_STAGEArthur Heymans
2017-07-06cpu/intel/haswell: Fix undefined behaviorRyan Salsamendi
2017-03-16cpu/intel: Fix the spacing issuesLee Leahy
2017-03-16cpu/intel: Indent with tabsLee Leahy
2016-07-23intel/haswell: Add asmlinkage for romstage_after_car()Kyösti Mälkki
2016-05-06cpu/intel/haswell: convert to using common MP and SMM initAaron Durbin
2015-10-31tree: drop last paragraph of GPL copyright headerPatrick Georgi
2015-05-21Remove address from GPLv2 headersPatrick Georgi
2014-05-05haswell: move to mp_init libraryAaron Durbin
2014-01-30coreboot: config to cache ramstage outside CBMEMAaron Durbin
2014-01-26src/cpu: Fix spelling of MTTR to MTRRPaul Menzel
2013-12-12haswell: Export functions for CPU family+model and steppingDuncan Laurie
2013-12-07haswell: VR controller configurationAaron Durbin
2013-12-07haswell: Misc power management setup and fixesDuncan Laurie
2013-12-01slippy/falco/peppy: Fix SPD GPIO initialization.Aaron Durbin
2013-11-24haswell: Configure PCH power sharing for ULTDuncan Laurie
2013-11-24haswell: calibrate 24MHz clock against BCLKAaron Durbin
2013-11-24haswell: configure c-statesAaron Durbin
2013-07-11cpu: Fix spellingMartin Roth
2013-06-03haswell: allow for disabled hyperthreadingAaron Durbin
2013-05-10Drop prototype guarding for romccStefan Reinauer
2013-05-07haswell: use asmlinkage for assembly-called funcsAaron Durbin
2013-03-21haswell: implement ramstage caching in SMM regionAaron Durbin
2013-03-21haswell: add multipurpose SMM memory regionAaron Durbin
2013-03-21haswell: support for parallel SMM relocationAaron Durbin
2013-03-19haswell: Parallel AP bringupAaron Durbin
2013-03-18haswell: add romstage_after_car() functionAaron Durbin
2013-03-18haswell: romstage: pass stack pointer and MTRRsAaron Durbin
2013-03-18haswell: unify romstage logicAaron Durbin
2013-03-18haswell: adjust CAR usageAaron Durbin
2013-03-18haswell: enable caching before SMM initializationAaron Durbin
2013-03-18haswell: move definition of CORE_THREAD_COUNT_MSRAaron Durbin
2013-03-14haswell: Add initial support for Haswell platformsAaron Durbin
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-01 05:41:32 +0000