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2024-03-21arch/x86: Fix typo for macro CPUID_FEATURE_HTTJincheng Li
Change-Id: I9b29233e75483cda6bf7723cf79632f6b04233b0 Signed-off-by: Jincheng Li <jincheng.li@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81260 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
2024-02-18arch to cpu: Add SPDX license headers to Kconfig filesMartin Roth
Change-Id: I7dd7b0b7c5fdb63fe32915b88e69313e3440b64a Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80587 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-24cpu: Rename Makefiles from .inc to .mkMartin Roth
The .inc suffix is confusing to various tools as it's not specific to Makefiles. This means that editors don't recognize the files, and don't open them with highlighting and any other specific editor functionality. This issue is also seen in the release notes generation script where Makefiles get renamed before running cloc. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I552d487978906f5ea74c3d0d85373fe5b2de3f38 Reviewed-on: https://review.coreboot.org/c/coreboot/+/80068 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
2023-12-22Revert "cpu/intel/common: Define build time physical address reserved bits"Jeremy Compostella
This reverts commit 6dff1fd7d5e419b2f947f516551dcab3f4ebe30a. BUG=b:314886709 Change-Id: Ic63c93cb15d2998e13d49a872f32d425237f528b Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79663 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-10-20cpu/intel/common: Define build time physical address reserved bitsJeremy Compostella
According the Intel Software Developer Manual, CPUID.80000008H:EAX[15:8] reports the physical-address width supported by the processor. Unfortunately, it does not necessarily reflect the physical-address space the system can actulally use as some of those bits can be reserved for internal hardware use. It is critical for coreboot to know the actual physical address size. Overestimating this size can lead to device resource overlaps due to the hardware ignoring upper reserved bits. On rex for instance, it creates some reboot hangs due to an overlap between thunderbolt and Input Output Manager (IOM) address space. As some SoCs, such as Meteor Lake, have physical address reserved bits which cannot be probed at runtime, this commit introduces `CPU_INTEL_COMMON_RESERVED_PHYS_ADDR_BITS' Kconfig to set the number of physical address reserved bits at compilation time for those SoCs. A runtime detection by hardware probing will be attempted if the value is 0 (default). BUG=b:288978352 Change-Id: I8748fa3e5bdfd339e973d562c5a201d5616f813e Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78451 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-09-29arch/x86/Kconfig: introduce RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORTFelix Held
Since also some AMD CPUs have reserved physical address bits that can't be used as normal address bits, introduce the RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT Kconfig option which gets selected by CPU_INTEL_COMMON, and use the new common option to configure if the specific SoC/CPU code implements get_reserved_phys_addr_bits or if the default of this returning 0 is used instead. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I0059e63a160e60ddee280635bba72d363deca7f7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/78073 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2023-09-29*/include/cpu: use unsigned int for number of address bitsFelix Held
The number of physical address bits and reserved address bits shouldn't ever be negative, so change the return type of cpu_phys_address_size, get_reserved_phys_addr_bits, and get_tme_keyid_bits from int to unsigned int. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I9e67db6bf0c38f743b50e7273449cc028de13a8c Reviewed-on: https://review.coreboot.org/c/coreboot/+/78072 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
2023-09-12arch/x86: Reduce max phys address size for Intel TME capable SoCsJeremy Compostella
On Intel SoCs, if TME is supported, TME key ID bits are reserved and should be subtracted from the maximum physical addresses available. BUG=288978352 TEST=Verified that DMAR ACPI table `Host Address Width` field on rex went from 45 to 41. Signed-off-by: Cliff Huang <cliff.huang@intel.com> Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Change-Id: I9504a489782ab6ef8950a8631c269ed39c63f34d Reviewed-on: https://review.coreboot.org/c/coreboot/+/77613 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-09-12cpu/intel: Move is_tme_supported() from soc/intel to cpu/intelJeremy Compostella
It makes the detection of this feature accessible without the CONFIG_SOC_INTEL_COMMON_BLOCK_CPU dependency. BUG=288978352 TEST=compilation Change-Id: I005c4953648ac9a90af23818b251efbfd2c04043 Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77697 Reviewed-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-06cpu: Add SPDX license headers to MakefilesMartin Roth
To help identify the licenses of the various files contained in the coreboot source, we've added SPDX headers to the top of all of the .c and .h files. This extends that practice to Makefiles. Any file in the coreboot project without a specific license is bound to the license of the overall coreboot project, GPL Version 2. This patch adds the GPL V2 license identifier to the top of all makefiles in the cpu directory that don't already have an SPDX license line at the top. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I3033f2a9eebc75220f7666325857b3ddd60c8f75 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68979 Reviewed-by: Tim Crawford <tcrawford@system76.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2022-11-08cpu: Include <cpu/cpu.h> instead of <arch/cpu.h>Elyes Haouas
Also sort includes. Change-Id: Ia4a3807e45777e2a596878fe09e3c80b1fd2704d Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69037 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-10-28cpu/intel/common: Fix typecasting issueSridhar Siricilla
The patch fixes the typecasting issue, that is conversion from 'int' to 'unsigned long long int'. This changes value from '0x8000 0000' to '0xFFFF FFFF 8000 0000'. During unit testing, the argument is getting changed to an unexpected number which is resulting to an exception when IA32_HWP_REQUEST MSR is updated. In this update, the MSR's reserved bits are getting updated, so this causes exception. TEST= Verified the code on the Gimble. No exception is seen after the fix. Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: I35d382c792b9df260381b7696f3bbff43d6c4dc2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68899 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-10-26cpu/intel: Clean up includesElyes Haouas
Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: Ie760711916c49d275ca49d94b9597fd24b5e7628 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68203 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2022-10-06cpu/intel/common/fsb.c: Sorte includes and add <stdint.h>Elyes Haouas
Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: I9b85836ac21da5b885a97f05e3973fb23a052fd5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68041 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2022-03-09cpu/intel/common: Add support for energy performance preference (EPP)Cliff Huang
This provides support to update energy performance preference value. BUG=b:219785001 BRANCH=firmware-brya-14505.B Signed-off-by: Cliff Huang <cliff.huang@intel.corp-partner.google.com> Change-Id: I381bca6c7746a4ae7ca32aa1b4992a6d53c8eaaa Reviewed-on: https://review.coreboot.org/c/coreboot/+/62653 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-02-05cpu/x86/lapic: Move LAPIC configuration to MP initKyösti Mälkki
Implementation for setup_lapic() did two things -- call enable_lapic() and virtual_wire_mode_init(). In PARALLEL_MP case enable_lapic() was redundant as it was already executed prior to initialize_cpu() call. For the !PARALLEL_MP case enable_lapic() is added to AP CPUs. Change-Id: I5caf94315776a499e9cf8f007251b61f51292dc5 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58387 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-02-02cpu/intel/common: Add `set_feature_ctrl_vmx_arg()`Angel Pons
Allow deciding whether to enable VMX through a function parameter. Used in a follow-up. Change-Id: I4f932de53207cd4e24cb4c67d20c60f708bfaa89 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61505 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Marvin Drees <marvin.drees@9elements.com>
2021-10-21acpigen,soc/amd,cpu/intel: rework static DWORD for CPPC tableMichael Niewöhner
Some elements in the ACPI CPPC table allow static DWORDs. Instead of using a fake register resource, use a tagged union with the two types "register" and "DWORD" and respective macros for CPPC table entries. Test: dumped SSDT before and after do not differ. Change-Id: Ib853261b5c0ea87ae2424fed188f2d1872be9a06 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57886 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-10-18cpu/intel/hyperthreading: Use initial LAPIC IDsKyösti Mälkki
For older CPU models where CPUID leaf 0xb is not supported, use initial LAPIC ID from CPUID instead of LAPIC register space to to detect if logical CPU is a hyperthreading sibling. The one in LAPIC space is more complex to read, and might not reflect CPU topology as it can be modified in XAPIC mode. Change-Id: I8c458824db1ea66948126622a3e0d0604e391e4b Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58385 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2021-10-18cpu/intel/hyperthreading: Use cpuid_get_max_func()Kyösti Mälkki
Change-Id: I4b69b1d20b5a768c269d85f0ea23f79e02391a71 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58384 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2021-10-18cpu/intel/hyperthreading: Use CPUID leaf 0xb without X2APICKyösti Mälkki
It is not a requirement to have X2APIC mode enabled to use CPUID leaf 0xb EDX to detect logical CPU is a hyperthreading sibling. Change-Id: I288f2df5a392c396f92bb6d18908df35de55915d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58383 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2021-10-13soc/amd/cezanne,soc/intel/common: rework CPPC table generationMichael Niewöhner
Make use of the newly introduced ACPI macros for CPPC table generation that currently exists of a bunch of confusing assignments of structs that only get partially filled. Test: dumped SSDT before and after do not differ. Change-Id: I844d191b1134b98e409240ede71e2751e51e2159 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57888 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Lance Zhao Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-09-17cpu: add missing arch/cpu.h includesFelix Held
Including arch/cpu.h is needed to have the declaration for cpuid_eax. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ic22aba062117e3afa818fa2fc39cb0738e6a1612 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57725 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-04-15cpu/intel/common: use lapicid apiWonkyu Kim
Use lapicid api to support both x2apic mode and apic mode BUG=None BRANCH=None TEST=boot to OS and check apic mode cat /proc/cpuinfo | grep "apicid" Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com> Change-Id: I5ca5b09ae67941adcc07dfafdfe4ba78b0f81009 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51725 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-28cpu/intel/common/fsb.c: Correct code styleFrans Hendriks
lint report warning Solve the RETURN_VOID BUG = N/A TEST = N/A Change-Id: I3b8088494049b5c3244531a4a77af4153edbdff4 Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49970 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-01-26cpu/intel/common/fsb.c: Add Broadwell CPUID modelsAngel Pons
Like Haswell, Broadwell has a "FSB" speed of 100 MHz. Add the IDs for both the traditional and ULT variants of Broadwell, because the CPU driver for Haswell already contains CPUIDs for both Broadwell types. Without this patch, Broadwell CPUs would hang when trying to print the first console log message, but only if flashconsole was not enabled. This was missed in commit f542b7bcef (cpu/intel/haswell: Add Broadwell CPUIDs and microcode) and went unnoticed until now because the tests were done with flashconsole enabled, which somehow boots properly even though the console time tracking would not work (depends on TSC). Tested on out-of-tree Acer E5-573, fixes booting without flashconsole. Change-Id: I78a1696771d4d6d2138ec432dc0d8e030f14293b Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49939 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-22cpu/intel/common: Fill cpu voltage in SMBIOS tablesPatrick Rudolph
Introduce a weak function to let the platform code provide the processor voltage in 100mV units. Implement the function on Intel platforms using the MSR_PERF_STATUS msr. On other platforms the processor voltage still reads as unknown. Tested on Intel CFL. The CPU voltage is correctly advertised. Change-Id: I31a7efcbeede50d986a1c096a4a59a316e09f825 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43904 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Jonathan Zhang <jonzhang@fb.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-10-31cpu/intel/common: correct MSR for the Nominal Performance in CPPCMichael Niewöhner
The "Nominal Performance" is not the same as the "Guaranteed Performance", but is defined as the performance a processor can deliver continously under ideal environmental conditions. According to edk2, this is the "Maximum Non-Turbo Ratio", which needs to be read from MSR_PLATFORM_INFO instead of IA32_HWP_CAPABILITIES. Correct the entry in the CPPC package. Test: dumped SSDT from Supermicro X11SSM-F and checked decompiled version Change-Id: Ic2c27fd3e14af18aa4101c0acd7a5ede15d1f3a9 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46464 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-26cpu/intel/common: implement the two missing CPPC v2 autonomous registersMichael Niewöhner
This implements the two missing registers for the CPPC Hardware Autonomous mode (HWP) to the CPPC v2 package. The right values can be determined via Intel SDM and the ACPI 6.3 spec. Test: dumped SSDT from Supermicro X11SSM-F and checked decompiled version Change-Id: I7e2f4e4ae6a0fdb57204538bd62ead97cb540e91 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46463 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Matt Delco <delco@chromium.org>
2020-10-24cpu/intel/common: rework code previously moved to common cpu codeMichael Niewöhner
Rework the code moved to common code in CB:46274. This involves simplification by using appropriate helpers for MSR and CPUID, using macros instead of plain values for MSRs and cpu features and adding documentation to the header. Change-Id: I7615fc26625c44931577216ea42f0a733b99e131 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46588 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-10-24{cpu,soc}/intel: deduplicate cpu codeMichael Niewöhner
Move a whole bunch of copy-pasta code from soc/intel/{bdw,skl,cnl,icl, tgl,ehl,jsl,adl} and cpu/intel/{hsw,model_*} to cpu/intel/common. This change just moves the code. Rework is done in CB:46588. Change-Id: Ib0cc834de8492d59c423317598e1c11847a0b1ab Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46274 Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-21cpu/intel/common: Fix regressionPatrick Rudolph
Fix the logic introduced in CB:46276 "cpu/intel/common: only lock AES-NI when supported" which needs to be negated. Change-Id: Icaf882625529842ea0aedf39147fc9a9e6081e43 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46634 Reviewed-by: Christian Walter <christian.walter@9elements.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-19cpu/intel/common: add a Kconfig to control AES-NI lockingMichael Niewöhner
Add a Kconfig to be able to disable locking of AES-NI for e.g debugging, testing, ... Change-Id: I4eaf8d7d187188ee6e78741b1ceb837c40c2c402 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46277 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-10-19cpu/intel/common: only lock AES-NI when supportedMichael Niewöhner
Add a check to only lock AES-NI when AES is supported. Change-Id: Ia7ffd5393a3e972f461ff7991b9c5bd363712361 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46276 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-10-19cpu/intel/common: rework AES-NI lockingMichael Niewöhner
Simplify the AES-NI code by using msr_set and correct the comment. Change-Id: Ib2cda433bbec0192277839c02a1862b8f41340cb Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46275 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-10-19soc/intel/skl,cpu/intel: copy AES-NI locking to common cpu codeMichael Niewöhner
Copy the AES-NI locking function to common cpu code to be able to reuse it. This change only copies the code and adds the MSR header file. Any further rework and later deduplication on the platforms code is done in the follow-up changes. Change-Id: I81ad5c0d4797b139435c57d3af0a95db94a5c15e Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46272 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-10-17cpu/intel,soc/intel: drop Kconfig for hyperthreadingMichael Niewöhner
Drop the Kconfig for hyperthreading to be always able to check at runtime if hyperthreading is supported. Having a Kconfig for this doesn't have any benefit. Change-Id: Ib7b7a437d758f7fe4a09738db1eab8189290b288 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46507 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-08-18cpu/intel/common: Use macro for access_sizeElyes HAOUAS
Change-Id: I0388ac41403ff03943c91ba19f6527e7d77e0139 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44518 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-08-06cpu/intel/common: Add `intel_ht_supported` functionAngel Pons
Change-Id: I90c0378c4042dec39c8c86c1d2339a5cbcfe78e3 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44210 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-08-03cpu/intel/common/fsb.c: add Crystal Well supportIru Cai
Without this change, there will be no console output when using a Crystal Well CPU. Tested with i5-4570R (with LGA1150 mod) on ASRock H81M-HDS. Change-Id: Id18645c52d9c4a4ea7acb602bcb39b796d9e24b9 Signed-off-by: Iru Cai <mytbk920423@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44065 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-05-28cpu/intel/common: Fix typo in commentElyes HAOUAS
Change-Id: I9ff49adebc1156d33c648efb8e9854b13c0ef859 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39696 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-05-11treewide: Remove "this file is part of" linesPatrick Georgi
Stefan thinks they don't add value. Command used: sed -i -e '/file is part of /d' $(git grep "file is part of " |egrep ":( */\*.*\*/\$|#|;#|-- | *\* )" | cut -d: -f1 |grep -v crossgcc |grep -v gcov | grep -v /elf.h |grep -v nvramtool) The exceptions are for: - crossgcc (patch file) - gcov (imported from gcc) - elf.h (imported from GNU's libc) - nvramtool (more complicated header) The removed lines are: - fmt.Fprintln(f, "/* This file is part of the coreboot project. */") -# This file is part of a set of unofficial pre-commit hooks available -/* This file is part of coreboot */ -# This file is part of msrtool. -/* This file is part of msrtool. */ - * This file is part of ncurses, designed to be appended after curses.h.in -/* This file is part of pgtblgen. */ - * This file is part of the coreboot project. - /* This file is part of the coreboot project. */ -# This file is part of the coreboot project. -# This file is part of the coreboot project. -## This file is part of the coreboot project. --- This file is part of the coreboot project. -/* This file is part of the coreboot project */ -/* This file is part of the coreboot project. */ -;## This file is part of the coreboot project. -# This file is part of the coreboot project. It originated in the - * This file is part of the coreinfo project. -## This file is part of the coreinfo project. - * This file is part of the depthcharge project. -/* This file is part of the depthcharge project. */ -/* This file is part of the ectool project. */ - * This file is part of the GNU C Library. - * This file is part of the libpayload project. -## This file is part of the libpayload project. -/* This file is part of the Linux kernel. */ -## This file is part of the superiotool project. -/* This file is part of the superiotool project */ -/* This file is part of uio_usbdebug */ Change-Id: I82d872b3b337388c93d5f5bf704e9ee9e53ab3a9 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41194 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-02acpi: Move ACPI table support out of arch/x86 (3/5)Furquan Shaikh
This change moves all ACPI table support in coreboot currently living under arch/x86 into common code to make it architecture independent. ACPI table generation is not really tied to any architecture and hence it makes sense to move this to its own directory. In order to make it easier to review, this change is being split into multiple CLs. This is change 3/5 which basically is generated by running the following command: $ git grep -iIl "arch/acpi" | xargs sed -i 's/arch\/acpi/acpi\/acpi/g' BUG=b:155428745 Change-Id: I16b1c45d954d6440fb9db1d3710063a47b582eae Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40938 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2020-04-04src/cpu: Use SPDX for GPL-2.0-only filesAngel Pons
Done with sed and God Lines. Only done for C-like code for now. Change-Id: I2adf28d805fe248d55a9514f74c38280c0ad9a78 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40049 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2020-03-23acpi: Change Processor ACPI Name (Intel only)Christian Walter
The ACPI Spec 2.0 states, that Processor declarations should be made within the ACPI namespace \_SB and not \_PR anymore. \_PR is deprecated and is removed here for Intel CPUs only. Tested on: * X11SSH (Kabylake) * CFL Platform * Asus P8Z77-V LX2 and Windows 10 FWTS does not return FAIL anymore on ACPI tests Tested-by: Angel Pons <th3fanbus@gmail.com> Change-Id: Ib101ed718f90f9056d2ecbc31b13b749ed1fc438 Signed-off-by: Christian Walter <christian.walter@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37814 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-03-15treewide: Replace uses of "Nehalem"Angel Pons
The code in coreboot is actually for the Arrandale processors, which are a MCM (Multi-Chip Module) with two different dies: - Hillel: 32nm Westmere dual-core CPU - Ironlake: 45nm northbridge with integrated graphics This has nothing to do with the older, single-die Nehalem processors. Therefore, replace the references to Nehalem with the correct names. Change-Id: I8c10a2618c519d2411211b9b8f66d24f0018f908 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38942 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-02src/: Remove g_ prefixes and _g suffixes from variablesPatrick Georgi
These were often used to distinguish CAR_GLOBAL variables that weren't directly usable. Since we're getting rid of this special case, also get rid of the marker. This change was created using coccinelle and the following script: @match@ type T; identifier old =~ "^(g_.*|.*_g)$"; @@ old @script:python global_marker@ old << match.old; new; @@ new = old if old[0:2] == "g_": new = new[2:] if new[-2:] == "_g": new = new[:-2] coccinelle.new = new @@ identifier match.old, global_marker.new; @@ - old + new @@ type T; identifier match.old, global_marker.new; @@ - T old; + T new; @@ type T; identifier match.old, global_marker.new; @@ - T old + T new = ...; There were some manual fixups: Some code still uses the global/local variable naming scheme, so keep g_* there, and some variable names weren't completely rewritten. Change-Id: I4936ff9780a0d3ed9b8b539772bc48887f8d5eed Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37358 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2019-11-29cpu/intel/common/fsb.c: Drop CAR_GLOBAL_MIGRATION supportArthur Heymans
Change-Id: I151090c8d7f670f121dc7e4cbebfd720034fde33 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37051 Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-22intel/smm: Provide common smm_relocation_paramsKyösti Mälkki
Pull in all copies of smm_relocation_params structs defined for intel platforms. Pull in all the inlined MSR accessors to the header file. Change-Id: I39c6cffee95433aea1a3c783b869eedfff094413 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34840 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-11-07Rangeley: Fix incorrect BCLKKyösti Mälkki
Not all Rangeley SKUs have a fixed 100MHz BCLK. As per BIOS Writer's Guide, BCLK is available in MSR_FSB_FREQ 0xCD[1:0]. Using fixed BCLK was causing wrong values of core frequencies in _PSS table for SKUs that do not have BCLK=100MHz. Change-Id: Id8e0244fab0283b74870950cb00a95aab2a7201f Signed-off-by: Hannah Williams <hannah.williams@dell.com> Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35348 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-28src: Remove unused '#include <cpu/cpu.h>'Elyes HAOUAS
Change-Id: Ibcb1cafe36c255b4c5bd0a4faeedb95e91048709 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36372 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-10-24cpu/intel/common: Enable GetSec leaves for Intel TXTPatrick Rudolph
Similar to VMX and SMX also enable all GetSec leaves for Intel TXT. Change-Id: I89620c2a98cfceaa785b1a798fafbf35cc99a0b2 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36092 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2019-10-01cpu/intel/common: Move intel_ht_sibling() to common folderPatrick Rudolph
Make intel_ht_sibling() available on all platforms. Will be used in MP init to only write "Core" MSRs from one thread on HyperThreading enabled platforms, to prevent race conditions and resulting #GP if MSRs are written twice or are already locked. Change-Id: I5d000b34ba4c6536dc866fbaf106b78e905e3e35 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35619 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-09-24cpu/intel/common: Fix invalid MSR accessKyösti Mälkki
Fix regression from commit ecea916 cpu/intel/common: Extend FSB detection to cover TSC MSR_EBC_FREQUENCY_ID (0x2c) was not defined for affected CPU models and rdmsr() caused reset loops. Implementations deviate from public documentation. Change to IA32_PERF_STATUS (0x198) already used in i945/udelay.c to detect FSB to TSC multiplier. Change-Id: I7a91da221920a7e7bfccb98d76115b5c89e3b52e Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35548 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-09-19cpu/intel/common: Extend FSB detection to cover TSCKyösti Mälkki
Use the same CPUID switch block to resolve the multiplier to derive TSC from FSB/BCLK frequency. Do not return 0 as base frequency. Change-Id: Ib7f1815b3fac7a610f7203720d526eac152a1648 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31340 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-19cpu/x86/lapic: Refactor timer_fsb()Kyösti Mälkki
Common apic_timer code in cpu/x86 should not depend on intel header files. Change-Id: Ib099921d4b8e561daea47219385762bb00fc4548 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34091 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-19cpu/intel/common: Add CPU_INTEL_COMMON_TIMEBASEKyösti Mälkki
To add a common tsc_freq_mhz() implementation, we need to guard againts soc-specific duplicate definitions. Change-Id: I37a34651d9e7d823ad5689d30739294358a97e31 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31341 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: David Guckian Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-10AUTHORS: Move src/cpu/intel copyrights into AUTHORS fileMartin Roth
As discussed on the mailing list and voted upon, the coreboot project is going to move the majority of copyrights out of the headers and into an AUTHORS file. This will happen a bit at a time, as we'll be unifying license headers at the same time. Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: I39f52764dc377c25953ef5dba16982a0b4637cdb Reviewed-on: https://review.coreboot.org/c/coreboot/+/35181 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Guckian Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-07-09arch/x86: Avoid HAVE_SMI_HANDLER conditional with smm-classKyösti Mälkki
Build of the entire smm-class is skipped if we have HAVE_SMI_HANDLER=n. Change-Id: I10b4300ddd18b1673c404b45fd9642488ab3186c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34125 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Lance Zhao <lance.zhao@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-01intel/fsp_rangeley: Use fixed FSB/BCLK value 100 MHzKyösti Mälkki
Prior to commit d731a24 src/cpu/intel: Set get_ia32_fsb function common value of 200 was silently used as a default for fsp_rangeley (model_406dx) in cpu/x86/lapic/apic_timer:set_timer_fsb(). After the commit, get_ia32_fsb() returns -2, eventually resulting with divide-by-zero in timer_monotonic_get(), as get_timer_fsb() returns 0. Add Rangeley CPUID model 0x4d to get_ia32_fsb() as a fix, using BCLK = 100 MHz based on the comments in northbridge/intel/fsp_rangeley/udelay.c Change-Id: I306f85dba9b1e91539fc0ecc9b2ae9d54f82be6c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33822 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2019-03-08coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX)Julius Werner
This patch is a raw application of find src/ -type f | xargs sed -i -e 's/IS_ENABLED\s*(CONFIG_/CONFIG(/g' Change-Id: I6262d6d5c23cabe23c242b4f38d446b74fe16b88 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31774 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-03-04arch/x86/acpi: Remove obsolete acpi_gen_regaddr resv fieldElyes HAOUAS
Since ACPI v2.c, this field is access_size. Currently, coreboot is using ACPI v3,so we can drop '.resv' field. Change-Id: I7b3b930861669bb05cdc8e81f6502476a0568fe0 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/31701 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-02-21cpu/intel/common: Add newline to set_feature_ctrl_lock() outputMatt DeVillier
Without newline, if IA32_FEATURE_CONTROL already locked, next console line will be concatenated. If run on a multiple CPUs, you get multiple lines concatenated. Change-Id: I5b73ae4cb045973fa3ce07f4d93fda0caadf78eb Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/31532 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-02-13cpu/intel/common: Add Nehalem for FSB detectionKyösti Mälkki
Change-Id: I194ac9eb6f03e7d3f5c96d6e6491e9ef32da9078 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/31339 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-02-13cpu/intel/common: Split get_ia32_fsb()Kyösti Mälkki
It is desireable to not have printk() inside a function body that can be used for udelay(). This avoids potential infinite recursion. Change-Id: Ie67fc2a8da8351f22794e4d36c55b887c298e8ca Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/31338 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2019-01-27src/cpu/intel: Set get_ia32_fsb function commonElyes HAOUAS
Add get_ia32_fsb returns FSB values in MHz of intel's CPUs. Also add get_ia32_fsb_x3 function. It returns round up 3 * get_ia32_fsb. Change-Id: I232bf88de7ebba6ac5865db046ce79e9b2f3ed28 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/30103 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-09cpu/intel/common: Fix generated exception if not supported VMXElyes HAOUAS
Reading rdmsr(IA32_FEATURE_CONTROL) in function set_feature_ctrl_lock() will generate an exception if the CPU do not support this MSR. Tested on pentium4 (CPUID F65). Change-Id: I72e138e3bcffe1dcd4e20739a8d07c9abfab4f80 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/30713 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2019-01-05cpu/intel/common: improve debug outputMatt DeVillier
currently, if the IA32_FEATURE_CONTROL lock bit is already set, VMX status isn't reported. Adjust debug output to provide more useful infomation on both VMX and lock bit statuses. Test: build/boot google/chell, observe useful output in cbmem log regardless of lock bit status. Change-Id: Ie50f214f7e3fcfd6c3d0d2de034a93518c0a6b46 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/30524 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2018-12-20cpu/intel/common: decouple IA32_FEATURE_CONTROL lock from set_vmx()Matt DeVillier
Newer CPUs/SoCs need to configure other features via the IA32_FEATURE_CONTROL msr, such as SGX, which cannot be done if the msr is already locked. Create separate functions for setting the vmx flag and lock bit, and rename existing function to indicate that the lock bit will be set in addition to vmx flag (per Kconfig). This will allow Skylake/Kabylake (and others?) to use the common VMX code without breaking SGX, while ensuring no change in functionality to existing platforms which current set both together. Test: build/boot each affected platform, ensure no change in functionality Change-Id: Iee772fe87306b4729ca012cef8640d3858e2cb06 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/30229 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: David Guckian Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-12-13cpuid: Add helper function for cpuid(1) functionsSubrata Banik
This patch introduces 3 helper function for cpuid(1) : 1. cpu_get_cpuid() -> to get processor id (from cpuid.eax) 2. cpu_get_feature_flags_ecx -> to get processor feature flag (from cpuid.ecx) 3. cpu_get_feature_flags_edx -> to get processor feature flag (from cpuid.edx) Above 3 helper functions are targeted to replace majority of cpuid(1) references. Change-Id: Ib96a7c79dadb1feff0b8d58aa408b355fbb3bc50 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/30123 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-11-30cpu/intel/common: Use a common acpi/cpu.asl fileArthur Heymans
Change-Id: Ifa5a3a22771ff2e0efa14fb765603fd5e0440d59 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/29894 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: David Guckian
2018-10-11src: Move common IA-32 MSRs to <cpu/x86/msr.h>Elyes HAOUAS
Use "cpu/x86/msr.h" for common IA-32 MSRs and correct IA-32 MSRs names. Change-Id: Ida7f2d608c55796abf9452f190a58802e498302d Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/28752 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-20cpu/intel/common: add function to init cppc_configMatt Delco
This change adds a method to init a cppc_config structure in a way that should ideally work across Intel processors that support EIST. Change-Id: Ib767df63d796bd1f21e36bcf575cf912e09090a1 Signed-off-by: Matt Delco <delco@chromium.org> Reviewed-on: https://review.coreboot.org/28068 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2018-01-17cpu/intel/speedstep: Fix the PNOT ACPI methodArthur Heymans
The PNOT method never notifies the CPU to update it's _CST methods due to reliance on inexisting variable (PDCx). Add a method in the speedstep ssdt generator to notify all available CPU nodes and hook this up in this file. The cpu.asl file is moved to cpu/intel/speedstep/acpi since it now relies on code generated in the speedstep ssdt generator. CPUs not using the speedstep code never included this PNOT method so this is a logical place for this code to be. Change-Id: Ie2ba5e07b401d6f7c80c31f2bfcd9ef3ac0c1ad1 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/23144 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-03-16cpu/intel: Wrap lines at 80 columnsLee Leahy
Fix the following warning detected by checkpatch.pl: WARNING: line over 80 characters TEST=Build and run on Galileo Gen2 Change-Id: I74f25da5c53bd518189ce86817d6e3385b29c3b4 Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/18850 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-12-27cpu/intel/common: Add/Use common function to set virtualizationMatt DeVillier
Migrate duplicated enable_vmx() method from multiple CPUs to common folder. Add common virtualization option for CPUs which support it. Note that this changes the default to enable virtualization on CPUs that support it. Change-Id: Ib110bed6c9f5508e3f867dcdc6f341fc50e501d1 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/17874 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins)
2016-02-14CPU/intel: Add missing license headersDamien Roth
Add missing license headers to files that have no coreboot header. Change-Id: Iaaa04b5dcbd446a2064ac68d501ae8e860486e36 Signed-off-by: Damien Roth <yves.r.roth@gmail.com> Reviewed-on: https://review.coreboot.org/13289 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2015-10-23cpu/intel: Move Power notification ASL code into `common/acpi`Paul Menzel
Commit 24813c14 (i945: Consolidate acpi/platform.asl) creates the file in the directory `src/cpu/intel/model_6dx/acpi`, although the devices can also use different Intel CPU models like, for example, `intel/model_6ex` on the Lenovo T60. Therefore move the file to the directory `src/cpu/intel/common/acpi` so that other devices, like Intel GM45 based devices, can also include it. Change-Id: I90126b66a4d70468923622a8e3aebadeafcbf96f Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/11880 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-15 19:42:15 +0000