coreboot.git - my copy of coreboot

Age	Commit message (Collapse)	Author
2019-01-08	cpu/intel/car: Prepare for C_ENVIRONMENT_BOOTBLOCK	Kyösti Mälkki
	Pass timestamps and BIST to romstage using the same signature as C_ENVIRONMENT_BOOTBLOCK will. Change-Id: Ic90da6b1b5ac3b56c69b593ba447ed8e05c8a4e2 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/30492 Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-12-24	car/non-evict/exit_car.S: Use tabs instead of white spaces	Elyes HAOUAS
	Change-Id: I53e33c54fe3ff7b6276a5bbf7defd2db33a60f0f Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/30376 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
2018-12-21	car/non-evict/cache_as_ram.S: Use tabs instead of spaces	Arthur Heymans
	Change-Id: Icc5fc9ca4aadf02bd9e63b4abc02131b6c2a79da Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/30336 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
2018-08-13	cpu/intel/car: Align the stack to 16 bytes before romstage_main	Arthur Heymans
	Change-Id: I1415c18779bc481fdec5f72f83c06a58ce6d5c39 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/26797 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-05	cpu/intel/car/non-evict: Improve a few things	Arthur Heymans
	This improve the following: - Improve readability for clearing fixed MTRR's - Compute PHYSMASK high during runtime - Cache the whole ROM_SIZE instead of XIP_ROM_SIZE Change-Id: Ifaed96b41fab973fa541de1c4f005d6f0af5254f Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/26790 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2018-06-05	cpu/intel/car/non-evict: Prepare for some POSTCAR_STAGE support	Arthur Heymans
	Prepare a common cache as ram for CPU's featuring a Non eviction mode MSR. Change-Id: I7fa3853498856050855b3b97546f4d31f66d12f7 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/26789 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>