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Make the variable override for CPU_MICROCODE_CBFS_EXTERNAL_BINS local to
the target. Otherwise, `cpu_microcode_bin +=` lines that are evaluated
after `src/cpu/Makefile.inc` still append to it.
Change-Id: If81f307afc325ff3c1e987e9483ed5e45fdc403e
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39031
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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FSP-T takes microcode pointer and location parameters, and FSP-T is
invoked before CAR is set-up and before memory is trained. So it is not
possible to modify supplied microcode pointer in runtime. Because of
that we have to hardcode the pointer in bootblock.
Also, current FSP-T on Xeons require microcode (it is not optional).
Reasons for that are currently unclear and are being investigated.
However for the present time we need to be able to add microcode at a
certain offset so FSP-T can be used.
TEST=test on OCP TiogaPass board, as well as out-of-tree CPU/board
Change-Id: I6c02601a7ac64078e556e2032baeccaf27f77da2
Signed-off-by: Andrey Petrov <anpetrov@fb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38640
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
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It is a requirement for Firmware to have Firmware Interface Table (FIT),
which contains pointers to each microcode update.
The microcode update is loaded for all logical processors before reset vector.
FSPT_UPD.MicrocodeRegionBase and FSPT_UPD.MicrocodeRegionLength are
input parameters to TempRamInit API.
If these values are 0, FSP will not attempt to update microcode.
Since Gen-4 all IA-SoC has FIT loading ucode even before cpu reset in place
hence skipping FSP-T loading ucode after CPU reset options.
Also removed unused kconfig CONFIG_CPU_MICROCODE_CBFS_LOC and
CONFIG_CPU_MICROCODE_CBFS_LEN
Change-Id: I3a406fa0e2e62e3363c2960e173dc5f5f5ca0455
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37187
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: David Guckian
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Relocatable ramstage, postcar stage and C_ENVIRONMENT_BOOTBLOCK are
now mandatory features, which this platform lacks.
Change-Id: I6d9771e97619c3775f8325daf4b8453cd51d6571
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36950
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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The MIPS architecture port has been added 5+ years ago in order to
support a Chrome OS project that ended up going nowhere. No other board
has used it since and nobody is still willing or has the expertise and
hardware to maintain it. We have decided that it has become too much of
a mainenance burden and the chance of anyone ever reviving it seems too
slim at this point. This patch eliminates all MIPS code and
MIPS-specific hacks.
Change-Id: I5e49451cd055bbab0a15dcae5f53e0172e6e2ebe
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34919
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The option to specify a binary file name was added later for platforms
that do not provide microcode updates in our blobs repository. Alas,
it wasn't visible what platforms these are. And if you specified a file
for a platform that already had one, they were all included together.
Make it visible which platforms don't provide binaries with the new con-
figs MICROCODE_BLOB_NOT_IN_BLOB_REPO, MICROCODE_BLOB_NOT_HOOKED_UP and
MICROCODE_BLOB_UNDISCLOSED. Based on that we can decide if we want to
include binaries by default or explicitly show that no files are inclu-
ded (default to CPU_MICROCODE_CBFS_NONE).
Also split CPU_MICROCODE_CBFS_GENERATE into the more explicit
CPU_MICROCODE_CBFS_DEFAULT_BINS and CPU_MICROCODE_CBFS_EXTERNAL_BINS.
And clean up the visibility of options: Don't show CBFS related options
on platforms that don't support it and don't show external file options
if the platform uses special rules for multiple files (CPU_MICROCODE_
MULTIPLE_FILES).
Change-Id: Ib403402e240d3531640a62ce93b7a93b4ef6ca5e
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/29934
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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All boards and chips that are still using LATE_CBMEM_INIT are being
removed as previously discussed.
If these boards and chips are updated to not use LATE_CBMEM_INIT, they
can be restored to the active codebase from the 4.7 branch.
chips:
soc/dmp/vortex86ex
Mainboards:
mainboard/dmp/vortex86ex
Change-Id: Iee7b6005cc2964b2346aaf4dbd9b2d2112b7403f
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/22026
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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When using microcode header and updating the header (due to a new
release of microcode during early development) the build system
doesn't detect the header change. This commit fixes this by adding
the appropriate dependency.
Change-Id: I4211a3e39f67da727ef7cddbbee6d8c4718dee4a
Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net>
Reviewed-on: https://review.coreboot.org/22307
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Because the binary repo is disabled by default, we get frequent
questions about why the build failed, relating to microcode in the
binary repository.
- Show an error saying that the file is missing instead of the typical
make error of no rule to build the file.
- Show a note encouraging users to try enabling the binary repo if it's
not enabled.
Change-Id: If4148c18cfb781ed2932bd2ae4a289b621afdebf
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/17940
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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The CPU_MICROCODE_BLOB_CBFS_LOC should only be specified for COREBOOT CBFS,
not for other CBFS.
BUG=none
BRANCH=none
TEST=Built and boot kunimitsu
Change-Id: I58bb289e6c9add2647876ef817b7920f6e7b427a
Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Reviewed-on: https://review.coreboot.org/16932
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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The build was changed to remove usage of microcode .h files when
all of the .h files were converted to binary. This is still
needed for some builds when microcode binaries aren't in the
blobs tree.
Change-Id: Ia323c90efe8aa0b8799fc5cce6197509e466a105
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: http://review.coreboot.org/12333
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
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There has been a concerted effort to clean up coreboot's microcode
handling that has included a move away from coreboot-specific
microcode file collections. As a result, the ability to specify
a single microcode file to be added to the image is of less utility
than before.
NOTE: This patch remove the built-in external microcode feature,
however the user can still specify no microcode during build and
manually add the correct microcode file(s) to the CBFS image after
the build is complete.
Change-Id: Ifea94c21e531a74953f5a0e2f489378c20ef3b5c
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/11903
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
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Having an empty microcode file makes it more easy to debug
in comparison to a not existing file in cbfs. There are some
platforms (e.g. ep80579) which support microcode updates but
not having any microcode updates yet in our tree.
These platform hang the build because `cat` is called with no
parameters.
Change-Id: I2699bde0c62ae62ca888686f8b496e845c36d970
Signed-off-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-on: http://review.coreboot.org/12109
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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Change-Id: I208b012c6b612a94b3bbc8235d5a005028be8bcc
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/11832
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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There is no other guard to prevent this from being picked up when
building for other architectures.
Change-Id: I2039a289a4dd9970d5dd0f90d43d5d5c2a6d0a0b
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/11795
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Using a copiler to compile something that's already a binary is pretty
stupid. Now that Stefan converted most microcode in blobs to a plain
binary, use the binary version.
Change-Id: Iecf1f0cdf7bbeb7a61f46a0cd984ba341af787ce
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/11607
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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There's no reason defining another class compiler which
overrides the first one. The microcode files are just
built into a binary and added to cbfs. There's no reason to
change compilers.
Change-Id: Icb47d509832e7433092a814bad020f8d66f2a299
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11596
Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Tested-by: build bot (Jenkins)
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Now that cbfstool supports file alignment, we can use the conveniently
available <filename>-align handler, and remove the need to have a
separate rule in src/Makefile.inc just for adding the microcode.
We can also get rid of the layering violation of having the
CONFIG_PLATFORM_USES_FSP1_0 symbol in a generic src/cpu/ makefile.
Note that we still have a layering violation by the use of the
CONFIG_CPU_MICROCODE_CBFS_LOC symbol, but this one is acceptable
for the time being.
Change-Id: Id2f8c15d250a0c75300d0a870284cac0c68a311b
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/11526
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Change-Id: I1535fea97c676ed6465d777f444b0a1a0e023474
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Signed-off-by: Scott Duplichan <scott@notabs.org>
Reviewed-on: http://review.coreboot.org/8694
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Prepare for FSP 1.1 integration by moving the FSP to a FSP 1.0 specific
directory. See follow-on patches for sharing of common code.
Change-Id: Ic58cb4074c65b91d119909132a012876d7ee7b74
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/9970
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Add build infrastructure and basic support code for the ImgTec Danube
SoC. This support is sufficient to run on a simulator.
BUG=chrome-os-partner:31438
TEST=none yet
Change-Id: I59e36589765bf06b075fd4850215a0ef71246bb1
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 881278d7fbb8e6803bc8f6f9e84c64640b097401
Original-Change-Id: Ia7ed7288b13085db7ff37b5ad75d978b6137f958
Original-Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/207974
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/8762
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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CPU_MICROCODE_CBFS_LOC used a non-existing dependency variable
CPU_MICROCODE_IN_CBFS. This broke alignment of microcode in CBFS.
Remoce CPU_MICROCODE_CBFS_LOC from global namespace as it is only
used with PLATFORM_FSP.
CPU_MICROCODE_CBFS_LEN was no longer used at all.
Change-Id: I0454397924d2526d97b1f095cc371ba962873c99
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/7957
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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The Exynos family and most ARM products are SoC, not just CPU.
We used to put ARM code in src/cpu to avoid polluting the code base for what was
essentially an experiment at the time. Now that it's past the experimental phase
and we're going to see more SoCs (including intel/baytrail) in coreboot.
Change-Id: I5ea1f822664244edf5f77087bc8018d7c535f81c
Reviewed-on: https://chromium-review.googlesource.com/170891
Tested-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Ronald Minnich <rminnich@chromium.org>
Commit-Queue: Hung-Te Lin <hungte@chromium.org>
(cherry picked from commit c8bb8fe0b20be37465f93c738d80e7e43033670a)
Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
Reviewed-on: http://review.coreboot.org/6739
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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Fix whitespace.
Change-Id: I9e28b819d685851a84cee6c5a71458e07d0ec808
Signed-off-by: Daniele Forsi <dforsi@gmail.com>
Reviewed-on: http://review.coreboot.org/6577
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
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Make all three coreboot stages (bootblock, romstage and ramstage) aware of the
architecture specific to that stage i.e. we will have CONFIG_ARCH variables for
each of the three stages. This allows us to have an SOC with any combination of
architectures and thus every stage can be made to run on a completely different
architecture independent of others. Thus, bootblock can have an x86 arch whereas
romstage and ramstage can have arm32 and arm64 arch respectively. These stage
specific CONFIG_ARCH_ variables enable us to select the proper set of toolchain
and compiler flags for every stage.
These options can be considered as either arch or modes eg: x86 running in
different modes or ARM having different arch types (v4, v7, v8). We have got rid
of the original CONFIG_ARCH option completely as every stage can have any
architecture of its own. Thus, almost all the components of coreboot are
identified as being part of one of the three stages (bootblock, romstage or
ramstage). The components which cannot be classified as such e.g. smm, rmodules
can have their own compiler toolset which is for now set to *_i386. Hence, all
special classes are treated in a similar way and the compiler toolset is defined
using create_class_compiler defined in Makefile.
In order to meet these requirements, changes have been made to CC, LD, OBJCOPY
and family to add CC_bootblock, CC_romstage, CC_ramstage and similarly others.
Additionally, CC_x86_32 and CC_armv7 handle all the special classes. All the
toolsets are defined using create_class_compiler.
Few additional macros have been introduced to identify the class to be used at
various points, e.g.: CC_$(class) derives the $(class) part from the name of
the stage being compiled.
We have also got rid of COREBOOT_COMPILER, COREBOOT_ASSEMBLER and COREBOOT_LINKER
as they do not make any sense for coreboot as a whole. All these attributes are
associated with each of the stages.
Change-Id: I923f3d4fb097d21071030b104c372cc138c68c7b
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: http://review.coreboot.org/5577
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@gmail.com>
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Add minimal support needed to get a bootblock capable of initialising
a serial console.
Change-Id: I50dd85544549baf9c5ea0aa3b4296972136c02a4
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/4549
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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When assembling microcode , the rule to link individual object files into
one larger file only passed the first dependency to the linker. As a results
only microcode from one object file would actually get linked. This is fixed
by replacing $^ with $+ inside the make rule.
Change-Id: I65c0565f2e03777af23e530c08d1241804ca19b1
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/4500
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
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Add support for 206ax using the Intel FSP.
The FSP is different enough to warrant its own source files
for now. It has different CAR code, micorcode, and FSP inclusion.
It may be possible to combine this code with the mrc based
solution used by the chromebooks in the future.
Change-Id: I5105631af34e9c3a804ace908c4205f073abb9b4
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/4016
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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On x86 there is a 16-byte alignment requirement for the
addresses containing the CPU microcode. The cbfs files
containing the microcode are used in memory-mapped fashion
when loading new mircocode. Therefore, the data payload's
address/offset of a cbfs file in flash dictates the resulting
alignment. Fix this by processing the CPU microcode cbfs
file separately as it uses $(CBFSTOOL) to find the proper
location within the provided rom image.
Change-Id: Ia200d62dbcf7ff1fa59598654718a0b7e178ca4c
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Signed-off-by: Gabe Black <gabeblack@chromium.org>
Reviewed-on: http://review.coreboot.org/3663
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Change-Id: I74de250c69a57109362be1b2f00c0b4aa24a64e8
Signed-off-by: Andrew Wu <arw@dmp.com.tw>
Reviewed-on: http://review.coreboot.org/3473
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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This patch adds a qemu x86 cpu chip. It has no initialization function
as this isn't needed on virtual hardware. A virtual machine can have
pretty much any CPU: qemu emulates a wide range of x86 CPUs (try 'qemu
-cpu ? for a list), also with 'qemu -cpu host' the guest will see a cpu
which is (almost) identical to the one on the host machine. So I've
added X86_VENDOR_ANY as wildcard match for the cpu_table.
Change-Id: Ib01210694b09702e41ed806f31d0033e840a863f
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Reviewed-on: http://review.coreboot.org/3344
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Initial structure of Beaglebone port
Change-Id: Ia255ab207f424dcd525990cdc0d74953e012c087
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Signed-off-by: Gabe Black <gabeblack@chromium.org>
Reviewed-on: http://review.coreboot.org/3279
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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There are some boards that do a significant amount of
work after cache-as-ram is torn down but before ramstage
is loaded. For example, using vboot to verify the ramstage
is one such operation. However, there are pieces of code
that are executed that reference global variables that
are linked in the cache-as-ram region. If those variables
are referenced after cache-as-ram is torn down then the
values observed will most likely be incorrect.
Therefore provide a Kconfig option to select cache-as-ram
migration to memory using cbmem. This option is named
CAR_MIGRATION. When enabled, the address of cache-as-ram
variables may be obtained dynamically. Additionally,
when cache-as-ram migration occurs the cache-as-ram
data region for global variables is copied into cbmem.
There are also automatic callbacks for other modules
to perform their own migration, if necessary.
Change-Id: I2e77219647c2bd2b1aa845b262be3b2543f1fcb7
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/3232
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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The ARM CPUs we know of don't have CPU microcode updates,
so don't show the selection in Kconfig.
Also simplify (and fix) the microcode selection in the Makefile
that would try to include microcode even though none is available.
Change-Id: I502d9b48d4449c1a759b5e90478ad37eef866406
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/2540
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins)
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To simplify testing ARM implementation, we need a QEMU configuration for
ARM. The qemu-armv7 provides serial output, CBFS simulation, and full
boot path (bootblock, romstage, ramstage) to verify the boot loader
functionality.
To run with QEMU:
export QEMU_AUDIO_DRV=none
qemu-system-arm -M vexpress-a9 -m 1024M -nographic -kernel build/coreboot.rom
Verified to boot until ramstage loaded successfully by QEMU v1.0.50.
Change-Id: I1f23ffaf408199811a0756236821c7e0f2a85004
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: http://review.coreboot.org/2354
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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Samsung SoC files, including Exynos5 (a Cortex-A15
implementation). Since this is an SoC we'll forego the x86-style
{north,south}bridge and cpu distinction. We may try to split some
stuff out before the final version if prudent.
Change-Id: Ie068e9dc3dd836c83d90e282b10d5202e7a4ba9b
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: http://review.coreboot.org/2005
Tested-by: build bot (Jenkins)
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This patch aims to improve the microcode in CBFS handling that was
brought by the last patches from Stefan and the Chromium team.
Choices in Kconfig
- 1) Generate microcode from tree (default)
- 2) Include external microcode file
- 3) Do not put microcode in CBFS
The idea is to give the user full control over including non-free
blobs in the final ROM image.
MICROCODE_INCLUDE_PATH Kconfig variable is eliminated. Microcode
is handled by a special class, cpu_microcode, as such:
cpu_microcode-y += microcode_file.c
MICROCODE_IN_CBFS should, in the future, be eliminated. Right now it is
needed by intel microcode updating. Once all intel cpus are converted to
cbfs updating, this variable can go away.
These files are then compiled and assembled into a binary CBFS file.
The advantage of doing it this way versus the current method is that
1) The rule is CPU-agnostic
2) Gives user more control over if and how to include microcode blobs
3) The rules for building the microcode binary are kept in
src/cpu/Makefile.inc, and thus would not clobber the other makefiles,
which are already overloaded and very difficult to navigate.
Change-Id: I38d0c9851691aa112e93031860e94895857ebb76
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/1245
Tested-by: build bot (Jenkins)
Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
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It's not a real northbridge, so I just move it into the mainboard directory for
now (until we maybe have a qemu-q35 image some day?)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5316 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4864 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4846 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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- Whitespace fixes, remove trailing whitespace, use TABs for identation
(except in Kconfig "help" lines, which start with one TAB and two spaces
as per Linux kernel style)
- Kconfig: Standardize on 'bool' (not 'boolean').
- s/lar/cbfs/ in one Kconfig help string.
- Reword various Kconfig menu entries for a more usable and consistent menu.
- Fix incorrect comment of NO_RUN in devices/Kconfig.
- superio/serverengines/Kconfig: Incorrect config name.
- superio/Makefile.inc: s/serverengine/serverengines/.
- superio/intel/Kconfig: s/SUPERIO_FINTEK_I3100/SUPERIO_INTEL_I3100/.
- mainboard/via/vt8454c/Kconfig: Fix copy-paste error in help string.
- mainboard/via/epia-n/Kconfig: Fix "bool" menu text.
- console/Kconfig: Don't mention defaults in the menu string, kconfig
already displays them anyway.
- Kill "Drivers" menu for now, it only confuses users as long as it's emtpy.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4567 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4537 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Works on Kontron, qemu, and serengeti.
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
tested on abuild only.
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4534 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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