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NOTE: UART base for SMM continues to be broken, as it does not use
the address resource allocator has assigned.
Change-Id: I79f2ca8427a33a3c719adfe277c24dab79a33ef3
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5235
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Change-Id: I6d56648e56f2177e1d5332497321e718df18300c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5234
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Do not pull in console hw-specific prototypes everywhere
with console.h as those are not needed for higher levels.
Move prototypes for UARTs next to other consoles.
Change-Id: Icbc9cd3e5bdfdab85d7dccd7c3827bba35248fb8
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5232
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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We should not have pc80/ includes in console/.
Change-Id: Id7da732b1ea094be01f45f9dbb49142f4e78f095
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5157
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Struct dbgp_pipe would not be suitable for use with xHCI.
Just use an index, it is easy to setup in Kconfig if our
future debug setup has separate pipes for console
output and debugging/traceings.
Change-Id: Icbbd28f03113b208016f80217ab801d598d443a8
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5227
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
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clang complains otherwise.
Change-Id: I2ac98d7147ecd3d7064f17f8c9d214d44baedf97
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/4717
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
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The RTC functionality provided by the include is specific to x86, but
is not used in these files.
Change-Id: I82d0dfdb6e8b67bc81291a7a5d63ced91e095772
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/4586
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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Needs printk and is not a console core function.
Change-Id: Id90a363eca133af4469663c1e8b504baa70471e0
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5155
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
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Read from USB endpoint_in 8 bytes at a time, the maximum what
EHCI debug port capability has to offer.
Change-Id: I3d012d758a24b24f894e587b301f620933331407
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/4700
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
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Also prepare this console for use in romstage.
Change-Id: I26a4d4b5db1e44a261396a21bb0f0574d72aa86d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5136
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Gerd Hoffmann <kraxel@redhat.com>
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Also relocate and split header files, there is some interest
for EHCI debug support without PCI.
Change-Id: Ibe91730eb72dfe0634fb38bdd184043495e2fb08
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5129
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
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Remove sprintf as if you can't easily use snprintf then you probably
have buffer overflow.
Change-Id: Ic4570e099a52d743aca938a2bfadb95981adc503
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4280
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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snprintf is a safe variant of sprintf. To avoid buffer overflows
we shouldn't use sprintf at all. But for now let's start by
implementing snprintf in first place.
Change-Id: Ic17d94b8cd91b72f66b84b0589a06b8abef5e5c9
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4278
Tested-by: build bot (Jenkins)
Reviewed-by: Peter Stuge <peter@stuge.se>
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If there is trouble setting up usbdebug, it may be useful to delay
usbdebug init to run in ramstage.
Change-Id: I31de5a06d3f9ce19f71c422cce0c8cb0fd50f396
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/4488
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@google.com>
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Instead of having global variables put them on the stack.
Change-Id: I462e3b245612ff2dfb077da1cbcc5ac88f8b8e48
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4288
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins)
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It was suggested to eliminate the lock for sprintf. One way to do it is
to make the fake tx_byte into a closure. This patch allows it.
It's a bit tricky since we need to preserve compatibility with romcc.
Change-Id: I877ef0cef54dcbb0589fe858c485f76f3dd27ece
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4287
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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No need to show the choice of USB port or controller in case of older
hardware where location for usbdebug was hardwired.
Change-Id: Ia186bf2c6ed60be2834cf6fd0a1965c8bf81ed4d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/4290
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
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This was used by Ron 13ys ago and was never used again
ever since.
Change-Id: I8ae8a570d67fa0b34b17c9e3709845687f73c724
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/59320
Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
Tested-by: Stefan Reinauer <reinauer@chromium.org>
Commit-Queue: Stefan Reinauer <reinauer@chromium.org>
Reviewed-on: http://review.coreboot.org/4256
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins)
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Do not directly check the return value of get_option, but instead compare
the returned value against a CB_CMOS_ error code, or against CB_SUCCESS.
Change-Id: I2fa7761d13ebb5e9b4606076991a43f18ae370ad
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/4266
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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One of the most common hangs during coreboot execution
is during ramstage device init steps. Currently there
are a set of (somewhat misleading) post codes during this
phase which give some indication as to where execution
stopped, but it provides no information on what device
was actually being initialized at that point.
This uses the new CMOS "extra" log banks to store the
encoded device path of the device that is about to be
touched by coreboot. This way if the system hangs when
talking to the device there will be some indication where
to investigate next.
interrupted boot with reset button and
gathered the eventlog after several test runs:
26 | 2013-06-10 10:32:48 | System boot | 120
27 | 2013-06-10 10:32:48 | Last post code in previous boot | 0x75 | Device Initialize
28 | 2013-06-10 10:32:48 | Extra info from previous boot | PCI | 00:16.0
29 | 2013-06-10 10:32:48 | Reset Button
30 | 2013-06-10 10:32:48 | System Reset
Change-Id: I6045bd4c384358b8a4e464eb03ccad639283939c
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/58105
Reviewed-on: http://review.coreboot.org/4230
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
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This can be used to indicate sub-state within a POST
code range which can assist in debugging BIOS hangs.
For example this can be used to indicate which device
is about to be initialized so if the system hangs
while talking to that device it can be identified.
Change-Id: I2f8155155f09fe9e242ebb7204f0b5cba3a1fa1e
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/58104
Reviewed-on: http://review.coreboot.org/4229
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
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The CMOS post code storage mechanism does back-to-back
CMOS reads and writes that may be interleaved during
CPU bringup, leading to corruption of the log or of other
parts of CMOS.
Change-Id: I704813cc917a659fe034b71c2ff9eb9b80f7c949
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/58102
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4227
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Add a function to display memory locations in the console
logfile.
Change-Id: Iddb8d2e7a24357075f32c2fdf7916ae7a732247d
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/4013
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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The main usbdebug file lib/usbdebug.c was removed from romstage
build with commit f8bf5a10 but the chipset-specific parts were not,
leading to unresolved symbol errors for AMD platforms.
Add a silent Kconfig variable USBDEBUG_IN_ROMSTAGE for convenient
use of this feature.
Change-Id: I0cd3fccf2612cf08497aa5c3750c89bf43ff69be
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3983
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
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As boards without EARLY_CBMEM_INIT do not initialize CBMEM in romstage,
and have no CAR migration, these features are available for ramstage only.
Change-Id: Ic3f77ccdedd4e71ba693619c02c9b98b328a0882
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3970
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
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This reverts commit de1fe7f655c549e8dce5b34218221890fa5ccc34.
While things appeared to work, there were actually invalid references
to CAR storage after CAR was torn down on boards without
EARLY_CBMEM_INIT. It was discussed use of CAR_GLOBAL should be
restricted to boards that handle CAR migration properly.
Change-Id: I9969d2ea79c334a7f95a0dbb7c78065720e6ccae
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3968
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
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Assume EARLY_CBMEM_INIT=y everywhere and remove option from Kconfig.
If romstage does not make the cbmem_initialize() call, features like
COLLECT_TIMESTAMPS and early CBMEM_CONSOLE will execute during
romstage, but that data will get lost as no CAR migration is
executed.
Change-Id: I5615645ed0f5fd78fbc372cf5c3da71a3134dd85
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3917
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
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These features depend on CAR_GLOBAL region, which is not available
when romstage is built with ROMCC. Exclude these from romstage, keep
them available for ramstage.
A follow-up patch will fix the dependencies and allows enabling these
features in menuconfig.
Change-Id: I9de5ad41ea733655a3fbdc734646f818e39cc471
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3919
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@google.com>
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Some development kits with USB 2.0 HS OTG have an USB hub instead
of being directly connected to the USB host/device controller.
Send the necessary initialisation sequence, using HUB CLASS requests
of PORT_POWER and PORT_RESET to enable a pre-selected port number
where a device supporting debug descriptor is located.
This also adds the Kconfig option for BeagleBone.
Change-Id: I7a5d0ba0962a9ca06bf3196232ed4a03bdfb2b06
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3925
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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Nowadays, chipsets or boards do not only have one USB port with the
capabilities of a debug port but several ones. Some of these ports are
easier accessible than others, so making them configurable is also necessary.
This change adds infrastructure to switch between EHCI controllers,
but does not implement it for any chipset.
Change-Id: I079643870104fbc64091a54e1bfd56ad24422c9f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3438
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
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On AMD platforms, setting of USBDEBUG_DEFAULT_PORT=0 tries to scan
all physical ports one after other in incrementing order. To avoid
possible problems with other USB devices, one can select the port
number here and bypass the scan.
Intel platforms can communicate with usbdebug dongle on one
physical port only, and this option makes no difference there.
Change-Id: I45be6cc3aa91b74650eda2d444c9fcad39d58897
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3872
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
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Add Kconfig option SQUELCH_EARLY_SMP and have it enabled by
default.
Console drivers have unpredictable results if multiple threads
attempt to share same resources without spinlock. Serial UARTs
have not had huge problems, only distorted output, but those
relying on cache-as-ram (CBMEM and usbdebug) may require this.
Change-Id: I7f406fdea7b6dc6a341c4da2fab56f7b7ff568b4
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3854
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@google.com>
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Add option to log changes in USB 2.0 EHCI debug port connection.
For romstage move usbdebug as the last initialised console so one
actually can see these messages.
Init order of consoles in ramstage is undetermined and unchanged.
Change-Id: I3aceec8a93064bd952886839569e9f5beb6c5720
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3387
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
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This change brings back the possibility to disable console
output while in romstage, like before commit d2f45c65.
For some platforms (AMD multi-socket) USBDEBUG and/or CBMEM
CONSOLE do not work correctly for romstage due the way
cache-as-ram is set up, but might already work for ramstage.
Change-Id: Id8d830e02a18129af419d3b5860866acf315d531
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3846
Tested-by: build bot (Jenkins)
Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@google.com>
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There are other uses for EHCI debug port besides console, so move
EHCI relocation code from console to lib.
Change-Id: I95cddd31be529351d9ec68f14782cc3cbe08c617
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3626
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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Move ehci_debug_info allocation from console to lib, as console code
was only built for ramstage.
Implement dbgp_ehci_info() to return the EHCI context. Alread alias this
as dbgp_console_input() and _output() to return the console stream context
later on.
Change-Id: Id6cc07d62953f0466df61eeb159e22b0e3287d4e
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3625
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Output to usbdebug console needs to be disabled until hardware is
initialized and while EHCI BAR is relocated. Add separate field
ehci_info to point to back to EHCI context when hardware is ready
to transfer data.
Change-Id: If7d441b561819ab8ae23ed9f3f320f7742ed231e
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3624
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
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Otherwise we have to worry about hand off between bootblock and
romstage. Too much complexity
Change-Id: I89bf8a229dba7e1330accadf9a732d831ebc4827
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Signed-off-by: Gabe Black <gabeblack@chromium.org>
Reviewed-on: http://review.coreboot.org/3694
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Change-Id: I6b28bb95c7decbe3eed33b5b5a029bee48bbe403
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Signed-off-by: Gabe Black <gabeblack@chromium.org>
Reviewed-on: http://review.coreboot.org/3691
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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It might be that you want an early console in romstage before RAM is up, but
you can't or don't want to support the console all the way back in the
bootblock. By making the console in those two different environments
configurable seperately that becomes possible.
On the 5250 console output as early as the bootblock works, but on the 5420 it
only starts working in the ROM stage after clocks have been initialized.
Change-Id: I68ae3fcb4d828fa8a328a30001c23c81a4423bb8
Signed-off-by: Gabe Black <gabeblack@chromium.org>
Reviewed-on: http://review.coreboot.org/3671
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Change-Id: I1fef27c4a16ee4358ace8014a8d6e9fa92c4f790
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/3728
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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All the additional work that needs to be done in EHCI BAR relocation
is independent of the hardware platform and was functionally identical
in all the copies removed.
When USBDEBUG is not selected, PCI EHCI controllers use standard
pci_dev_read_resources() call.
With USBDEBUG selected, PCI EHCI controller's device_operations
.read_resources is replaced with pci_ehci_read_resources() call,
which in turn will replace the device_operations .set_resources call.
The replacement for .set_resources reconfigures usbdebug driver side,
and calls the original .set_resources to configure hardware side.
Change-Id: I8e136a5da4efedf60b6dd7068c0488153efaaf8e
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3412
Reviewed-by: Aaron Durbin <adurbin@google.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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If EARLY_CONSOLE is not selected, the PCI function for EHCI
host controller must be configured in ramstage instead.
Change-Id: I20f7569f79484c744bc413450bfa139052f3580f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3383
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
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Change-Id: Ie0507475f33d029d6e8ce59f138e0e7da5156d4f
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Reviewed-on: http://review.coreboot.org/3339
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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The qemu debugcon port returns 0xe9 on reads in case the device is
present. Use that for detection and write console output to the
port only in case the device is actually present.
Change-Id: I41aabcf11845d24004e4f795dfd799822fd14646
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Reviewed-on: http://review.coreboot.org/3338
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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Change-Id: Ibcc0a94638c022a76cd3c2e3387af6e1ab757ccb
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Reviewed-on: http://review.coreboot.org/3337
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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Add support for sending debug output to an I/O port.
It can be used together with QEMU's isa-debugcon driver to log the
coreboot output to a file. The port is configurable and defaults
to 0x402 which has established as the de facto standard. For example,
SeaBIOS+OVMF [1] use that one too.
[1] http://www.linux-kvm.org/page/OVMF
Open Virtual Machine Firmware
Change-Id: I0803f7fc70030242f80003e25c9449c37d71975e
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Reviewed-on: http://review.coreboot.org/3331
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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binary
This option has never had much if any use. It solved a problem over 10
years ago that resulted from an argument over the value or lack thereof
of including all the debug strings in a coreboot image. The answer is
in: it's a good idea to maintain the capability to print all messages,
for many reasons.
This option is also misleading people, as in a recent discussion, to
believe that log messges are controlled at build time in a way they are
not. For the record, from this day forward, we can print messages at all
log levels and the default log level is set at boot time, as directed by
DEFAULT_CONSOLE_LOGLEVEL. You can set the default to 0 at build time and
if you are having trouble override it in CMOS and get more messages.
Besides, a quick glance shows it's always set to max (9 in this case) in
the very few cases (1) in which it is set.
Change-Id: I60c4cdaf4dcd318b841a6d6c70546417c5626f21
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: http://review.coreboot.org/3188
Tested-by: build bot (Jenkins)
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Change-Id: Ie497e4c8da05001ffe67c4a541bd24aa859ac0e2
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/2987
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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It makes much more sense to use CONFIG_USE_OPTION_TABLE instead
of CONFIG_HAVE_CMOS_DEFAULT. As we want to read the used
debug_level from our CMOS. This change makes it possible to
change log_debug via nvramtool and make use of the new
value after a reboot/poweroff.
CONFIG_HAVE_CMOS_DEFAULT does have an other meaning
Change-Id: I438dd01a2b4171dba2b73f2001511c71f4317725
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-on: http://review.coreboot.org/2381
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
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There are assumptions that COLLECT_TIMESTAMPS and CONSOLE_CBMEM
rely on EARLY_CBMEM_INIT. This isn't true in the face of
DYNAMIC_CBMEM as it provides the same properties as EARLY_CBMEM_INIT.
Therefore, allow one to select COLLECT_TIMESTAMPS and CONSOLE_CBMEM
when DYNAMIC_CBMEM is selected. Lastly, don't hard code the cbmem
implementation when COLLECT_TIMESTAMPS is selected.
Change-Id: I053ebb385ad54a90a202da9d70b9d87ecc963656
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/2895
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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On ARMv7 the console code can also be built into
the bootblock. Currently building the ARM targets
on a reasonably fast machine can fail, because
console.bootblock.o is attempted to build before
build.h is created. This patch adds a specific
rule for the bootblock variant of console.c, to
match the other variants so that the race condition
goes away.
Change-Id: I52e4242c66a02f011ef26b854aa50c2606a1f81f
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/2873
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
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This eliminates the use of do_div() in favor of using libgcc
functions.
This was tested by building and booting on Google Snow (ARMv7)
and Qemu (x86). printk()s which use division in vtxprintf() look good.
Change-Id: Icad001d84a3c05bfbf77098f3d644816280b4a4d
Signed-off-by: Gabe Black <gabeblack@chromium.org>
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/2606
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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In the file `COPYING` in the coreboot repository and upstream [1]
just one space is used.
The following command was used to convert all files.
$ git grep -l 'MA 02' | xargs sed -i 's/MA 02/MA 02/'
[1] http://www.gnu.org/licenses/gpl-2.0.txt
Change-Id: Ic956dab2820a9e2ccb7841cab66966ba168f305f
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/2490
Tested-by: build bot (Jenkins)
Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
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Just a tiny mistake, but it made the console driver assume that
CMOS data isn't available.
Change-Id: I4e6f53e9ed59024de7b09333f82f0ce3235ef8f6
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/2323
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Peter Stuge <peter@stuge.se>
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Revise console source file dependency (especially for EARLY_CONSOLE) and
interpret printk/console_init according to EARLY_CONSOLE setting (no-ops if
EARLY_CONSOLE is not defined).
Verified to boot on x86/qemu and armv7/snow. Disabling EARLY_CONSOLE correctly
stops romstage messages on x86/qemu (armv7/snow needs more changes to work).
Change-Id: Idbbd3a26bc1135c9d3ae282aad486961fb60e0ea
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: http://review.coreboot.org/2300
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: David Hendricks <dhendrix@chromium.org>
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Early console should always be allowed to be turned on / off (for generating
production and debug versions), and should not be enforced by "select" Kconfig
rule.
A new "DEFAULT_EARLY_CONSOLE" is introduced for devices to select if they
prefer early console output by default.
Verified Kconfig value on qemu/x86 (default y by CACHE_AS_RAM), snow/x86
(default y by EXYNOS5 config), and intel/jarrell (default n).
Change-Id: Ib1cc76d4ec115a302b95e7317224f1a40d1ab035
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: http://review.coreboot.org/2307
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: David Hendricks <dhendrix@chromium.org>
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The console drivers (especially serial drivers) in Kconfig were named in
different styles. This change will rename configuration names to a better naming
style.
- EARLY_CONSOLE:
Enable output in pre-ram stage. (Renamed from EARLY_SERIAL_CONSOLE
because it also supports non-serial)
- CONSOLE_SERIAL:
Enable serial output console, from one of the serial drivers. (Renamed
from SERIAL_CONSOLE because other non-serial drivers are named as
CONSOLE_XXX like CONSOLE_CBMEM)
- CONSOLE_SERIAL_UART:
Device-specific UART driver. (Renamed from
CONSOLE_SERIAL_NONSTANDARD_MEM because it may be not memory-mapped)
- HAVE_UART_SPECIAL:
A dependency for CONSOLE_SERIAL_UART.
Verified to boot on x86/qemu and armv7/snow, and still seeing console
messages in romstage for both platforms.
Change-Id: I4bea3c8fea05bbb7d78df6bc22f82414ac66f973
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: http://review.coreboot.org/2299
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
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Remove duplicated / testing code and share more driver for bootblock, romstage
and ramstage.
The __PRE_RAM__ is now also defined in bootblock build stage, since bootblock is
executed before RAM is initialized.
Change-Id: I4f5469b1545631eee1cf9f2f5df93cbe3a58268b
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: http://review.coreboot.org/2282
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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The do_div code has a nice optimization in it when it is called with
constants. The current highly generalized use of it defeats those
optimizations and causes trouble on ARM, resulting in a complex and
buggy code path.
Since we only need to print in bases 8, 10, and 16, do a minor
restructuring of the code so that we call do_div with constants.
If you need base 2, print in base 16 and do it in your head. :-)
This fixes an ongoing problem with ARM, will not harm X86, and will
help PPC should we ever want to support it again.
Plus, I don't have to ever try to understand the div64 assembly and where
it's going wrong :-)
Change-Id: I6a480011916eb0834e05c5bb10909d83330fe797
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: http://review.coreboot.org/2235
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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During the ARM port, disabling serial console became broken.
This patch fixes it.
Change-Id: I40460596073918a08c19bb9c991cada341cca940
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/2136
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
|
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This patch makes pre-RAM serial init more generic, particularly for
platforms which do not necessarily need cache-as-RAM in order to use
the serial console and do not have a standard 8250 serial port.
This adds a Kconfig variable to set romstage-* for very early serial
console init. The current method assumes that cache-as-RAM should
enable this, so to maintain compatibility selecting CACHE_AS_RAM will
also select EARLY_SERIAL_CONSOLE.
The UART code structure needs some rework, but the use of ROMCC,
romstage, and then ramstage makes things complex.
uart.h now includes all .h files for all uarts. All 2 of them.
This is actually a simplifying change.
Change-Id: I089e7af633c227baf3c06c685f005e9d0e4b38ce
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: http://review.coreboot.org/2086
Tested-by: build bot (Jenkins)
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Change-Id: I5b412678bb8993633b3a610315d298cb20c705f3
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/2011
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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Because they use outb instructions, they are bound to fail
on non-PC80 systems like ARM.
Change-Id: I679ac6c0964c06c369cc90556529bb6f629d56f9
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1974
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Tested-by: build bot (Jenkins)
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get_option() is used to get a config option (debug loglevel) from
CMOS. However, not all machines have CMOS, so define a dummy inline
function that will return an error code so the caller (console_init())
will use the default loglevel.
Change-Id: I6adf371d79164178f40a83f7608289a6a7673357
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/1962
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
|
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The use of ramstage.a required the build system to handle some
object files in a special way, which were put in the drivers
class.
These object files didn't provide any symbols that were used
directly (but only via linker magic), and so the linker never
considered them for inclusion.
With ramstage.a gone, we can drop this special class, too.
Change-Id: I6f1369e08d7d12266b506a5597c3a139c5c41a55
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/1872
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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This will omit the mc1468181rtc header if it is not needed. Currently
it contains a lot of inlined functions which depend on architecture-
specific IO.
Change-Id: I4ef1bc1362c159e0c780c3eade01af04f029f949
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/1916
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins)
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This adds more configurability to POST codes. The current assumption
is that POST codes should be written to an IO port (e.g. LPC) if POST
codes are enabled. This changes the assumption so that POST codes can
be written to the serial console without being written to an IO port.
This enables POST codes by default using "default y" to avoid
changing current behavior.
Change-Id: I3db91c358ccb1557096983c4d07f70b2e872c4b3
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/1685
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
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Read out the post code from the previous boot and
log it if the code is not one of the expected values.
Test:
1) interrupt the boot of the system, this is easiest
with warm reset button when servo is attached
2) check the event log with mosys
65 | 2012-09-09 12:32:11 | Last post code in previous boot | 0x9d
Change-Id: Id418f4c0cf005a3e97b8c63de67cb9a09bc57384
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/1744
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
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This will use 3 bytes of CMOS to keep track of the POST
code for the current boot while also leaving a record of
the previous boot.
The active bank is switched early in the bootblock.
Test:
1) clear cmos
2) reboot
3) use "mosys nvram dump" to verify that the first byte
contains 0x80 and the second byte contains 0xF8
4) powerd_suspend and then resume
5) use "mosys nvram dump" to verify that the first byte
contains 0x81 and the second byte contains 0xFD
Change-Id: I1ee6bb2dac053018f3042ab5a0b26c435dbfd151
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/1743
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
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Some mainboards have really nice capabilities for posting, beyond
simple POST cards. Further, some can not use a POST card. This
change defines a weak symbol (mainboard_post) that can be overridden
by a real mainboard_post function.
If, for example, you'd like to do something fancy before the payload starts,
you can add this to mainboard.c:
void mainboard_post(u8 value)
{
switch(value){
case POST_TIME_TO_PARTY: some_fancy_lights();
break;
}
}
Maybe the post function should be an entry in the device. We're beginning to over-use
weak symbols.
BUG=None
TEST=Build and boot a google chromebook. Observe that it still works. Use it to drive
some pretty lights.
Change-Id: I3512d2ec34a66c747287191851c3f68b6a7cc1b2
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/1397
Tested-by: build bot (Jenkins)
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EHCI debug allows to send message with 8 bytes length, but
we're only sending one byte in each transaction. Buffer up
to 8 bytes to speed up debug output.
Change-Id: I9dbb406833c4966c3afbd610e1b13a8fa3d62f39
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/1357
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.huber@secunet.com>
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This is used by the SPI driver and ELOG.
It requires SMM TSEG and a _heap/_eheap region defined in the
linker script. The first time malloc is called in SMM the
start and end pointers to the heap region will be relocated
for the TSEG region.
Enable SPI flash and ELOG in SMM and successfully
allocate memory. The allocated addresses are verified
to be sure they are within the TSEG heap region:
smm.elf:00014000 B _eheap
smm.elf:00010000 B _heap
TSEG base is 0xad000000
Memory allocated in ELOG:
ELOG: MEM @0xad018030
Change-Id: I5cca38e4888d597cbbfcd9983cd6a7ae3600c2a3
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/1312
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
|
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The oxpcie ramstage code calls uartmem_init after the PCI memory
allocation, but hte function was static and didn't have a prototype.
Change-Id: Iabc1a3d248aeaed29aaaa22504defac97c572326
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/1285
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
|
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The SPI drivers from u-boot make heavy use of %zu/%zd (size_t/ssize_t).
Implement this in our printk implementation so we get useful output.
Change-Id: I91798ff4f28b9c3cd4db204c7ec503596d247dcd
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1043
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
|
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Traditionally coreboot's SMM handler runs in ASEG (0xa0000),
"behind" the graphics memory. This approach has two issues:
- It limits the possible size of the SMM handler (and the
number of CPUs supported in a system)
- It's not considered a supported path anymore in newer CPUs.
Change-Id: I9f2877e46873ab2ea8f1157ead4bc644a50be19e
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Acked-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/842
Reviewed-by: Peter Stuge <peter@stuge.se>
Tested-by: build bot (Jenkins)
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- cash -> Cache
- make the new size of the cbmem console buffer the default
Change-Id: Ia906077257e93622ad56bc54a42f8184ade78b29
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/726
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
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The appropriate Makefiles are modified to include the required
source code in compilation.
Change-Id: I91842b1ba0f89d611d3249b63c020a2713a9124f
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: http://review.coreboot.org/722
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
|
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The new added code is compiled in when the CBMEM_CONSOLE config
flag is enabled.
Change-Id: Ifd1f492ce6321412a014333babbc5b3f14635988
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: http://review.coreboot.org/721
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
|
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The CBMEM console driver saves console output in a CBMEM area, which
then is made available to Linux applications for perusing.
There are some system limitations which need to be worked around
to achieve this goal:
- some console traffic is generated before DRAM is initialized,
leave alone CBMEM initialized.
- after the RAM based stage starts, a lot of traffic is generated
before CBMEM is initialized.
As a result, the console log lives in three different places -
the bottom of the cache as RAM space, the CBMEM buffer (where it
is expected to be) and a static buffer used early in the RAM
stage.
When execution starts (in the cache as RAM mode), the console
buffer is allocated at the bottom of the cache as RAM memory
address range. Once DRAM is initialized, the CBMEM structure is
initialized, and then the console buffer contents are copied from
the bottom of the cache as RAM space into the CBMEM area right
before the cache as RAM mode is disabled. The
src/lib/cbmem_console.c:cbmemc_reinit() takes care of the
copying.
At this point the cache as RAM memory is about to be disabled,
but the ROM stage is still going generating console output. To
make sure this output is not lost, cbmemc_reinit() saves the new
buffer address at a fixed location (0x600 was chosen for this),
and the actual "printing" function checks to see if the RAM is
already initialized (the stack is in RAM), and if so, gets the
console buffer pointer from this location instead of using the
cache as RAM address.
When the RAM stage starts, a static buffer is used to store the
console output, as the CBMEM buffer location is not known. Then,
when CBMEM is reinitialized, cbmemc_reinit() again takes care of
the copying.
In case the allocated buffers are not large enough, the excessive
data is dropped, and the copying routine adds some text to the
output buffer to indicate that there has been data lost and how
many characters were dropped.
Change-Id: I8c126e31db6cb2141f7f4f97c5047f39a8db44fc
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: http://review.coreboot.org/719
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
|
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Some experiments have demonstrated that total amount of text
generated by coreboot console when BIOS_SPEW level is enabled
exceeds 40KB.
Console output generated before DRAM is initialized can exceed
2KB. This patch introduces the new configuration option and
assigns adequate default values to cache based and DRAM based
console buffers.
BUG=chrome-os-partner:4200
TEST=manual
. run the following commands in the root directory
cp config.stumpy .config
make menuconfig
. enable the new option (Console->Send console output to a CBMEM buffer)
. save the configuration
Observe the following settings added to the config:
+CONFIG_CONSOLE_CBMEM=y
+CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0xae00
+CONFIG_CONSOLE_CAR_BUFFER_SIZE=0xc00
Change-Id: I209603f516244ae136631e6281ba21ebc6fb1710
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://gerrit-int.chromium.org/5855
Tested-by: Vadim Bendebury <vbendeb@google.com>
Reviewed-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/718
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
|
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Because it's included everywhere anyways.
Change-Id: I99a9e6edac08df57c50ef3a706fdbd395cad0abc
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/691
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
|
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Also mark the corresponding lint test stable.
Change-Id: Ib7c9ed88c5254bf56e68c01cdbd5ab91cd7bfc2f
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/772
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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trivial change in src/console/Kconfig
Change-Id: Ib6bb4ccfabaa3af18b48a23a51a576b872d807a8
Signed-off-by: Vikram Narayanan <vikram186@gmail.com>
Reviewed-on: http://review.coreboot.org/505
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
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Change-Id: Ib91889a374515d36a2b12b53aeb12b6ea6e22732
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/364
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
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- move enable_usbdebug() declaration to usbdebug.h
- reinitialize debug driver in ramstage, as copying the data
structure from romstage doesn't work right now. This way of copying
data from romstage to ramstage is really board/cpu specific, and is
likely to break often. So don't do it.
Change-Id: I394678ded6679c1803e29eb691b926182bdcab68
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/355
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Add a configuration option POST_PORT which defaults to 0x80 and
can be redefined by boards which have integrated POST displays
on another I/O port. Change post.c to output POST codes to this
port instead of 0x80 hardcoded.
Change-Id: I8f8e820f8c75641b35e7249bf622b63a3604b9f3
Signed-off-by: Christoph Grenz <christophg+cb@grenz-bonn.de>
Reviewed-on: http://review.coreboot.org/221
Tested-by: build bot (Jenkins)
Reviewed-by: Rudolf Marek <r.marek@assembler.cz>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
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Add information about memory mapped/io mapped base addresses.
and fix up libpayload to use the same structures
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Change-Id: I5f7b5eda6063261b9acb7a46310172d4a5471dfb
Reviewed-on: http://review.coreboot.org/261
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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The compiler is forced to emmit special functions on every
entry/exit of the function. Add a compile time option
to support it. Function entries will be printed in
the console. The CONFIG_TRACE has more documentation.
Patch for userspace tools will follow.
Change-Id: I2cbeb3f104892b034c8756f86ed05bf71187c3f3
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Reviewed-on: http://review.coreboot.org/178
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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The previous code does a full flush of the uart after every character.
Unfortunately, this can cause transmission delays on some serial
ports.
This patch changes the code so that it does a flush at the end of
every printk instead of at the end of every character. This reduces
the time it takes to transmit serial messages (up to 9% on my Asrock
e350m1 board). It also makes the transmission time more consistent
which is important when performing timing tests via serial
transmissions.
Change-Id: I6b28488b905da68c6d68d7c517cc743cde567d70
Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
Reviewed-on: http://review.coreboot.org/90
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Rudolf Marek <r.marek@assembler.cz>
Reviewed-by: Sven Schnelle <svens@stackframe.org>
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example.
This newer version reflects the recent changes to further simplify the console
code and partly gets rid of some hacks in the previous version.
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6544 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6539 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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and baudrate, not hardcoded in addition to that.
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6538 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6536 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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initialization functions.
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6531 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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to unify calls to *_enable_usbdebug()
* rename *_enable_usbdebug() to enable_usbdebug()
* move enable_usbdebug() to generic romstage console init code
and drop it from the individual romstage.c files.
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6513 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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because that is what it does.
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Acked-by: Patrick Georgi <patrick.georgi@secunet.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6311 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Stefan Reinauer <stepan@coreboot.org>
Acked-by: Stefan Reinauer <stepan@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6244 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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coreboot made it kind of complicated to print a character on serial. Not quite
as complicated as UEFI, but too much for a good design. Fix it.
Signed-off-by: Stefan Reinauer <stepan@coreboot.org>
Acked-by: Stefan Reinauer <stepan@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6191 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Acked-by: Patrick Georgi <patrick@georgi-clan.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6113 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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