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2017-12-11commonlib: Add timestamp codes for AGESAMartin Roth
BUG=b:70432544 TEST=Build & boot kahlee. Look at timestamps. Change-Id: I3bf691a0fb1f5c09e7b6c9965c9e506393ec31f6 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/22797 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-12-07boardid: Add helpers to read sku_id strapping into coreboot tablesJulius Werner
On many recent Chrome OS boards, the desire to unite more configurations under the same image has led to the need of a "SKU ID" that identifies different configurations of the same board (e.g. with certain optional components stuffed or not stuffed, or replaced with a comparable component). This is markedly different from the existing "board ID", because that is reserved to count "revisions" -- changes made to the same configuration over time during the development process. This patch adds support to have a mainboard define this SKU ID and pass it through the coreboot table like we already have for board IDs. Change-Id: I8aabffe8e1003b0d6fb70d689ae513ca4b46aeda Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/22696 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-12-07boardid: Minor clean up and standardizationJulius Werner
Merge the different coreboot table strapping ID structures into one because they're really just all the same, and I want to add more. Make the signature of the board_id() function return a uint32_t because that's also what goes in the coreboot table. Add a printk to the generic code handling strapping IDs in ramstage so that not every individual mainboard implementation needs its own print. (In turn, remove one such print from fsp1_1 code because it's in the way of my next patch.) Change-Id: Ib9563edf07b623a586a4dc168fe357564c5e68b5 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/22741 Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-12-02riscv: Remove config string supportJonathan Neuschäfer
The code dealing with the old config string isn't needed anymore, because the config string has been deprecated in favor of OpenFirmware-derived devicetrees. Change-Id: I71398fb4861dbaf7eefc6e6f222bb7159798fafa Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/22594 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2017-11-04commonlib/helpers.h: Include stddef.hJonathan Neuschäfer
The definition of offsetof() uses size_t, which is declared in stddef.h, according to POSIX. Include stddef.h directly to avoid relying on implicit inclusion. Change-Id: I221be02c332de55c9fcf7d86673709ed43dd5c3c Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/22230 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maximilian Schander <coreboot@mimoja.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-10-29LB_TAGS: change the value of CB_TAG_MAC_ADDRS to 0x33Ronald G. Minnich
When building the Go version of cbmem I found that LB_TAG_MAC_ADDRS has the same value as LB_TAG_VERSION_TIMESTAMP. I am guessing that this tag was little used. In any event, move it forward to 0x33. Change-Id: I038ad68e787e56903a2ed9cb530809a55821c313 Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: https://review.coreboot.org/22218 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-10-18arch/x86: restore forwarding table on resume for EARLY_EBDA_INITAaron Durbin
In commit c06a3f72 (arch/x86: initialize EBDA in S3 and S0/S5 path) the BDA and EBDA are wiped in the resume path. However, the coreboot table forwarding entry wasn't taken into account so that was wiped which resulted in cbmem not working on the resume path. Fix this by stashing the forwarding table in cbmem and restoring it on the resume path. Change-Id: I142503535a78635fbb1c698fc7d032c1a2921813 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/22078 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-09-27commonlib: Consistently spell *romstage* without spacePaul Menzel
Make the spelling of *romstage* consistent without a space. Choose this version, as *ramstage* is also spelled without a space, since commit a7d924412a (timestamps: You can never have enough of them!). Fixes: 0db924d74c (cbmem: print timestamp names) Change-Id: I1b1c10393f0afb9a20ac916ff9dc140a51c716cd Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: https://review.coreboot.org/21706 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-09-13sb/intel/bd82x6x: Add time-stamp around ME DRAM updateNathaniel Roach
Add a timestamp before and after waiting for the ME to acknowledge the DRAM being ready. This allows easier debugging during use of me_cleaner and/or alternate ME images. Change-Id: Ie228e12a75d373b4f406b3595e1fb1aab41aa5df Signed-off-by: Nathaniel Roach <nroach44@gmail.com> Reviewed-on: https://review.coreboot.org/21465 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-07-13Rename __attribute__((packed)) --> __packedStefan Reinauer
Also unify __attribute__ ((..)) to __attribute__((..)) and handle ((__packed__)) like ((packed)) Change-Id: Ie60a51c3fa92b5009724a5b7c2932e361bf3490c Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/15921 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-01riscv: Update the gcc built-in macro __riscv__wxjstz
The architecture is determined by __riscv__ in the LZ4_copy8 function (located in src / commonlib / lz4_wrapper.c). __riscv exists in gcc7.1.1. But __riscv__ does not exist. Change-Id: I38fd41da9afd76c254f0c3d6984579c3790e5792 Signed-off-by: XiangWang <wxjstz@126.com> Reviewed-on: https://review.coreboot.org/20125 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Andrew Waterman <aswaterman@gmail.com> Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
2017-06-27commonlib/storage: Zero extend MMC capacityLee Leahy
Fix CID 1376472 detected by coverity. Zero extend the capacity instead of sign extending it. TEST=Build and run on reef Change-Id: I6aac422fb1dacb75e0cc44a94ff1f467ce9f529e Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/20392 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2017-06-20arch/x86/ebda: Change memcpy() to endian wrappersRyan Salsamendi
Change memcpy()s and memset()s to endian.h wrappers for consistency and safety. Add zero_n() wrapper to safely clear memory. Change-Id: If155d82608c81992f05eae4d2223de6f506e98c5 Signed-off-by: Ryan Salsamendi <rsalsamendi@hotmail.com> Reviewed-on: https://review.coreboot.org/20240 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-06-20commonlib/storage: Fix MMC buildLee Leahy
Add missing includes to build mmc.c. TEST=Build and run on Galileo Gen2 Change-Id: I0dea597272e5ece97843704a159aa546a8d77ff0 Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/20271 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-05-12commonlib: Move drivers/storage into commonlib/storageLee Leahy
Move drivers/storage into commonlib/storage to enable access by libpayload and indirectly by payloads. * Remove SD/MMC specific include files from include/device * Remove files from drivers/storage * Add SD/MMC specific include files to commonlib/include * Add files to commonlib/storage * Fix header file references * Add subdir entry in commonlib/Makefile.inc to build the SD/MMC driver * Add Kconfig source for commonlib/storage * Rename *DEVICE* to *COMMONLIB* * Rename *DRIVERS_STORAGE* to *COMMONLIB_STORAGE* TEST=Build and run on Galileo Gen2 Change-Id: I4339e4378491db9a0da1f2dc34e1906a5ba31ad6 Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/19672 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-04-28commonlib: Add ID for STORAGE_DATALee Leahy
TEST=Build and run on Reef Change-Id: I2f04a01e5e266422e3ef0d90541dc9d39471260c Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/19301 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-04-25include: Add xmalloc, xzmalloc and dma routinesLee Leahy
Add a Kconfig value to indicate coreboot builds. Add prototypes and definitions for: * dma_coherent * dma_malloc * xmalloc * xzmalloc Move prototype for memset into stdlib.h from string.h to eliminate build breaks. TEST=Build and test on Galileo Gen2 Change-Id: Ib2eb2ca143b0538bdd1863e628af4c1948bc0f8c Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/19207 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-04-24commonlib/helpers: Add helper macro for member_sizeFurquan Shaikh
member_size macro provides the size of a structure member. Change-Id: I53e9c9bf70b3ebed0d15e8258111b17e50667a74 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/19384 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-04-24commonlib: add input and output buffer helpersAaron Durbin
Introduce ibuf and obuf structures for helping manage memory buffers. The ibuf, an input buffer, can be read from and the obuf, an output buffer, can be written to. Helper functions are provided for serializing values in different endian formats. This library is provided to for common buffer management routines such that the same code doesn't have to re-written in different and less consistent forms. BUG=b:36598499 Change-Id: I5247237f68b658906ec6916bbbb286d57d6df5ee Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/19062 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
2017-03-13commonlib: Wrap lines at 80 columnsLee Leahy
Fix the following warning detected by checkpatch.pl: TEST=Build and run on Galileo Gen2 Change-Id: I811763c6de57dfdf5456579f63e83dca29d37d61 Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/18751 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-03-10commonlib: Remove space after *Lee Leahy
Fix the following error detected by checkpatch.pl: ERROR: "foo * bar" should be "foo *bar" TEST=Build and run on Galileo Gen2 Change-Id: If68dfa2b49c61d574f35192f94d1a6642069fa7f Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/18752 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2017-03-10commonlib: Fix issues with { } and elseLee Leahy
Fix the following errors and warning detected by checkpatch.pl: ERROR: open brace '{' following struct go on the same line ERROR: else should follow close brace '}' WARNING: else is not generally useful after a break or return False positives are detected for the following checkpatch.pl error. ERROR: that open brace { should be on the previous line These false positives are in cbfs.c for two function definitions. TEST=Build and run Galileo Gen2 Change-Id: Ic679ff3a2e1cfc0ed52073c20165e05bf21d76f3 Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/18750 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2017-03-10commonlib: Wrap lines at 80 columnsLee Leahy
Fix the following error detected by checkpatch.pl: ERROR: code indent should use tabs where possible TEST=Build and run on Galileo Gen2 Change-Id: I3a44a02d4cd1be6b2bb2f52fc832e673a580e562 Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/18749 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2017-03-10commonlib: Fix spacing issuesLee Leahy
Fix the following errors and warnings detected by checkpatch.pl: ERROR: space required after that ',' (ctx:VxV) ERROR: space required after that ';' (ctx:VxV) ERROR: space prohibited after that open parenthesis '(' ERROR: space prohibited before that close parenthesis ')' WARNING: please, no spaces at the start of a line WARNING: please, no space before tabs TEST=Build and run on Galileo Gen2 Change-Id: I54877f60eb5fdf3f6d8729711c55ff5a284d22cf Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/18748 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2017-02-22commonlib/fsp.h: include sys/types.h for ssize_tJonathan Neuschäfer
This file reportedly didn't compile on SUSE Linux with gcc 4.3.4: [...] > HOSTCC cbfstool/fsp_relocate.o > In file included from coreboot/src/commonlib/fsp_relocate.c:18: > coreboot/src/commonlib/include/commonlib/fsp.h:26: error: > expected '=', ',', ';', 'asm' or '__attribute__' before > 'fsp_component_relocate' [...] According to POSIX-2008[1], sys/types.h defines ssize_t, so include it. This should not break coreboot code (as opposed to utils code), as we have a sys/types.h in src/include. [1]: http://pubs.opengroup.org/onlinepubs/9699919799/basedefs/sys_types.h.html Change-Id: Id3694dc76c41d800ba09183e4b039b0719ac3d93 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/18417 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Martin Roth <martinroth@google.com>
2016-12-08buildsystem: Drop explicit (k)config.h includesKyösti Mälkki
We have kconfig.h auto-included and it pulls config.h too. Change-Id: I665a0a168b0d4d3b8f3a27203827b542769988da Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17655 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-12-08commonlib: provide incoherent region deviceAaron Durbin
The MRC cache uses an incoherent mechanism for updating the cache contents in that it assumes memory mapped boot device access for checking against latest data for update. However, it uses another driver for updating the underlying storage area. In order to aid in moving the MRC cache over to using region_devices for updates provide an implementation of a region_device which performs reads and writes to different region_devices so that different drivers can be used transparently. BUG=chrome-os-partner:56151 Change-Id: I30e858245c30cbccd6313aff5ebecd3fd98d7302 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/17716 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-12-07lib: Add time stamp when starting to finalize chipsPaul Menzel
Add the new time stamps *finalize chips* to track, when the method `dev_finalize_chips()` is called, so that the real time of `write_tables()` is known. Change-Id: I65ca0ec4c07c2eaa14982989cb206d23d8a2293f Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: https://review.coreboot.org/17725 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-12-02soc/intel/common: Add suppport for Extended VBTAbhay Kumar
With addition of new features in VBT its size got increased more than 6k and was unable to pass using mailbox 4 hence pass using mailbox 3 to kernel. BRANCH=none BUG=chrome-os-partner:60026 TEST=firmware screen and Chrome OS screen should come up. Change-Id: I359cf9bc402881161c9623cada689496716e04a5 Signed-off-by: Abhay Kumar <abhay.kumar@intel.com> Reviewed-on: https://review.coreboot.org/17585 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-30soc/intel/common: Add save/restore for variable MRC dataAndrey Petrov
Piggy-back on existing MRC cache infrastructure to store variable MRC data. Only one set of data can be valid at given point of time. Currently this magically happens because region alignment is forced to 0x1000 and region itself is of the same size. This needs to be somehow programmatically enforced. Change-Id: I8a660d356ca760b8ff9907396fb9b34cb16cf1db Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/17320 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-19commonlib/include: remove NEED_VB20_INTERNALSAaron Durbin
vboot_handoff.c is the only place that needs the vb2 internals. Provide it in the one place it is actually required instead of pulling in the headers unnecessarily in common code. There is, however, still a need to get the vb2 hashing types for a function declaration. Change-Id: I038fda68b1cd05fa2e66135158e5e2d18567563a Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/17475 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-11-14commonlib: Add new cbmem id for EC_HOSTEVENTFurquan Shaikh
BUG=chrome-os-partner:59352 BRANCH=None TEST=Compiles successfully. Change-Id: Ife167bff484ef552bd6cd2e61fdc8291ad6a8acf Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/17392 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-12riscv: start to use the configstring functionsRonald G. Minnich
These functions will allow us to remove hardcodes, as long as we can verify the qemu and lowrisc targets implement the configstring correctly. Hence, for the most part, we'll start with mainboard changes first. Define a new config variable, CONFIG_RISCV_CONFIGSTRING, which has a default value that works on all existing systems but which can be changed as needed for a new SOC or mainboard. Change-Id: I7dd3f553d3e61f1c49752fb04402b134fdfdf979 Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: https://review.coreboot.org/17256 Tested-by: build bot (Jenkins) Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
2016-11-12riscv: bring in the configstring parsing functions from UCBRonald G. Minnich
I've tested this with commits to come later. This is from the lowrisc bbl distribution, 87588c4, with fixes so it builds. Change-Id: I87893638872259c94d6972e1971578b633155e7e Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: https://review.coreboot.org/17255 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-11-12drivers/intel/fsp2_0: track end of firmware notificationsAaron Durbin
The end of firmware notification is currently not being tracked so it's hard to get good data on how long it takes. Update the code to provide timestamp data as well as post codes. BUG=chrome-os-partner:56656 Change-Id: I74c1043f2e72d9d85b23a99b8253ac465f62a7f2 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/17373 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
2016-09-07commonlib: move DIV_ROUND macros from nvidia/tegraArthur Heymans
DIV_ROUND_CLOSEST and DIV_ROUND_UP are useful macros for other architectures. This patch moves them from soc/nvidia/tegra/types.h to commonlib/include/commonlib/helpers.h . Change-Id: I54521d9b197934cef8e352f9a5c4823015d85f01 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/16415 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-02commonlib: update fsp_relocate to make it compatible with UEFI 2.6Brandon Breitenstein
UEFI 2.6 spec casts the return of FFS_FILE2_SIZE to a UINT32 which cannot be read using read_le32(&returnval). Add in a cast in order to safeguard for any non x86 architecture that may use this relocate. The proper change will be to get the UEFI header files changed to not cast this return value. Change-Id: Ie1b50d99576ac42a0413204bbd599bab9f01828e Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com> Reviewed-on: https://review.coreboot.org/16309 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-08-27cbfs: Add "struct" file type and associated helpersJulius Werner
This patch adds functionality to compile a C data structure into a raw binary file, add it to CBFS and allow coreboot to load it at runtime. This is useful in all cases where we need to be able to have several larger data sets available in an image, but will only require a small subset of them at boot (a classic example would be DRAM parameters) or only require it in certain boot modes. This allows us to load less data from flash and increase boot speed compared to solutions that compile all data sets into a stage. Each structure has to be defined in a separate .c file which contains no functions and only a single global variable. The data type must be serialization safe (composed of only fixed-width types, paying attention to padding). It must be added to CBFS in a Makefile with the 'struct' file processor. Change-Id: Iab65c0b6ebea235089f741eaa8098743e54d6ccc Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/16272 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-08-27commonlib: cbfs: Add CBFS attribute supportJulius Werner
This patch adds support for the CBFS attributes that were already introduced in cbfstool and libpayload. I'm only copy&pasting the header definitions needed for this once more. Really, we should be unifying the definitions (and possibly part of the code) from cbfstool with commonlib, but apparently that hadn't been done when this feature was introduced and I don't really have time to do it cleanly now. Also add a function to extract info from the compression attribute, which can then be used to run cbfs_load_and_decompress() on the file. Change-Id: I7b6463597757122cfe84f006c946a1658bb3acc6 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/16271 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-08-15commonlib/region: allow empty mmap()/munmap() in region_device_opsAaron Durbin
Instead of assuming all region_devices have an mmap() and munmap() implementation fail those calls when one isn't provided. BUG=chrome-os-partner:56151 Change-Id: I9b03e084aa604d52d6b5bab47c0bf99d9fbcd422 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/16190 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-08-08commonlib/region: make buffer argument const for writeatAaron Durbin
The buffer for writeat() should be marked as const as the contents won't be manipulated within the call. BUG=chrome-os-partner:55932 Change-Id: I968570c1cf80f918a07b97af625a56f11b5889c1 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/16084 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-07-20cbmem: share additional time stamps IDsAntonello Dettori
Split the additional time stamps concerning depthcharge from the cbmem utility sourcecode and move them into commonlib/timestamp_serialized.h header. Change-Id: Ic23c3bc12eac246336b2ba7c7c39eb2673897d5a Signed-off-by: Antonello Dettori <dev@dettori.io> Reviewed-on: https://review.coreboot.org/15725 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-07-19drivers/intel/fsp2_0: load and relocate FSPS in cbmemAaron Durbin
The FSPS component loading was just loading to any memory address listed in the header. That could be anywhere in the address space including ramstage itself -- let alone corrupting the OS memory on S3 resume. Remedy this by loading and relocating FSPS into cbmem. The UEFI 2.4 header files include path are selected to provide the types necessary for FSP relocation. BUG=chrome-os-partner:52679 Change-Id: Iaba103190731fc229566a3b0231cf967522040db Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15742 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-by: John Zhao <john.zhao@intel.com>
2016-07-19commonlib: fix 'AFTER CAR' spacing to align with othersAaron Durbin
The cbmem string for 'AFTER CAR' didn't have the proper spacing so when that entry is added to cbmem it results in a misaligned log entry with the others. Change-Id: If940e85b7dc5fb8372d7e2845270dadad67ab3a0 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15735 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-06-24region: Add writeat and eraseat supportAntonello Dettori
Implement writeat and eraseat support into the region_device_ops struct. Change-Id: Iac2cf32e523d2f19ee9e5feefe1fba8c68982f3d Signed-off-by: Antonello Dettori <dev@dettori.io> Reviewed-on: https://review.coreboot.org/15318 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-06-24src/commonlib/lz4_wrapper: Correct inline asm for unaligned 64-bit copyBenjamin Barenblat
Rewrite inline assembly for ARMv7+ to correctly annotate inputs and outputs. On ARM GCC 6.1.1, this causes assembly output to change from the incorrect @ r0 is allocated to hold dst and x0 @ r1 is allocated to hold src and x1 ldr r0, [r1] @ clobbers dst! ldr r1, [r1, #4] str r0, [r0] str r1, [r0, #4] to the correct @ r0 is allocated to hold dst @ r1 is allocated to hold src and x1 @ r3 is allocated to hold x0 ldr r3, [r1] ldr r1, [r1, #4] str r3, [r0] str r1, [r0, #4] Also modify checkpatch.pl to ignore spaces before opening brackets when used in inline assembly. Change-Id: I255995f5e0a7b1a95375258755a93972c51d79b8 Signed-off-by: Benjamin Barenblat <bbaren@google.com> Reviewed-on: https://review.coreboot.org/15216 Tested-by: build bot (Jenkins) Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-06-21commonlib/region: Add helpers for dynamic initialization of region devFurquan Shaikh
This allows initialization of runtime region devices and xlate region devices where all parameters cannot be statically determined. BUG=chrome-os-partner:54563 Change-Id: Ia6e1b695fed3bbfa08598d1593e650fc1465d41f Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/15267 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-21commonlib/region: Rename XLATE region device init macroFurquan Shaikh
This makes the name consistent with other region device init macros. Change-Id: I248894ba6c85326b615dcb71e8f498bc8be50911 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/15277 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-05-31commonlib/lz4: Avoid unaligned memory access on RISC-VJonathan Neuschäfer
From the User-Level ISA Specification v2.0: "We do not mandate atomicity for misaligned accesses so simple implementations can just use a machine trap and software handler to handle misaligned accesses." (— http://riscv.org/specifications/) Spike traps on unaligned accesses. Change-Id: Ia57786916f4076cc08513f4e331c2deec9cfa785 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/14983 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-05-11cbfstool/fsp: Rename fsp1_1_relocateFurquan Shaikh
FSP 2.0 uses the same relocate logic as FSP 1.1. Thus, rename fsp1_1_relocate to more generic fsp_component_relocate that can be used by cbfstool to relocate either FSP 1.1 or FSP 2.0 components. Allow FSP1.1 driver to still call fsp1_1_relocate which acts as a wrapper for fsp_component_relocate. Change-Id: I14a6efde4d86a340663422aff5ee82175362d1b0 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/14749 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2016-05-09coreboot_tables: Extend serial port descriptionLee Leahy
Extend the serial port description to include the input clock frequency and a payload specific value. Without the input frequency it is impossible for the payload to compute the baud-rate divisor without making an assumption about the frequency. This breaks down when the UART is able to support multiple input clock frequencies. Add the UART_PCI_ADDR Kconfig value to specify the unique PCI device being used as the console UART. Specify this value as zero when the UART is not on the PCI bus. Otherwise specify the device using bus, device and function along with setting the valid bit. Currently the only payload to consume these new fields is the EDK-II CorebootPayloadPkg. Testing on Galileo: * Edit the src/mainboard/intel/galileo/Makefile.inc file: * Add "select ADD_FSP_PDAT_FILE" * Add "select ADD_FSP_RAW_BIN" * Add "select ADD_RMU_FILE" * Place the FSP.bin file in the location specified by CONFIG_FSP_FILE * Place the pdat.bin files in the location specified by CONFIG_FSP_PDAT_FILE * Place the rmu.bin file in the location specified by CONFIG_RMU_FILE * Build EDK2 CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc to generate UEFIPAYLOAD.fd * Testing is successful when CorebootPayloadPkg is able to properly initialize the serial port without using built-in values. Change-Id: Id4b4455bbf9583f0d66c315d38c493a81fd852a8 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/14609 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-04-25ensure correct byte ordering for cbfs segment listGeorge Trudeau
Decode each cbfs_payload_segment into native byte order during segments iteration. Note : List ordering has been changed, segments are now always inserted at the end. cbfs_serialized.h PAYLOAD_SEGMENT definitions have been changed to their standard order (big-endian). Change-Id: Icb3c6a7da2d253685a3bc157bc7f5a51183c9652 Signed-off-by: George Trudeau <george.trudeau@usherbrooke.ca> Reviewed-on: https://review.coreboot.org/14294 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-03-23arch/x86: introduce postcar stage/phaseAaron Durbin
Certain chipsets don't have a memory-mapped boot media so their code execution for stages prior to DRAM initialization is backed by SRAM or cache-as-ram. The postcar stage/phase handles the cache-as-ram situation where in order to tear down cache-as-ram one needs to be executing out of a backing store that isn't transient. By current definition, cache-as-ram is volatile and tearing it down leads to its contents disappearing. Therefore provide a shim layer, postcar, that's loaded into memory and executed which does 2 things: 1. Tears down cache-as-ram with a chipset helper function. 2. Loads and runs ramstage. Because those 2 things are executed out of ram there's no issue of the code's backing store while executing the code that tears down cache-as-ram. The current implementation makes no assumption regarding cacheability of the DRAM itself. If the chipset code wishes to cache DRAM for loading of the postcar stage/phase then it's also up to the chipset to handle any coherency issues pertaining to cache-as-ram destruction. Change-Id: Ia58efdadd0b48f20cfe7de2f49ab462306c3a19b Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/14140 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-03-05lz4_wrapper: Use __asm__ rather than asm.Vladimir Serbinenko
__asm__ is more robust to compilation flags. Change-Id: Ic7ca6e38ddd439dcfc4a62ef272ecea62416b4be Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: https://review.coreboot.org/13905 Tested-by: build bot (Jenkins) Reviewed-by: Julius Werner <jwerner@chromium.org>
2016-02-25cbfs: Fix compiler error for gcc versions < 4.6Werner Zeh
The missing braces for access to a union member cause an error on gcc versions < 4.6. Change-Id: I7de14a6d89219f5376f4f969adecfe8014a5a9d8 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/13776 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-02-24commonlib/lz4_wrapper: Use correct casts to ensure valid calculationsPaul Menzel
Commit 09f2921b (cbfs: Add LZ4 in-place decompression support for pre-RAM stages) breaks building cbfstool with gcc (Debian 4.9.2-10) 4.9.2 in Debian 8.3 (jessie) with a 32-bit user space. It works fine in a 64-bit user space. ``` /home/joey/src/coreboot/src/commonlib/lz4_wrapper.c:164:18: note: in expansion of macro 'MIN' size_t size = MIN((uint32_t)b.size, dst + dstn - out); ^ /home/joey/src/coreboot/src/commonlib/include/commonlib/helpers.h:29:35: error: signed and unsigned type in conditional expression [-Werror=sign-compare] #define MIN(a,b) ((a) < (b) ? (a) : (b)) ^ ``` The problem is arithmetic on void*, so explicitly cast to the wanted types as suggested by user *redi* in #gcc@irc.freenode.net. Change-Id: I85bee25a69c432ef8bb934add7fd2e2e31f03662 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: https://review.coreboot.org/13771 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-02-22cbfs: Add LZ4 in-place decompression support for pre-RAM stagesJulius Werner
This patch ports the LZ4 decompression code that debuted in libpayload last year to coreboot for use in CBFS stages (upgrading the base algorithm to LZ4's dev branch to access the new in-place decompression checks). This is especially useful for pre-RAM stages in constrained SRAM-based systems, which previously could not be compressed due to the size requirements of the LZMA scratchpad and bounce buffer. The LZ4 algorithm offers a very lean decompressor function and in-place decompression support to achieve roughly the same boot speed gains (trading compression ratio for decompression time) with nearly no memory overhead. For now we only activate it for the stages that had previously not been compressed at all on non-XIP (read: non-x86) boards. In the future we may also consider replacing LZMA completely for certain boards, since which algorithm wins out on boot speed depends on board-specific parameters (architecture, processor speed, SPI transfer rate, etc.). BRANCH=None BUG=None TEST=Built and booted Oak, Jerry, Nyan and Falco. Measured boot time on Oak to be about ~20ms faster (cutting load times for affected stages almost in half). Change-Id: Iec256c0e6d585d1b69985461939884a54e3ab900 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/13638 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-02-19x86: add coreboot table entry for TSC infoAaron Durbin
The 8254 (Programmable Interrupt Timer) is becoming optional on x86 platforms -- either from saving power or not including it at all. To allow a payload to still use a TSC without doing calibration provide the TSC frequency information in the coreboot tables. That data is provided by code/logic already employed by platform. If tsc_freq_mhz() returns 0 or CONFIG_TSC_CONSTANT_RATE is not selected the coreboot table record isn't created. BUG=chrome-os-partner:50214 BRANCH=glados TEST=With all subsequent patches confirmed TSC is picked up in libpayload. Change-Id: Iaeadb85c2648587debcf55f4fa5351d0c287e971 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/13670 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
2016-02-02commonlib: move uefi includes out of commonlib includesStefan Reinauer
... and move them into the code using them, instead. Change-Id: I2391234797ad00da8038dda198eadf0b0fcaedb2 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/13526 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-27chromeos: Add timestamps to measure VPD read timesJulius Werner
This patch adds three timestamps to coreboot and the cbmem utility that track the time required to read in the Chrome OS Vital Product Data (VPD) blocks (RO and RW). It's useful to account for these like all other large flash accesses, since their size is variable. BRANCH=None BUG=None TEST=Booted Oak, found my weird 100ms gap at the start of ramstage properly accounted for. Change-Id: I2024ed4f7d5e5ae81df9ab5293547cb5a10ff5e0 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: b97288b5ac67ada56e2ee7b181b28341d54b7234 Original-Change-Id: Ie69c1a4ddb6bd3f1094b3880201d53f1b5373aef Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/322831 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: https://review.coreboot.org/13139 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-18commonlib/: Add missing license headersMartin Roth
These files are original to coreboot and get the standard coreboot GPL header. Change-Id: I19565b0d2424a6f37a95ab4d7b16742d23122d1e Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12919 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-01-06commonlib: Add function to hash contents of a CBFS region.Aaron Durbin
Provide a common routine to hash the contents of a cbfs region. The cbfs region is hashed in the following order: 1. potential cbfs header at offset 0 2. potential cbfs header retlative offset at cbfs size - 4 3. For each file the metadata of the file. 4. For each non-empty file the data of the file. BUG=chrome-os-partner:48412 BUG=chromium:445938 BRANCH=None TEST=Utilized in chromeos cros_bundle_firmware as well as at runtime during vboot verification on glados. Change-Id: Ie1e5db5b8a80d9465e88d3f69f5367d887bdf73f Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/12786 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins)
2016-01-06commonlib/cbfs: Add type ids for empty filesPatrick Georgi
We will soon need to handle empty files. Change-Id: Ia72a4bff7d9bb36f6a6648c3dd89e86593d80761 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/12785 Tested-by: build bot (Jenkins)
2016-01-06commonlib: Prepare code to be included in cbfstool builds.Aaron Durbin
Some of the files need to be adjusted so that they can be used both in cbfstool as well as coreboot proper. For coreboot, add a <sys/types.h> file such that proper types can be included from both the tools and coreboot. The other chanes are to accomodate stricter checking in cbfstool. BUG=chrome-os-partner:48412 BUG=chromium:445938 BRANCH=None TEST=Built on glados including tools. Booted. Change-Id: I771c6675c64b8837f775427721dd3300a8fa1bc0 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/12784 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-01-06commonlib: Add common cbfs parsing logic to coreboot and cbfstool.Aaron Durbin
To continue sharing more code between the tools and coreboot proper provide cbfs parsing logic in commonlib. A cbfs_for_each_file() function was added to allow one to act on each file found within a cbfs. cbfs_locate() was updated to use that logic. BUG=chrome-os-partner:48412 BUG=chromium:445938 BRANCH=None TEST=Utilized and booted on glados. Change-Id: I1f23841583e78dc3686f106de9eafe1adbef8c9f Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/12783 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-01-06commonlib: Add function to compute relative offsets from two region_devices.Aaron Durbin
Provide a helper function which returns the relative offset between 2 region_devices that have a parent-child child relationship. BUG=chrome-os-partner:48412 BUG=chromium:445938 BRANCH=None TEST=Utilized and booted on glados. Change-Id: Ie0041b33e73a6601748f1289e98b6f1f8756eb11 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/12782 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-12-10cbfs/vboot: remove firmware component supportAaron Durbin
The Chrome OS verified boot path supported multiple CBFS instances in the boot media as well as stand-alone assets sitting in each vboot RW slot. Remove the support for the stand-alone assets and always use CBFS accesses as the way to retrieve data. This is implemented by adding a cbfs_locator object which is queried for locating the current CBFS. Additionally, it is also signalled prior to when a program is about to be loaded by coreboot for the subsequent stage/payload. This provides the same opportunity as previous for vboot to hook in and perform its logic. BUG=chromium:445938 BRANCH=None TEST=Built and ran on glados. CQ-DEPEND=CL:307121,CL:31691,CL:31690 Change-Id: I6a3a15feb6edd355d6ec252c36b6f7885b383099 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/12689 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-23commonlib/cbmem_id.h: Add CBMEM_ID_HOB_POINTER to CBMEM_ID_TO_NAME_TABLEBen Gardner
fsp-based platforms have this ID, so give it a name. Change-Id: Idce4dbb60b7b3581e18046e66183a7c91b17abd7 Signed-off-by: Ben Gardner <gardner.ben@gmail.com> Reviewed-on: http://review.coreboot.org/12485 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-20intel: Add MMA feature in corebootPratik Prajapati
This patch implements Memory Margin Analysis feature in coreboot. Few things to note (1) the feature is enabled by setting CONFIG_MMA=y in the config file (2) coreboot reads mma_test_metadata.bin from cbfs during romstage and gets the name of MMA test name and test config name. Then coreboot finds these files in CBFS. If found, coreboot passes location and size of these files to FSP via UPD params. Sets MrcFastBoot to 0 so that MRC happens and then MMA test would be executed during memory init. (3) FSP passes MMA results data in HOB and coreboot saves it in cbmem (4) when system boots to OS after test is executed cbmem tool is used to grab the MMA results data. BRANCH=none BUG=chrome-os-partner:43731 TEST=Build and Boot kunimitsu (FAB3) and executed MMA tests Not tested on Glados CQ-DEPEND=CL:299476,CL:299475,CL:299474,CL:299473,CL:299509,CL:299508,CL:299507,CL:*230478,CL:*230479 Change-Id: I0b4524abcf57db4d2440a06a79b5a0f4b60fa0ea Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 4aba9b728c263b9d5da5746ede3807927c9cc2a7 Original-Change-Id: Ie2728154b49eac8695f707127334b12e345398dc Original-Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/299476 Original-Commit-Ready: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com> Original-Tested-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-on: http://review.coreboot.org/12481 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-19vendorcode/google/chromeos: Cache VPD data into CBMEMHung-Te Lin
There are few drawbacks reading VPD from SPI flash in user land, including "lack of firmware level authority" and "slow reading speed". Since for many platforms we are already reading VPD in firmware (for example MAC and serial number), caching the VPD data in CBMEM should will speed up and simplify user land VPD processing without adding performance cost. A new CBMEM ID is added: CBMEM_ID_VPD, referring to a structure containing raw Google VPD 2.0 structure and can be found by the new LB_TAG_VPD in Coreboot tables. BRANCH=smaug BUG=chrome-os-partner:39945 TEST=emerge-smaug coreboot chromeos-bootimage # and boots successfully. [pg: lots of changes to make it work with what happened in upstream since 2013] Change-Id: If8629ac002d52abed7b480d3d06298665613edbf Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 117a9e88912860a22d250ff0e53a7d40237ddd45 Original-Change-Id: Ic79f424a6e3edfb6c5d168b9661d61a56fab295f Original-Signed-off-by: Hung-Te Lin <hungte@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/285031 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/12453 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2015-11-09commonlib: Remove unused static function.zbao
Building with Clang without option -Wno-unused-function causes building error. I don't know why GCC doesn't have that issue. ------------ coreboot/src/commonlib/fsp1_1_relocate.c:47:23: error: unused function 'le8toh' [-Werror,-Wunused-function] static inline uint8_t le8toh(uint8_t byte) ^ 1 error generated. ------------ Change-Id: Iecd1e84e4321446412ef68d65dc918baf1ab45ce Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/12339 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: York Yang <york.yang@intel.com>
2015-11-07arm64: remove spin table supportAaron Durbin
As ARM Trusted Firmware is the only first class citizen for booting arm64 multi-processor in coreboot remove spintable support. If SoCs want to bring up MP then ATF needs to be ported and integrated. Change-Id: I1f38b8d8b0952eee50cc64440bfd010b1dd0bff4 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11908 Tested-by: build bot (Jenkins) Reviewed-by: Julius Werner <jwerner@chromium.org>
2015-11-03cbmem: add coreboot table records for each cbmem entryAaron Durbin
In order to not expose the cbmem data structures to userland that are used by coreboot internally add each of the cbmem entries to a coreboot table record. The payload ABI uses coreboot tables so this just provides a shortcut for cbmem entries which were manually added previously by doing the work on behalf of all entries. A cursor structure and associated functions are added to the imd code for walking the entries in order to be placed in the coreboot tables. Additionally a struct lb_cbmem_entry is added that lists the base address, size, and id of the cbmem entry. BUG=chrome-os-partner:43731 BRANCH=None TEST=Booted glados. View coreboot table entries with cbmem. Change-Id: I125940aa1898c3e99077ead0660eff8aa905b13b Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11757 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins)
2015-10-31tree: drop last paragraph of GPL copyright headerPatrick Georgi
It encourages users from writing to the FSF without giving an address. Linux also prefers to drop that and their checkpatch.pl (that we imported) looks out for that. This is the result of util/scripts/no-fsf-addresses.sh with no further editing. Change-Id: Ie96faea295fe001911d77dbc51e9a6789558fbd6 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/11888 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-10-29commonlib/region: add xlate_region_deviceAaron Durbin
There are cases where one region_device needs to be accessed using offset/sizes from one address space that need the offset translated into a different address space for operations to take place. The xlate_region_device provides an offset that is subtracted from the incoming transaction before deferring to the backing access region. Change-Id: I41d43924bb6fbc7b4d3681877543209e1085e15c Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/12227 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-10-11vboot: prepare for x86 verstageAaron Durbin
In order to support x86 verstage proper the work buffer needs to live in cache-as-ram. However, after cache-as-ram is torn down one still needs the verification results to know which slot was selected. Though the platforms with a dedicated SRAM can just use the work buffer in SRAM, the x86 cache-as-ram platforms need a place to stash the results. For that situation cbmem is employed. This works because when cbmem is initialized cache-as-ram is still enabled. The VBOOT_DYNAMIC_WORK_BUFFER case assumes verified boot doesn't start until after cbmem is up. That doesn't change, but it's a goal to get rid of that option entirely once all other x86 platforms are moved over to pre-romstage vboot. BUG=chrome-os-partner:44827 BRANCH=None TEST=Built and booted glados with pre-romstage verification as well as VBOOT_DYNAMIC_WORK_BUFFER case. Change-Id: I7eacd0edb2b6ca52b59b74075d17c00b50676d4c Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11821 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-10-02commonlib/helpers.h: handle interaction with other environmentsAaron Durbin
There are compiler settings and interactions with other header files that should be handled. First use __typeof__ instead of typeof because 'std' modes don't accept typeof. The __typeof__ variant works equally well on clang. The other change is to guard the helper macros so as not to trigger redefinition errors. BUG=chrome-os-partner:44827 BRANCH=None TEST=Built cbfstool including commonlib/helpers.h Change-Id: I58890477cb17df14a9fa8b7af752a7c70769cf36 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11773 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-10-02fsp1_1: move relocation algorithm to commonlibAaron Durbin
In order to support FSP 1.1 relocation within cbfstool the relocation code needs to be moved into commonlib. To that end, move it. The FSP 1.1 relocation code binds to edk2 UEFI 2.4 types unconditionally which is separate from the FSP's version binding. BUG=chrome-os-partner:44827 BRANCH=None TEST=Built and booted glados. Change-Id: Ib2627d02af99092875ff885f7cb048f70ea73856 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11772 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-09-22commonlib: add endian related accessor functionsAaron Durbin
This commit adds read/write functions for both big and little endian interpretations. Additionally there are variants that allow an offset to be provided into the source buffer. BUG=None TEST=Wrote test harness for functions. Also booted ARM QEMU through end of payload. Change-Id: If44c4d489f0dab86a73b73580c039e364c7e517d Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11677 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-09-22coreboot: introduce commonlibAaron Durbin
Instead of reaching into src/include and re-writing code allow for cleaner code sharing within coreboot and its utilities. The additional thing needed at this point is for the utilities to provide a printk() declaration within a <console/console.h> file. That way code which uses printk() can than be mapped properly to verbosity of utility parameters. Change-Id: I9e46a279569733336bc0a018aed96bc924c07cdd Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11592 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
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