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2020-01-10src/commonlib/storage: Fix typosElyes HAOUAS
Change-Id: Ie210191b79e94d3918ea95d40aeba40f33eb1b2f Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38269 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-12-19commonlib/fsp_relocate: Fix typosElyes HAOUAS
Change-Id: I9426b88c0936c68d02554b580cc312902b8e5e13 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37810 Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-19storage/mmc: Fix wrong frequency setting for HS speed modeBora Guvendik
Emmc spec, JEDEC Standard No. 84-B51, section 6.6.2.3, selection flow of HS400 using Enhanced Strobe states that host should change frequency to ≤ 52MHz when switching to HS speed mode first. In current code, mmc_select_hs400() calls mmc_select_hs() to do this, however caps are not cleared, so when switching from HS200 to HS400, caps will still have DRVR_CAP_HS200, and mmc_recalculate_clock() will set 200Mhz instead of ≤ 52MHz. As a result, switching to HS400 will intermittently fail. BUG=b:140124451 TEST=Switch speed from HS200 to HS400 on WHL RVP. Change-Id: Ie639c7616105cca638417d7bc1db95b561afb7af Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37775 Reviewed-by: Selma Bensaid <selma.bensaid@intel.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-19Drop ROMCC code and header guardsArthur Heymans
Change-Id: I730f80afd8aad250f26534435aec24bea75a849c Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37334 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2019-12-11printf: Automatically prefix %p with 0xJulius Werner
According to the POSIX standard, %p is supposed to print a pointer "as if by %#x", meaning the "0x" prefix should automatically be prepended. All other implementations out there (glibc, Linux, even libpayload) do this, so we should make coreboot match. This patch changes vtxprintf() accordingly and removes any explicit instances of "0x%p" from existing format strings. How to handle zero padding is less clear: the official POSIX definition above technically says there should be no automatic zero padding, but in practice most other implementations seem to do it and I assume most programmers would prefer it. The way chosen here is to always zero-pad to 32 bits, even on a 64-bit system. The rationale for this is that even on 64-bit systems, coreboot always avoids using any memory above 4GB for itself, so in practice all pointers should fit in that range and padding everything to 64 bits would just hurt readability. Padding it this way also helps pointers that do exceed 4GB (e.g. prints from MMU config on some arm64 systems) stand out better from the others. Change-Id: I0171b52f7288abb40e3fc3c8b874aee14b9bdcd6 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37626 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: David Guckian
2019-12-03src: Add missing include <stdlib.h>Elyes HAOUAS
Change-Id: I17dc2fed6c6518daf5af286788c98c049088911e Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37366 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2019-11-29commonlib/storage/pci_sdhci.c: Drop CAR_GLOBAL_MIGRATION supportArthur Heymans
Change-Id: Idfbc0cf24000c361c9272fe0f61797de999c9277 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37052 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-20security/vboot/sync_ec: Add timestampsTim Wawrzynczak
Add 4 new timestamps to the EC software sync flow: 1) Beginning of EC software sync 2) EC finished calculating Vboot hash 3) EC is no longer requesting power limiting 4) End of EC software sync BUG=none BRANCH=none TEST=verified timestamps show up in cbmem log Change-Id: I6e5703c146b5ec27d01700fdb39cb3d2092ea8a8 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36209 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-11-14{drivers,mainboard}: Move FSP logo support to fsp1_1Frans Hendriks
Support to display a logo using FSP 1.1 currently resides in facebook fbg1701 mainboard. The related support is moved to drivers/intel/fsp1_1 and used by the Facebook fbg1701 mainboard. The storage for the uncompressed logo is changed. We don't use .bss any longer as the logo doesn't need to be available at runtime. BUG=N/A TEST=booting Facebook fbg1701 Change-Id: I276e6e14fc87d0b95fe5fdf7b617afd26769de79 Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36679 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2019-11-11region: publicize region_end() and add region_device_end()Aaron Durbin
Provide region_device_end() and make region_end() publically available for use to match a pattern of open coding the offset + size calculation for both struct region and struct region_device. Apply the use of the helpers where the usage matches in the code. Change-Id: Iaef5d007eef9a77f7f33b0e89298abef0197352d Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36689 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-11region: add rdev_chain_full()Aaron Durbin
Instead of open coding an offset of 0 and querying the size of a region device provide a rdev_chain_full() helper function that does that for the caller. For the existing users that match this pattern convert them to using rdev_chain_full(). Change-Id: Ie316790a8a5b16a7f7e22f86f58bd2e633c19450 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36683 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-05commonlib: Use __builtin_offsetof with supported compilersAlex James
Use __builtin_offsetof (which is treated as a constant expression) with Clang & GCC. This also allows check_member to work with Clang 9. Signed-off-by: Alex James <theracermaster@gmail.com> Change-Id: I8b5cb4110c13ee42114ecf65932d7f1e5636210e Reviewed-on: https://review.coreboot.org/c/coreboot/+/36249 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-30commonlib/helpers: Add alloca() macroTim Wawrzynczak
If there is no alloca() macro defined, then define it as __builtin_alloca(), as most compilers support that as an intrinsic instead, if no alloca.h is included. Change-Id: I8730d57ce7c2f323b52e7a5720c598fb7af16b44 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36387 Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-20cbmem: Add IDs for TSEG and BERT table dataMarshall Dawson
Prepare for products that can use any DRAM for TSEG. Include an ID for data pointed to by an ACPI BERT table. This region's only requirement is it is marked reserved. Change-Id: Ia6518e881b0add71c622e65572474e0041f83d61 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36115 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-18util/cbfstool: Add optional argument ibbPhilipp Deppenwiese
* Mark files in CBFS as IBB (Initial BootBlock) * Will be used to identify the IBB by any TEE Change-Id: Idb4857c894b9ee1edc464c0a1216cdda29937bbd Signed-off-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/29744 Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-30device,drivers/: Drop some __SIMPLE_DEVICE__ useKyösti Mälkki
The simple PCI config accessors are always available under names pci_s_[read|write]_configX. Change-Id: Ic1b67695b7f72e4f1fa29e2d56698276b15024e1 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35669 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-09-23lib/fmap: Cache FMAP in cbmemPatrick Rudolph
For platform independend exposure of FMAP through a kernel module cache the FMAP in CBMEM. In addition add a pointer in coreboot tables pointing to the introduced CBMEM area. To not waste the allocated DRAM, use the cached CBMEM in RAM enabled stages if possible. Tested on qemu using https://github.com/9elements/linux/commits/google_firmware_fmap2 Tested on QEMU and Supermicro X11SSH-TF. Change-Id: I4e01c573c3edfa34dbba5fe7604d4f6e18b584d5 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35377 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-09-10AUTHORS: Move src/commonlib copyrights into AUTHORS fileMartin Roth
As discussed on the mailing list and voted upon, the coreboot project is going to move the majority of copyrights out of the headers and into an AUTHORS file. This will happen a bit at a time, as we'll be unifying license headers at the same time. Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: I4c9351652d81040cc4e7b85bdd1ba85709a74192 Reviewed-on: https://review.coreboot.org/c/coreboot/+/35178 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-08-19commonlib/region: Fix up overflow check in region_is_subregion()Julius Werner
region_is_subregion() checks whether the size of the inner region is larger than the size of the outer region... which isn't really necessary because we're already checking the starts and ends of both regions. Maybe this was added to ensure the inner region doesn't overflow? But it's not guaranteed to catch that in all cases. Replace it with a proper overflow check. Change-Id: I9e442053584a479a323c1fa1c0591934ff83eb10 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34892 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-08-08lib/edid: Add suport for display rotationNicolas Boichat
Sometimes the display native orientation does not match the device default orientation. We add a parameter to be passed to libpayload, which can then do the rotation. BUG=b:132049716 TEST=Boot krane, see that FW screen is orientation properly. Change-Id: I5e1d94b973a3f615b73eebe0ca1202ba03731844 Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34731 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-07-23vboot: deprecate vboot_handoff structureJoel Kitching
vboot_handoff is no longer used in coreboot, and is not needed in CBMEM or cbtable. BUG=b:124141368, b:124192753 TEST=make clean && make runtests BRANCH=none Change-Id: I782d53f969dc9ae2775e3060371d06e7bf8e1af6 Signed-off-by: Joel Kitching <kitching@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33536 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-21commonlib/storage: use ALIGN_UP instead of ALIGN for better readabilityFelix Held
Change-Id: I76ec5ff107bc043d9457b3377e88226a96eb3f3c Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33632 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2019-06-18commonlib: define cbtable tags as enum to identify conflictsPatrick Georgi
We had a value that was overloaded thrice. By moving them in a common structure and ordering them by value such issues are hopefully avoided in the future. Also add a few values to libpayload that were only defined in commonlib. Change-Id: I227d078eebee2d92488454707d4dab8ecc24a4d8 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32958 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-07cbmem: Add ID for UCSIDuncan Laurie
The USB Type-C Connector System Software Interface (UCSI) defines a required memory oregion for the OS UCSI driver to use to communicate with the BIOS and EC. This provides a CBMEM ID that can be used by drivers to allocate this shared memory region for the UCSI driver to use. BUG=b:131083691 Change-Id: Id5b7fa19436443bc11a6ebe3ce89cd552cee4d85 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32356 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-05-29commonlib: fix typo LB_TAB_* (instead of LB_TAG_*)Patrick Georgi
Also adapt all users of these symbols Change-Id: Ibf924a283d438de49a93ce661b0d9ca1a81cd6d1 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32956 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-05-29commonlib: renumber CB_TAG_TCPA_LOGPatrick Georgi
It conflicts with VBOOT_WORKBUF but unlike VBOOT_WORKBUF no user can be identified in the coreboot tree for TCPA_LOG, so renumber this. Change-Id: Ib8a850c0ccbcacdf7d288316b54eb82fce874a82 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32955 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-05-23Renumber cbtable tag MMC_INFOPatrick Georgi
We got another tag in the meantime, so resolve the conflict. Change-Id: I64cb5e02a9bed3d8746b75e451c13a1598341ba1 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32954 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-05-23coreboot_tables: pass the early_mmc_wake_hw status to payloadBora Guvendik
Pass the return value from early_mmc_wake_hw() to the payload so that payload can skip sending CMD0 and resetting the card in case of success or in case of a failure in firmware, payload can recover by sending CMD0 and resetting the card. BUG=b:78106689 TEST=Boot to OS Change-Id: Ia4c57d05433c3966118c3642913d7017958cce55 Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/25464 Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-05-23intel/common/block/scs: Add ability to send early CMD0, CMD1Bora Guvendik
In order to improve boot time with emmc, add ability to send CMD0 and CMD1 early in romstage. This way, by the time system boots to payload, we are ready to continue with emmc setup and we don't need to send CMD0 in payload again, and wait for card to reset and be ready. BUG=b:78106689 TESTS = Boot to OS Force early_mmc_wake_hw() to return error, recover in payload Force an error in payload, make sure system can recover/boot Change-Id: I3488b077bf5100a1e0f2c879fb1436105607d25e Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/25068 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
2019-05-23commonlib/stdlib.h: Remove printf() from corebootJulius Werner
coreboot should not have a definition of printf() anywhere -- it's too easy to accidentally sneak it into code otherwise. Where that is needed in code shared with userspace utilities, we should instead use printk() and define a shim for that for the userspace side. Change-Id: Iaa459df7122c88beb56695eee7c252d90bbde861 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32857 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-05-09vboot: include vb2_sha.h when requiredJoel Kitching
Should include vb2_sha.h header when SHA library functions or constants are required. This replaces NEED_VB2_SHA_LIBRARY. BUG=b:124141368, chromium:956474 TEST=make clean && make test-abuild BRANCH=none Change-Id: I9f32174dbf3de05fbe5279cb8017888757abf368 Signed-off-by: Joel Kitching <kitching@google.com> Cq-Depend: chromium:1583820 Reviewed-on: https://review.coreboot.org/c/coreboot/+/32454 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-04-23src: include <assert.h> when appropriateElyes HAOUAS
Change-Id: Ib843eb7144b7dc2932931b9e8f3f1d816bcc1e1a Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/26796 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: David Guckian
2019-04-23src: Add missing include 'console.h'Elyes HAOUAS
Change-Id: Ie21c390ab04adb5b05d5f9760d227d2a175ccb56 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32122 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2019-04-08commonlib/cbfs: Check for presence of CONFIG() macroNico Huber
Check for CONFIG not IS_ENABLED, as we use the former now. Change-Id: I7e1b67bc0894ca6f0149039054449656b58bcdd3 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32226 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-04-06src: Use #include <timer.h> when appropriateElyes HAOUAS
Also, extra-lines added or removed and local includes moved down. Change-Id: I5e739233f3742fd68d537f671642bb04886e3009 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32009 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-04Make common macros double-evaluation safeJulius Werner
I just got hit by a double-evaluation bug again, it's time to attempt to fix this once more. Unfortunately there are several issues that don't make this easy: - bitfield variables don't support typeof() - local macro variables that shadow others trigger -Werror=shadow - sign warnings with integer literal and unsigned var in typeof-MIN() - ({ statement expressions }) can not be used outside functions - romcc doesn't support any of the fancy GCC/clang extensions This patch tries to address all of them as far as possible with macro magic. We don't have the technology to solve the bitfield and non-function context issues yet (__builtin_choose_expr() still throws a "no statement expression outside a function" error if it's only in the branch that's not chosen, unfortunately), so we'll have to provide alternative macros for use in those cases (and we'll avoid making __ALIGN_MASK() double-evaluation safe for now, since it would be annoying to do that there and having an alignment mask with side effects seems very unlikely). romcc can continue using unsafe versions since we're hopefully not writing a lot of new code for it. Sign warnings can be avoided in literal/variable comparisons by always using the type of the variable there. Shadowing is avoided by picking very explicit local variable names and using a special __COUNTER__ solution for MIN() and MAX() (the only ones of these you're likely to nest). Also add DIV_ROUND_UP() to libpayload since it's a generally quite useful thing to have. Change-Id: Iea35156c9aa9f6f2c7b8f00991418b746f44315d Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32027 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-03-25Fix up remaining boolean uses of CONFIG_XXX to CONFIG(XXX)Julius Werner
This patch cleans up remaining uses of raw boolean Kconfig values I could find by wrapping them with CONFIG(). The remaining naked config value warnings in the code should all be false positives now (although the process was semi-manual and involved some eyeballing so I may have missed a few). Change-Id: Ifa0573a535addc3354a74e944c0920befb0666be Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31813 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-03-20src: Use 'include <string.h>' when appropriateElyes HAOUAS
Drop 'include <string.h>' when it is not used and add it when it is missing. Also extra lines removed, or added just before local includes. Change-Id: Iccac4dbaa2dd4144fc347af36ecfc9747da3de20 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31966 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-03-19vboot: make vboot workbuf available to payloadJoel Kitching
Create a new cbtable entry called VBOOT_WORKBUF for storing a pointer to the vboot workbuf within the vboot_working_data structure. BUG=b:124141368, b:124192753 TEST=Build and deploy to eve TEST=util/lint/checkpatch.pl -g origin/master..HEAD TEST=util/abuild/abuild -B -e -y -c 50 -p none -x BRANCH=none Change-Id: Id68f43c282939d9e1b419e927a14fe8baa290d91 Signed-off-by: Joel Kitching <kitching@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31887 Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-16src: Drop unused '#include <halt.h>'Elyes HAOUAS
Change-Id: Ie7afe77053a21bcf6a1bf314570f897d1791a620 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31921 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-03-14vboot: copy data structures to CBMEM for downstream useJoel Kitching
For platforms that do not employ VBOOT_STARTS_IN_ROMSTAGE, vboot verification occurs before CBMEM is brought online. In order to make vboot data structures available downstream, copy vb2_working_data from CAR/SRAM into CBMEM when CBMEM comes online. Create VBOOT_MIGRATE_WORKING_DATA config option to toggle this functionality. BUG=b:124141368, b:124192753 TEST=Built and deployed on eve with STARTS_IN_BOOTBLOCK TEST=Built and deployed on eve with STARTS_IN_ROMSTAGE TEST=util/lint/checkpatch.pl -g origin/master..HEAD TEST=util/abuild/abuild -B -e -y -c 50 -p none -x BRANCH=none Change-Id: I62c11268a83927bc00ae9bd93b1b31363b38e8cf Signed-off-by: Joel Kitching <kitching@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31329 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-03-14commonlib/bubblesort: Do not try to sort less than two entriesWerner Zeh
Before start sorting check for the number of entries in the data set. If there are less than two entries, sorting makes no sense. Change-Id: Ib9d5522cdebb6559a025217f7faf318589d55a2c Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31854 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-03-08coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX)Julius Werner
This patch is a raw application of find src/ -type f | xargs sed -i -e 's/IS_ENABLED\s*(CONFIG_/CONFIG(/g' Change-Id: I6262d6d5c23cabe23c242b4f38d446b74fe16b88 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31774 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-03-07arch/x86/postcar: Add separate timestamp for postcar stageSubrata Banik
This patch adds dedicated timestamp value for postcar stage. TEST=Able to see "start of postcar" and "end of postcar" timestamp while executing cbmem -t after booting to chrome console. > cbmem -t 951:returning from FspMemoryInit 20,485,324 (20,103,067) 4:end of romstage 20,559,235 (73,910) 100:start of postcar 20,560,266 (1,031) 101:end of postcar 20,570,038 (9,772) Change-Id: I084f66949667ad598f811d4233b4e639bc4c113e Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31762 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-03-07security/tpm: Fix TCPA log featurePhilipp Deppenwiese
Until now the TCPA log wasn't working correctly. * Refactor TCPA log code. * Add TCPA log dump fucntion. * Make TCPA log available in bootblock. * Fix TCPA log formatting. * Add x86 and Cavium memory for early log. Change-Id: Ic93133531b84318f48940d34bded48cbae739c44 Signed-off-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/29563 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-03-04device/mmio.h: Add include file for MMIO opsKyösti Mälkki
MMIO operations are arch-agnostic so the include path should not be arch/. Change-Id: I0fd70f5aeca02e98e96b980c3aca0819f5c44b98 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/31691 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-04fmap: Add FMAP_AREA_PRESERVEHung-Te Lin
When updating firmware, we may need to preserve some sections like VPD, calibration data, ... etc. The logic can be hard-coded in updater as a list of known names, but a better solution is to have that directly declared inside FMAP area flags. To do that, the first step is to apply the changes in flash map (http://crosreview.com/1493767). A new FMAP_AREA_PRESERVE is now defined and will be set in future with new syntax in FMD parser. BUG=chromium:936768 TEST=make; boots an x86 image. Change-Id: Idba5c8d4a4c5d272f22be85d2054c6c0ce020b1b Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: https://review.coreboot.org/c/31676 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-03-01device/pci: Fix PCI accessor headersKyösti Mälkki
PCI config accessors are no longer indirectly included from <arch/io.h> use <device/pci_ops.h> instead. Change-Id: I2adf46430a33bc52ef69d1bf7dca4655fc8475bd Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/31675 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-02-26commonlib: Add Bubble sort algorithmWerner Zeh
Add an implementation for Bubble sort. For now, only integers can be sorted in an ascending or descending order. It can be later simply extended to cover other datasets like strings if needed. The reasons for choosing bubble sort are: * it is a simple algorithm * bubble sort is stable, i.e. it does not exchange entries which are not needed to be sorted as they are already in order Change-Id: I2c5e0b5685a907243b58ebe6682078272d316bf6 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/31544 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-01-16buildsystem: Promote rules.h to default includeKyösti Mälkki
Does not fix 3rdparty/, *.S or *.ld or yet. Change-Id: I66b48013dd89540b35ab219d2b64bc13f5f19cda Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/17656 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-11-29src: Remove duplicated round up functionElyes HAOUAS
This removes CEIL_DIV and div_round_up() altogether and replace it by DIV_ROUND_UP defined in commonlib/helpers.h. Change-Id: I9aabc3fbe7834834c92d6ba59ff0005986622a34 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/29847 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2018-11-27src/{commonlib,drivers/intel/fslp1_1/include}: Fix typoFrans Hendriks
Correct typo of 'compilation' BUG=N/A TEST=N/A Change-Id: Iee6b8a8afc4d885d2d4ab9ee5d596e32e5e6d3f1 Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-on: https://review.coreboot.org/c/29831 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2018-11-23src/arch/x86/acpi.c: Create log area and extend TPM2 tableMichał Żygowski
According to newest TCG ACPI Specification for Family 1.2 and 2.0 Version 1.2, Revision 8, TPM2 ACPI table has two more fields LAML and LASA. Update the table structure definition, create the log area for TPM2 in coreboot tables and fill the missing fields in TPM2 table. TPM2 should be now probed well in SeaBIOS rel-1.12.0 or master. Tested on apu2 with Infineon SLB9665 TT2.0. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: Ie482cba0a3093aae996f7431251251f145fe64f3 Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/29800 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2018-11-16src: Get rid of duplicated includesElyes HAOUAS
Change-Id: I252a1cd77bf647477edb7dddadb7e527de872439 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29582 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2018-10-23src: Remove unneeded whitespaceElyes HAOUAS
Change-Id: I6c77f4289b46646872731ef9c20dc115f0cf876d Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29161 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2018-10-11commonlib/storage: Make pci sdhci code compile in romstageBora Guvendik
In romstage malloc is not available, so use CAR_GLOBAL variable instead. BUG=b:78106689 TEST=Boot to OS Change-Id: If9438d0b707c6ffaa61db80bd1d385112bc91cfc Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-on: https://review.coreboot.org/25067 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-10-08Move compiler.h to commonlibNico Huber
Its spreading copies got out of sync. And as it is not a standard header but used in commonlib code, it belongs into commonlib. While we are at it, always include it via GCC's `-include` switch. Some Windows and BSD quirk handling went into the util copies. We always guard from redefinitions now to prevent further issues. Change-Id: I850414e6db1d799dce71ff2dc044e6a000ad2552 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/28927 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-09-14complier.h: add __always_inline and use it in code baseAaron Durbin
Add a __always_inline macro that wraps __attribute__((always_inline)) and replace current users with the macro, excluding files under src/vendorcode. Change-Id: Ic57e474c1d2ca7cc0405ac677869f78a28d3e529 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/28587 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@google.com>
2018-08-22cbtable: remove chromeos_acpi from cbtableJoel Kitching
Since we can derive chromeos_acpi's location from that of ACPI GNVS, remove chromeos_acpi entry from cbtable and instead use acpi_gnvs + GVNS_CHROMEOS_ACPI_OFFSET. BUG=b:112288216 TEST=None CQ-DEPEND=CL:1179725 Change-Id: I74d8a9965a0ed7874ff03884e7a921fd725eace9 Signed-off-by: Joel Kitching <kitching@google.com> Reviewed-on: https://review.coreboot.org/28190 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-08-22acpi: remove CBMEM_ID_ACPI_GNVS_PTR entryJoel Kitching
Since we can retrieve the address of ACPI GNVS directly from CBMEM_ID_ACPI_GNVS, there is no need to store and update a pointer separately. TEST=Compile and run on Eve Signed-off-by: Joel Kitching <kitching@google.com> Change-Id: I59f3d0547a4a724e66617c791ad82c9f504cadea Reviewed-on: https://review.coreboot.org/28189 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-08-16src/{commonlib,lib}: Fix typoElyes HAOUAS
Change-Id: If7650ac4d9be2614a9665c7f2aba9ac5cc413efe Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/28097 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-08-14cbmem: rename vdat to chromeos_acpiJoel Kitching
There is a confusingly named section in cbmem called vdat. This section holds a data structure called chromeos_acpi_t, which exposes some system information to the Chrome OS userland utility crossystem. Within the chromeos_acpi_t structure, there is a member called vdat. This (currently) holds a VbSharedDataHeader. Rename the outer vdat to chromeos_acpi to make its purpose clear, and prevent the bizarreness of being able to access vdat->vdat. Additionally, disallow external references to the chromeos_acpi data structure in gnvs.c. BUG=b:112288216 TEST=emerge-eve coreboot, run on eve CQ-DEPEND=CL:1164722 Change-Id: Ia74e58cde21678f24b0bb6c1ca15048677116b2e Signed-off-by: Joel Kitching <kitching@google.com> Reviewed-on: https://review.coreboot.org/27888 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-08-03security/tpm: Improve TCPA log generationPhilipp Deppenwiese
* Make tcpa_log_init static and move init code into the tcpa_log_add_table_entry routine. * Add more checks for log initialization. * Fix minor issues Change-Id: I215d79eed7ad17c6ab87f0c4b14a282e519ef07d Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org> Reviewed-on: https://review.coreboot.org/27769 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-30security/tpm: Use unique CBMEM names for TCPA logsPhilipp Deppenwiese
Fix regression introduced in commit f18dc5c7 "Add TCPA logging functionality": Introduced TCPA log got overwritten in acpi.c of x86/arch, due to CBMEM name collision. Use a different cbmem name to have two independent TCPA logs. Change-Id: Iac63ac26989080a401aac2273265a263a3fdec56 Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org> Reviewed-on: https://review.coreboot.org/27726 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-07-28util/cbmem: Add cbmem TCPA log supportPhilipp Deppenwiese
* Read and print the TCPA ACPI log. Change-Id: Ie2253d86cfc675d45b0a728794cc784215401f4a Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org> Reviewed-on: https://review.coreboot.org/26244 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-07-28security/tpm: Add TCPA logging functionalityPhilipp Deppenwiese
* TCG spec only applies to BIOS or UEFI. * Therefore implement coreboot TCPA compliant log in CBMEM. * Write CBMEM log into the coreboot table for CBMEM tool access Change-Id: I0a52494f647d21e2587231af26ed13d62b3a72f5 Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org> Reviewed-on: https://review.coreboot.org/22867 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-07-09src/{arch,commonlib,cpu}: Use "foo *bar" instead of "foo* bar"Elyes HAOUAS
Change-Id: I8e4118c5c5d70719ad7dc5f9ff9f86d93fa498ac Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26942 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-07-02commonlib/storage: Make sd_mmc_go_idle an apiBora Guvendik
change sd_mmc_go_idle to be accessible from other files so that we have an api to send CMD0 and reset the card. BUG=b:78106689 TEST=Boot to OS Change-Id: I064a9bded347be5d500047df92d1c448c3392016 Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-on: https://review.coreboot.org/25066 Reviewed-by: Justin TerAvest <teravest@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-15util/cbfstool: Support FIT payloadsPatrick Rudolph
In order to support booting a GNU/Linux payload on non x86, the FIT format should be used, as it is the defacto standard on ARM. Due to greater complexity of FIT it is not converted to simple ELF format. Add support for autodecting FIT payloads and add them as new CBFS_TYPE 'fit'. The payload is included as is, with no special header. The code can determine the type at runtime using the CBFS_TYPE field. Support for parsing FIT payloads in coreboot is added in a follow on commit. Compression of FIT payloads is not supported, as the FIT sections might be compressed itself. Starting at this point a CBFS payload/ can be either of type FIT or SELF. Tested on Cavium SoC. Change-Id: Ic5fc30cd5419eb76c4eb50cca3449caea60270de Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/25860 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-06-04src/commonlib/storage: Move include <console.h> to sd_mmc.hElyes HAOUAS
Non of the .c files is using a function from console.h directly. Include console.h is moved to sd_mmc.h, where sdhc_error("msg..") is defined. Change-Id: Ic9283f227a37785056b9fac216fabcac054066a0 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26752 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-22Introduce bootblock self-decompressionJulius Werner
Masked ROMs are the silent killers of boot speed on devices without memory-mapped SPI flash. They often contain awfully slow SPI drivers (presumably bit-banged) that take hundreds of milliseconds to load our bootblock, and every extra kilobyte of bootblock size has a hugely disproportionate impact on boot speed. The coreboot timestamps can never show that component, but it impacts our users all the same. This patch tries to alleviate that issue a bit by allowing us to compress the bootblock with LZ4, which can cut its size down to nearly half. Of course, masked ROMs usually don't come with decompression algorithms built in, so we need to introduce a little decompression stub that can decompress the rest of the bootblock. This is done by creating a new "decompressor" stage which runs before the bootblock, but includes the compressed bootblock code in its data section. It needs to be as small as possible to get a real benefit from this approach, which means no device drivers, no console output, no exception handling, etc. Besides the decompression algorithm itself we only include the timer driver so that we can measure the boot speed impact of decompression. On ARM and ARM64 systems, we also need to give SoC code a chance to initialize the MMU, since running decompression without MMU is prohibitively slow on these architectures. This feature is implemented for ARM and ARM64 architectures for now, although most of it is architecture-independent and it should be relatively simple to port to other platforms where a masked ROM loads the bootblock into SRAM. It is also supposed to be a clean starting point from which later optimizations can hopefully cut down the decompression stub size (currently ~4K on RK3399) a bit more. NOTE: Bootblock compression is not for everyone. Possible side effects include trying to run LZ4 on CPUs that come out of reset extremely underclocked or enabling this too early in SoC bring-up and getting frustrated trying to find issues in an undebuggable environment. Ask your SoC vendor if bootblock compression is right for you. Change-Id: I0dc1cad9ae7508892e477739e743cd1afb5945e8 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/26340 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-05-16commonlib/cbfs: Make cbfsf_file_type publicPatrick Rudolph
Make cbfsf_file_type public to support detecting the payload type at runtime. To be used by the following commits. Possible payload types are: * simple ELF * FIT Change-Id: I37e9fb06f926dc71b001722a6c3b6205a2f20462 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/25859 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-14cbfs_locate: Optionally return file typeRonald G. Minnich
In some cases callers want to know if a file exists and, if so, what its type is. Modify cbfs_locate so that if the pointer is non-NULL, but has the value 0, the type of the file that matches the name will be returned. Change-Id: Ic1349d358c3054207ccbccf3825db56784327ad0 Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: https://review.coreboot.org/26279 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-05-13timestamp: Add timestamps for TPM communicationRaul E Rangel
On grunt these operations combined take a little over 37ms. BUG=b:64549506 TEST=built on grunt 511:starting TPM PCR extend 301,268 (598) 512:finished TPM PCR extend 326,710 (25,442) 513:starting locking TPM 326,716 (6) 514:finished locking TPM 339,517 (12,801) Change-Id: I05cfb3d0f8463f073e329a035484a340546649e1 Signed-off-by: Raul E Rangel <rrangel@chromium.org> Reviewed-on: https://review.coreboot.org/26218 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-04cbfs: Rename CBFS_TYPE_PAYLOAD to CBFS_TYPE_SELFPatrick Rudolph
In preparation of having FIT payloads, which aren't converted to simple ELF, rename the CBFS type payload to actually show the format the payload is encoded in. Another type CBFS_TYPE_FIT will be added to have two different payload formats. For now this is only a cosmetic change. Change-Id: I39ee590d063b3e90f6153fe655aa50e58d45e8b0 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/25986 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-05-04commonlib: Add descriptions for new AGESA timestampsMartin Roth
When the latest AGESA timestamp values were added, the descriptions weren't added along with them. Because of this, the cbmem tool just shows them as "<unknown>". Bug=b:79153552 TEST=None Change-Id: Iad7bcd53bc6136b74d4d933d1a290feac6a0de56 Signed-off-by: Martin Roth <martinroth@chromium.org> Reviewed-on: https://review.coreboot.org/26001 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-24compiler.h: add __weak macroAaron Durbin
Instead of writing out '__attribute__((weak))' use a shorter form. Change-Id: If418a1d55052780077febd2d8f2089021f414b91 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/25767 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Justin TerAvest <teravest@chromium.org>
2018-03-08timestamps: Add timestamps around the vbios load & initMartin Roth
Add timestamps before and after the vBIOS load and after the vBIOS run. This lets us see exactly how long it took to load it from the ROM chip, and how long it takes to run. BUG=b:64549506 TEST=Build & boot Grunt, see vBIOS load & initialization times. Change-Id: I878ba653eb086ad6c6614aa08a6d3fe216a9323e Signed-off-by: Martin Roth <martinroth@chromium.org> Reviewed-on: https://review.coreboot.org/25018 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-02-07lib/stage_cache: Add save/get raw storageMarshall Dawson
Leverage the stage_cache mechanism to store a non-specific type of data. This is not interesting when the location for the cache is in cbmem. However it will be more useful when an external location is used, e.g. when the cache is in TSEG, locked from user modification. Change-Id: Iaf0b25ebe14c176bbd24fc8942f902f627ca8e6f Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/23518 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-02-07storage: Fix CMD13 failure issueBarnali Sarkar
This patch stores the correct capabilities for EMMC media which in turn sets the correct timing data for HS400 mode. Without this code change, EMMC CMD13 is failing at the end of HS400 mode switching. BUG=none BRANCH=none TEST=Build and boot Soraka Change-Id: I3f00c9eace7cc136d86a1e07f040fbfc09e0e02e Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/23541 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-02-05coreboot_tables: Document coreboot framebufferNico Huber
A discussion around the `bytes_per_line` field (it was ignored in CorebootPayloadPkg for some reason) made the lack of documentation obvious. Change-Id: I5e1343b5fe37ac106e61e6907fbcc1737ac56f8b Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/23466 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-01-31commonlib: Add AGESA S3 resume definesMarshall Dawson
Extend the values reserved for AGESA to include the Entry Points used for S3 Resume. BUG=b:69614064 Change-Id: I6b50e76a0c49c1f317f9294c5f95735e7aa5d95c Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/23439 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-01-31device/pci_rom: Write _ROM method for VGA devicesPatrick Rudolph
Write _ROM method and store PCI Option ROM in CBMEM. Allows an EFI compatible OS to retrieve the Option ROM without the need to access the PCI BAR. As the Option ROM is no longer present in the legacy VGA area it's required for mobile platforms. On hybrid devices, like Lenovo Thinkpads supporting NVIDIA Optimus it's the only way to retrieve the Option ROM, even with legacy BIOS, as there's no PCI BAR to map. Tested on: * Lenovo T530 * Linux Kernel 4.13.7 * nouveau Change-Id: I548b730fb64833083cc05af5b21dd6959804224b Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/20548 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-12-15commonlib/region: expose subregion helper functionAaron Durbin
Export region_is_subregion() for determinig if a region is a child of a parent region. BUG=b:69614064 Change-Id: I6363fe4fdb33342f9d025a726ec7e17e87adf7e0 Signed-off-by: Aaron Durbn <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/22878 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-12-11commonlib: Add timestamp codes for AGESAMartin Roth
BUG=b:70432544 TEST=Build & boot kahlee. Look at timestamps. Change-Id: I3bf691a0fb1f5c09e7b6c9965c9e506393ec31f6 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/22797 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-12-07boardid: Add helpers to read sku_id strapping into coreboot tablesJulius Werner
On many recent Chrome OS boards, the desire to unite more configurations under the same image has led to the need of a "SKU ID" that identifies different configurations of the same board (e.g. with certain optional components stuffed or not stuffed, or replaced with a comparable component). This is markedly different from the existing "board ID", because that is reserved to count "revisions" -- changes made to the same configuration over time during the development process. This patch adds support to have a mainboard define this SKU ID and pass it through the coreboot table like we already have for board IDs. Change-Id: I8aabffe8e1003b0d6fb70d689ae513ca4b46aeda Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/22696 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-12-07boardid: Minor clean up and standardizationJulius Werner
Merge the different coreboot table strapping ID structures into one because they're really just all the same, and I want to add more. Make the signature of the board_id() function return a uint32_t because that's also what goes in the coreboot table. Add a printk to the generic code handling strapping IDs in ramstage so that not every individual mainboard implementation needs its own print. (In turn, remove one such print from fsp1_1 code because it's in the way of my next patch.) Change-Id: Ib9563edf07b623a586a4dc168fe357564c5e68b5 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/22741 Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-12-02riscv: Remove config string supportJonathan Neuschäfer
The code dealing with the old config string isn't needed anymore, because the config string has been deprecated in favor of OpenFirmware-derived devicetrees. Change-Id: I71398fb4861dbaf7eefc6e6f222bb7159798fafa Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/22594 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2017-11-04commonlib/helpers.h: Include stddef.hJonathan Neuschäfer
The definition of offsetof() uses size_t, which is declared in stddef.h, according to POSIX. Include stddef.h directly to avoid relying on implicit inclusion. Change-Id: I221be02c332de55c9fcf7d86673709ed43dd5c3c Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/22230 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maximilian Schander <coreboot@mimoja.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-10-29LB_TAGS: change the value of CB_TAG_MAC_ADDRS to 0x33Ronald G. Minnich
When building the Go version of cbmem I found that LB_TAG_MAC_ADDRS has the same value as LB_TAG_VERSION_TIMESTAMP. I am guessing that this tag was little used. In any event, move it forward to 0x33. Change-Id: I038ad68e787e56903a2ed9cb530809a55821c313 Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: https://review.coreboot.org/22218 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-10-18arch/x86: restore forwarding table on resume for EARLY_EBDA_INITAaron Durbin
In commit c06a3f72 (arch/x86: initialize EBDA in S3 and S0/S5 path) the BDA and EBDA are wiped in the resume path. However, the coreboot table forwarding entry wasn't taken into account so that was wiped which resulted in cbmem not working on the resume path. Fix this by stashing the forwarding table in cbmem and restoring it on the resume path. Change-Id: I142503535a78635fbb1c698fc7d032c1a2921813 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/22078 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-09-27commonlib: Consistently spell *romstage* without spacePaul Menzel
Make the spelling of *romstage* consistent without a space. Choose this version, as *ramstage* is also spelled without a space, since commit a7d924412a (timestamps: You can never have enough of them!). Fixes: 0db924d74c (cbmem: print timestamp names) Change-Id: I1b1c10393f0afb9a20ac916ff9dc140a51c716cd Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: https://review.coreboot.org/21706 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-09-13sb/intel/bd82x6x: Add time-stamp around ME DRAM updateNathaniel Roach
Add a timestamp before and after waiting for the ME to acknowledge the DRAM being ready. This allows easier debugging during use of me_cleaner and/or alternate ME images. Change-Id: Ie228e12a75d373b4f406b3595e1fb1aab41aa5df Signed-off-by: Nathaniel Roach <nroach44@gmail.com> Reviewed-on: https://review.coreboot.org/21465 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-07-13Rename __attribute__((packed)) --> __packedStefan Reinauer
Also unify __attribute__ ((..)) to __attribute__((..)) and handle ((__packed__)) like ((packed)) Change-Id: Ie60a51c3fa92b5009724a5b7c2932e361bf3490c Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/15921 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-01riscv: Update the gcc built-in macro __riscv__wxjstz
The architecture is determined by __riscv__ in the LZ4_copy8 function (located in src / commonlib / lz4_wrapper.c). __riscv exists in gcc7.1.1. But __riscv__ does not exist. Change-Id: I38fd41da9afd76c254f0c3d6984579c3790e5792 Signed-off-by: XiangWang <wxjstz@126.com> Reviewed-on: https://review.coreboot.org/20125 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Andrew Waterman <aswaterman@gmail.com> Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
2017-06-27commonlib/storage: Zero extend MMC capacityLee Leahy
Fix CID 1376472 detected by coverity. Zero extend the capacity instead of sign extending it. TEST=Build and run on reef Change-Id: I6aac422fb1dacb75e0cc44a94ff1f467ce9f529e Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/20392 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2017-06-20arch/x86/ebda: Change memcpy() to endian wrappersRyan Salsamendi
Change memcpy()s and memset()s to endian.h wrappers for consistency and safety. Add zero_n() wrapper to safely clear memory. Change-Id: If155d82608c81992f05eae4d2223de6f506e98c5 Signed-off-by: Ryan Salsamendi <rsalsamendi@hotmail.com> Reviewed-on: https://review.coreboot.org/20240 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-06-20commonlib/storage: Fix MMC buildLee Leahy
Add missing includes to build mmc.c. TEST=Build and run on Galileo Gen2 Change-Id: I0dea597272e5ece97843704a159aa546a8d77ff0 Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/20271 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-05-12commonlib: Move drivers/storage into commonlib/storageLee Leahy
Move drivers/storage into commonlib/storage to enable access by libpayload and indirectly by payloads. * Remove SD/MMC specific include files from include/device * Remove files from drivers/storage * Add SD/MMC specific include files to commonlib/include * Add files to commonlib/storage * Fix header file references * Add subdir entry in commonlib/Makefile.inc to build the SD/MMC driver * Add Kconfig source for commonlib/storage * Rename *DEVICE* to *COMMONLIB* * Rename *DRIVERS_STORAGE* to *COMMONLIB_STORAGE* TEST=Build and run on Galileo Gen2 Change-Id: I4339e4378491db9a0da1f2dc34e1906a5ba31ad6 Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/19672 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-04-28commonlib: Add ID for STORAGE_DATALee Leahy
TEST=Build and run on Reef Change-Id: I2f04a01e5e266422e3ef0d90541dc9d39471260c Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/19301 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-15 06:55:38 +0000