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2024-11-27commonlib/bsd/mem_chip_info: Add mem_chip_info_entry_density_bytesYu-Ping Wu
Add a helper function to get the mem_chip_info entry size. Change-Id: Ibf2a2006fb3e7772688b80807589e8f2d64d1147 Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85312 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yidi Lin <yidilin@google.com>
2024-11-13mem_chip_info: Add LPDDR5 enums to mem_chip_typeCrystal Guo
Add MEM_CHIP_LPDDR5 and MEM_CHIP_LPDDR5X to mem_chip_type enum. BUG=b:357743097 TEST=build pass Change-Id: Ic947932bacf9bef53f275685b2616601d0a6823c Signed-off-by: Crystal Guo <crystal.guo@mediatek.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85034 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-08-30drivers/efi/uefi_capsules.c: coalesce and store UEFI capsulesSergii Dmytruk
How it approximately works: (During a normal system run): 1. OS puts a capsule into RAM and calls UpdateCapsule() function of EFI runtime 2. If applying the update requires a reboot, EFI implementation creates a new CapsuleUpdateData* EFI variable pointing at the beginning of capsules description (not data, but description of the data) and does a warm reboot leaving capsule data and its description in RAM to be picked by firmware on the next boot process (After DEV_INIT:) 3. Capsules are discovered by checking for CapsuleUpdateData* variables 4. Capsule description in memory and capsule data is validated for sanity 5. Capsule data is coalesced into a continuous piece of memory (On BS_WRITE_TABLES via dasharo_add_capsules_to_bootmem() hook:) 6. Buffer with coalesced capsules is marked as reserved (On BS_WRITE_TABLES via lb_uefi_capsules() hook:) 7. coreboot table entry is added for each of the discovered capsules (In UEFI payload:) 8. CapsuleUpdateData* get removed 9. coreboot table is checked for any update capsules which are then applied Change-Id: I162d678ae5c504906084b59c1a8d8c26dadb9433 Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83422 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
2024-08-23region: Turn region_end() into an inclusive region_last()Nico Huber
The current region_end() implementation is susceptible to overflow if the region is at the end of the addressable space. A common case with the memory-mapped flash of x86 directly below the 32-bit limit. Note: This patch also changes console output to inclusive limits. IMO, to the better. Change-Id: Ic4bd6eced638745b7e845504da74542e4220554a Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79946 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2024-08-19drivers/efi: add optional ESRT-friendly coreboot table tagSergii Dmytruk
EFI System Resource Table (ESRT) is an informational structure that reports basic details about current system or device firmware. This is chiefly used to perform firmware updates. New CONFIG_DRIVERS_EFI_FW_INFO is off by default, enabling it adds DRIVERS_EFI_FW_{GUID,VERSION,LSV} to be used to specify firmware version/update information. Existing forms of versions wouldn't be sufficient because there is no universal way of converting string versions to 32-bit unsigned integers and there are no GUIDs or lowest supported versions. Change-Id: Ic1b768d7bed43edf7ca8e41552087734054de033 Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83421 Reviewed-by: Christian Walter <christian.walter@9elements.com> Reviewed-by: coreboot org <coreboot.org@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-08-19commonlib/bsd: Optimize strnlen()Julius Werner
This patch changes the strnlen() implementation to fix a small issue where we would dereference once more byte than intended when not finding a NUL-byte within the specified amount of characters. It also changes the implementation to rely on a pre-calculated end pointer rather than a running counter, since this seems to lead to slightly better assembly (one less instruction in the inner loop) on most architectures. Change-Id: Ic36768fd3a26e2b64143904e78cd0b52ba66898d Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83933 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2024-08-15commonlib/bsd/string: Fix pointer overflow for strnlen()Yu-Ping Wu
When `maxlen` is large (such as SIZE_MAX), the `end` pointer will overflow, causing strnlen() to incorrectly return 0. To not make the implementation over-complicated, fix the problem by using a counter. BUG=b:359951393 TEST=make unit-tests -j BRANCH=none Change-Id: Ic9d983b11391f5e05c2bceb262682aced5206f94 Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83914 Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
2024-08-14commonlib/bsd: Add strcat() and strncat() functionsYu-Ping Wu
An upcoming vboot feature [1] will need strcat() to be defined in string.h. Therefore, add strcat() and strncat() to commonlib/bsd. Remove those functions from libpayload. [1] https://chromium-review.googlesource.com/c/chromiumos/platform/vboot_reference/+/5650810 Change-Id: If02fce0eafb4f6fa01d8bab17d87a32360f4ac83 Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83765 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2024-08-14commonlib/bsd: Add strlen() and strnlen() functionsYu-Ping Wu
Add strlen() and strnlen() to commonlib/bsd by rewriting them from scratch, and remove the same functions from coreboot and libpayload. Note that in the existing libpayload implementation, these functions return 0 for NULL strings. Given that POSIX doesn't require the NULL check and that other major libc implementations (e.g. glibc [1]) don't seem to do that, the new functions also don't perform the NULL check. [1] https://github.com/bminor/glibc/blob/master/sysdeps/i386/strlen.c Change-Id: I1203ec9affabe493bd14b46662d212b08240cced Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83830 Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2024-08-13commonlib/include: Include <stdint.h> to fix 'SIZE_MAX' undeclared errorSubrata Banik
This change includes the <stdint.h> header file to resolve the compilation error "'SIZE_MAX' undeclared". This issue was introduced by commit hash af0d4bce65df277b56e495892dff1c712ed76ddd (region: Introduce region_create() functions). TEST=Able to build google/rex. Change-Id: I0dbd839e3573d5c74375911903c8f9d6a66bbf28 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83886 Reviewed-by: Jakub Czapiga <czapiga@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-08-11region: Introduce region_create() functionsNico Huber
We introduce two new functions to create region objects. They allow us to check for integer overflows (region_create_untrusted()) or assert their absence (region_create()). This fixes potential overflows in region_overlap() checks in SMI handlers, where we would wrongfully report MMIO as *not* overlapping SMRAM. Also, two cases of strtol() in parse_region() (cbfstool), where the results were implicitly converted to `size_t`, are replaced with the unsigned strtoul(). FIT payload support is left out, as it doesn't use the region API (only the struct). Change-Id: I4ae3e6274c981c9ab4fb1263c2a72fa68ef1c32b Ticket: https://ticket.coreboot.org/issues/522 Found-by: Vadim Zaliva <lord@digamma.ai> Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79905 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2024-08-08commonlib/device_tree.c: Remove incorrect warningMaximilian Brune
Currently a warning is printed even if the maximum amount of nodes is not exceeded. Remove the warning, since in most cases the maximum amount of nodes for a given prefix is usually well known. For example the /cpu nodes always have a maximum of CONFIG_MAX_CPUS. One may also just want to read the first X amount of nodes matching a given prefix. Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com> Change-Id: Ic1111e8acb72ea1e9159da0d8386f40cbbdbc63f Reviewed-on: https://review.coreboot.org/c/coreboot/+/83085 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2024-07-26commonlib/device_tree.c: Add read reg property helperMaximilian Brune
Add a helper function to read the reg property from an unflattened device tree. It also factors out the common code into a new function called `read_reg_prop`. Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com> Change-Id: I7846eb8af390d709b0757262025cb819e9988699 Reviewed-on: https://review.coreboot.org/c/coreboot/+/83457 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2024-07-16commonlib: Add ELOG_TYPE_FW_LATE_SOL eventLog typeSubrata Banik
Add a new eventLog type of ELOG_TYPE_FW_LATE_SOL to support logging when we show late (from payload) Signs Of Life (SOL) to the user. BUG=b:305898363 TEST=Event shows in eventlog tool after CSE sync: ``` Late Sign of Life | CSE Sync Late SOL Screen Shown ``` Change-Id: Ibbe9f37a791e5c2a0c6e982942cf3043a2bd4b45 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83461 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Dinesh Gehlot <digehlot@google.com>
2024-07-01commonlib/bsd/lz4_wrapper.c: Fix misaligned accessMaximilian Brune
Currently the HiFive Unleashed produces the following exception: [DEBUG] Exception: Load address misaligned [DEBUG] Hart ID: 0 [DEBUG] Previous mode: machine [DEBUG] Bad instruction pc: 0x080010d0 [DEBUG] Bad address: 0x08026ab3 [DEBUG] Stored ra: 0x080010c8 [DEBUG] Stored sp: 0x08010cc8 The coreboot LZ4 decompression code does some misaligned access during decompression which the FU540 apparently does not support in SRAM. Make the compiler generate code that adheres to natural alignment by fixing the LZ4_readLE16() function and creating LZ4_readLE32(). Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com> Change-Id: Id165829bfd35be2bce2bbb019c208a304f627add Reviewed-on: https://review.coreboot.org/c/coreboot/+/81910 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-06-28include/device_tree.h: Fix function name fdt_node_nameMaximilian Brune
Rename fdt_node_name to the actual function name and also rename the references. Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com> Change-Id: I527146df26264a0c3af1ad01c21644d751b80236 Reviewed-on: https://review.coreboot.org/c/coreboot/+/83084 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-06-27commonlib/device_tree: Improve node and property allocation speedJulius Werner
Now that the device tree code has been made available in libpayload, we should reintroduce the node and property allocation optimization for libpayload's memory allocator that was originally dropped when porting this code from depthcharge to coreboot. On a Qualcomm SC7180 unflattening a normal ChromeOS kernel device tree, this saves roughly ~145ms. The total scratch space used is about ~1350 nodes and ~5200 properties, so we leave a little room to grow with the constants hardcoded here. Change-Id: I0f4d80a8b750febfb069b32ef47304ccecdc35af Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83208 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2024-06-22treewide: Move device_tree to commonlibMaximilian Brune
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com> Change-Id: I990d74d9fff06b17ec8a6ee962955e4b0df8b907 Reviewed-on: https://review.coreboot.org/c/coreboot/+/77970 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-06-21commonlib/fsp_relocate: Add PE32+ supportPatrick Rudolph
Add support for PE32+ binaries which can be found on X64 UEFI builds. TEST: Able to relocate and boot a X64 FSP. Change-Id: I22586834d7c9f3ab3a5e31bba957584587ec14e0 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82680 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-06-11treewide: Move skip_atoi function to commonlibKapil Porwal
BUG=none TEST=Build and verify on Screebo TEST=make unit-tests ``` $ make tests/commonlib/bsd/string-test [==========] tests_commonlib_bsd_string-test(tests): Running 1 test(s). [ RUN ] test_skip_atoi [ OK ] test_skip_atoi [==========] tests_commonlib_bsd_string-test(tests): 1 test(s) run. [ PASSED ] 1 test(s). ``` Change-Id: Ifaaa80d0c696a625592ce301f9e3eefb2b4dcd98 Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82910 Reviewed-by: Jakub Czapiga <czapiga@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-05-08commonlib/timestamp_serialized: Define VB_AUXFW_SYNC_DONE timestampKarthikeyan Ramasubramanian
Define a new timestamp to identify the completion of Auxiliary Firmware Sync. Without that, it gets accounted into a different timestamp ID in a misleading way. BUG=None TEST=Build Brox BIOS image and boot to OS. Confirm the timestamp is recorded in cbmem. Change-Id: Icd01c68a5848e2aed7bbdcc794987bc780e78dab Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82230 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Shelley Chen <shchen@google.com>
2024-04-11tree: Drop unused <string.h>Elyes Haouas
Change-Id: I0e216cbc4acf9571c65c345a1764e74485f89438 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81818 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-04-04commonlib: Simplify FSP header inclusionSubrata Banik
Include `fsp_header.h` from vendorcode for dynamic FSP_INFO_HEADER selection. BUG=b:242829490 TEST=google/rex0 builds successfully with 64-bit FSP. Change-Id: If165e0517752f320d898cf82f298aa9f5699ae86 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81624 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-30commonlib: Remove blank lines before '}' and after '{'Elyes Haouas
Change-Id: I57686e68b4b1bdb28a15b69e55b71c98b0b53a1f Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81492 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-03-24commonlib: Add timestamp entries for eSOLSubrata Banik
This patch adds timestamp entries for eSOL (early Sign-Off Life). This is critical to tracking the panel initialization time while rendering the eSOL screen. TEST=Able to build and boot google/omnigul. 555: started early sign-off life (eSOL) notification 643,694 (40) 556: finished early sign-off life (eSOL) notification 1,072,143 (428,449) Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I33f7f3a8622600ef23163faf45e2da7b96d6bbdb Reviewed-on: https://review.coreboot.org/c/coreboot/+/81386 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-19soc/intel/xeon_sp: Drop RMRR entry for USBPatrick Rudolph
Drop RMRR entry for XHCI controller since it's not under BIOS control. There's no USB-PS/2 emulation done in SMM, hence it's not needed. TEST=intel/archercity CRB Change-Id: I5afd68371d71a00988fe0f8a6045ec5ce2adc6a1 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81297 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shuo Liu <shuo.liu@intel.com>
2024-03-17commonlib: list: Include <stdint.h>Julius Werner
The list macros use uintptr_t, so they need to include the header that declares it. Change-Id: I56b2a988bb11d40c8761717bcd02a8199c077046 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81288 Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-15treewide: Move stdlib.h to commonlibMaximilian Brune
This patch moves commonlib/stdlib.h -> commonlib/bsd/stdlib.h, since all code is BSD licensed anyway. It also moves some code from libpayloads stdlib.h to commonlib/bsd/stdlib.h so that it can be shared with coreboot. This is useful for a subsequent commit that adds devicetree.c into commonlib. Also we don't support DMA on arm platforms in coreboot (only libpayload) therefore `dma_malloc()` has been removed and `dma_coherent()` has been moved to architecture specific functions. Any architecture that tries to use `dma_coherent()` now will get a compile time error. In order to not break current platforms like mb/google/herobrine which make use of the commonlib/storage/sdhci.c controller which in turn uses `dma_coherent` a stub has been added to arch/arm64/dma.c. Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com> Change-Id: I3a7ab0d1ddcc7ce9af121a61b4d4eafc9e563a8a Reviewed-on: https://review.coreboot.org/c/coreboot/+/77969 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2024-03-13cbfs: Remove broken remnants of PAYLOAD_INFO featureJulius Werner
PAYLOAD_INFO is a very old feature that can add a key/value information section to a payload file. It seems to have only ever been generated by coreinfo and never really read by anything. Since CB:1721 in 2012, the feature has been inadvertently broken in practice since the `.note.pinfo` sections that contain the information get discarded from the payload before cbfstool gets to see them. Since CB:28647 in 2018, support for the section in the SELF loader was (inadvertently?) dropped, so if someone actually fed cbfstool a payload ELF that did have a `.note.pinfo` section, modern coreboot would refuse to boot the payload entirely (which is probably not a good state to leave things in). This patch removes the code to generate PAYLOAD_INFO entries entirely, but leaves the support to parse and extract those sections from old payloads in place in cbfstool. Change-Id: I40d8e9b76a171ebcdaa2eae02d54a1ca5e592c85 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81087 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2024-03-08drivers/intel/fsp2_0: Add limited to 32-bits FSP 2.4 supportJeremy Compostella
Intel Firmware Support Package 2.4 specification (document 736809) brings some significant changes compared to version 2.3 (document 644852): 1. It supports FSP-M multi-phase init. Some fields have been added to the FSP header data structure for this purpose. 2. The `FSPM_ARCH2_UPD' and `FSPS_ARCH2_UPD' data structures must be used in place of `FSPM_ARCH_UPD' and `FSPS_ARCH_UPD' respectively. 3. It support 64-bits FSP but 64-bits support will be provided by subsequent patch. Note that similarly to what is done for silicon initialization, timestamps and post-codes are used during the memory initialization multi-phase. [736809] https://cdrdv2-public.intel.com/736809/736809_FSP_EAS_v2.4_Errata_A.pdf [644852] https://cdrdv2-public.intel.com/644852/644852_2.3_Firmware-Support-Package-External-Architecture-Specification.pdf TEST=verified on Lunar Lake RVP board (lnlrvp) Change-Id: I1c24d26e105c3dcbd9cca0e7197ab1362344aa97 Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80275 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Dinesh Gehlot <digehlot@google.com>
2024-02-24treewide: Move list.h to commonlibMaximilian Brune
It is needed in order to move device_tree.c into commonlib in a subsequent commit. Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com> Change-Id: I16eb7b743fb1d36301f0eda563a62364e7a9cfec Reviewed-on: https://review.coreboot.org/c/coreboot/+/77968 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-02-08commonlib: Change GCD function to always use 64 bitsJulius Werner
It seems that we have some applications where we need to calculate a GCD in 64 bits. Now, we could instantiate the algorithm multiple times for different bit width combinations to be able to use the most efficient one for each problem... but considering that the function usually only gets called once per callsite per stage, and that software emulation of 64-bit division on 32-bit systems doesn't take *that* long either, we would probably usually be paying more time loading the second instance of the function than we save with faster divisions. So let's just make things easy and always do it in 64-bit and then nobody has to spend time thinking on which version to call. Change-Id: I028361444c4048a0d76ba4f80c7334a9d9983c87 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80319 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yidi Lin <yidilin@google.com>
2024-02-02commonlib: Add assembly optimization for ipchksum() on x86Julius Werner
This patch adds a bit of optimized assembly code to the ipchksum() algorithm for x86 targets in order to take advantage of larger load sizes and the add-with-carry instruction. The same assembly (with one minor manual tweak) works for both 32 and 64 bit mode (with most of the work being done by GCC which automatically inserts `rax` or `eax` in the inline assembly depending on the build target). Change-Id: I484620dc14679ff5ca02b2ced2f84650730a6efc Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80255 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-02-02commonlib: Add assembly optimization for ipchksum() on arm64Julius Werner
This patch adds a bit of optimized assembly code to the ipchksum() algorithm for arm64 targets in order to take advantage of larger load sizes and the add-with-carry instruction. This improves execution speed on a Cortex-A75 by more than 20x. Change-Id: I9c7bbc9d7a1cd083ced62fe9222592243a796077 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80254 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Yidi Lin <yidilin@google.com>
2024-02-02lib: Move IP checksum to commonlibJulius Werner
This patch moves the IP checksum algorithm into commonlib to prepare for it being shared with libpayload. The current implementation is ancient and pretty hard to read (and does some unnecessary questionable things like the type-punning stuff which leads to suboptimal code generation), so this reimplements it from scratch (that also helps with the licensing). This algorithm is prepared to take in a pre-calculated "wide" checksum in a machine-register-sized data type which is then narrowed down to 16 bits (see RFC 1071 for why that's valid). This isn't used yet (and the code will get optimized out), but will be used later in this patch series for architecture-specific optimization. Change-Id: Ic04c714c00439a17fc04a8a6e730cc2aa19b8e68 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80251 Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jakub Czapiga <czapiga@google.com>
2024-01-24acpi,arch,commonlib: Rename Makefiles from .inc to .mkMartin Roth
The .inc suffix is confusing to various tools as it's not specific to Makefiles. This means that editors don't recognize the files, and don't open them with highlighting and any other specific editor functionality. This issue is also seen in the release notes generation script where Makefiles get renamed before running cloc. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: Ice5dadd3eaadfa9962225520a3a75b05b44518ca Reviewed-on: https://review.coreboot.org/c/coreboot/+/80066 Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-01-22commonlib/bsd/compiler.h: Define __section(section) macroYu-Ping Wu
Define __section(section) to be a shorthand for __attribute__((__section__(section))). Change-Id: I67a37e5b2aae0bfa68b0319c477ab5d6c55e6501 Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80137 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2023-12-20commonlib/bsd: Tag CBMEM IDs deprecated for crashlogPratikkumar Prajapati
These IDs are not used as crashlog data is not stored in CBMEM now. (Ref CL: I43bb61485b77d786647900ca284b7f492f412aee Title: soc/intel/common,mtl: Refactor BERT generation flow for crashlog) BUG=b:298234592 TEST=Able to build REX. Change-Id: Ie38571dece89a995d582099d34f0a1dd57cb936f Signed-off-by: Pratikkumar Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78259 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-12-06vendorcode/amd/opensil: Add initial setup and API callsArthur Heymans
- First a console is set up for opensil. - After that a region in CBMEM is reserved and passed to opensil which will use it as a buffer for input/output information. - Finally opensil is called and the return value handled. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I4833a5a86034a13e6be102a6b68c3bb54108bc9a Reviewed-on: https://review.coreboot.org/c/coreboot/+/76515 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-12-06commonlib/bsd: Use tabs instead of whitespacesVarshit Pandya
Change-Id: I05e7ba10e499ea1e824bdd6c87df05fc5a0864f8 Signed-off-by: Varshit Pandya <pandyavarshit@gmail.com> Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79400 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-11-09Allow to build romstage sources inside the bootblockArthur Heymans
Having a separate romstage is only desirable: - with advanced setups like vboot or normal/fallback - boot medium is slow at startup (some ARM SOCs) - bootblock is limited in size (Intel APL 32K) When this is not the case there is no need for the extra complexity that romstage brings. Including the romstage sources inside the bootblock substantially reduces the total code footprint. Often the resulting code is 10-20k smaller. This is controlled via a Kconfig option. TESTED: works on qemu x86, arm and aarch64 with and without VBOOT. Change-Id: Id68390edc1ba228b121cca89b80c64a92553e284 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55068 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-11-04commonlib: Add GCD functionYidi Lin
Implement a simple GCD function. BUG=b:307790895 TEST=emerge-geralt coreboot TEST=make tests/commonlib/bsd/gcd-test Change-Id: I21819cda4299b3809b8ca7a95cbdc6a87e4b3481 Signed-off-by: Yidi Lin <yidilin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78798 Reviewed-by: Martin L Roth <gaumless@gmail.com> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-11-02commonlib/fsp_relocate: Fix potential NULL pointer dereferenceJeremy Compostella
Commit 1df1cf994aa9 ("commonlib/fsp_relocate: add PE32 section support") introduced a potential NULL pointer dereference if there is PE32 binary to relocate outside of the first firmware volume. The `fih_offset' pointer was used as an output variable but now it is also used as an input variable to pass the FSP information header to the `pe_relocate()' function. This commit resolves this potential NULL-pointer dereference by passing the pointer systematically and without affecting the logic as it is only set if it has not been set before. Change-Id: I9fad90a60854d5f050aa044a5c0b3af91c99df4a Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78501 Reviewed-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-10-06cbfs: Restore 32-bit padding in cbfs_headerIvan Jager
It was changed from a fixed size-1 array to a flexible array in commit 242bac0e162c ("…: Use C99 flexible arrays") which resulted in a change to the serialized format as the header size was no longer the same. That broke other tools that read CBFS files, like diffoscope https://github.com/NixOS/nixpkgs/issues/256896 Change-Id: I4199dcc4823469c5986ac967a55b1c85cc62f780 Signed-off-by: Ivan Jager <aij+git@mrph.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78239 Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Patrick Georgi <patrick@coreboot.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-10-04{commonlib, libpayload}: Add "has_external_display" in coreboot tableSubrata Banik
This patch introduces a new coreboot table entry named "has_external_display" to understand if external display is attached. This information is useful to prevent graceful shutdown by payload when the LID is closed but an external display is present. This piece of the information will be gathered by coreboot and passed into the payload using this new entry aka external_display because payload (i.e., deptcharge) doesn't have any other way to determine if external display is available. BUG=b:299137940 TEST=Able to build and boot google/rex. w/o this patch: LID closed and external display attached (HDMI) in developer mode (GBB 0x39): > System is powered off by depthcharge w/ this patch: LID closed and external display attached (HDMI) in developer mode (GBB 0x39): > Booted to OS and device is alive/usable Change-Id: I0fa7eee4c5a50371a7a66c6ca1ac2c7d046d010b Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77796 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-25commonlib: Make CBMEM_ID_CSE_BP_INFO little endian, fix id for stringSubrata Banik
This patch fixes the mistake introduced with 'commit 17cea380d985 ("commonlib: Add CBMEM ID to store CSE Boot Partition Info")' where single CBMEM ID name `CBMEM_ID_CSE_INFO` is associated with two different name description. Additionally, use little endian format for `CBMEM_ID_CSE_INFO` cbmem id. TEST=Build and boot google/rex. Able to fix the issue introduced in commit 17cea380d985 while running cbmem --list and verify that the associated name string is proper. Change-Id: I4235f1f6881ab86ccb252065e922d5d526f7f1f7 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78110 Reviewed-by: Patrick Georgi <patrick@coreboot.org> Reviewed-by: Dinesh Gehlot <digehlot@google.com> Reviewed-by: sridhar siricilla <siricillasridhar@gmail.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Krishna P Bhat D <krishna.p.bhat.d@intel.com>
2023-09-23commonlib: Add CBMEM ID to store CSE Boot Partition InfoKrishna Prasad Bhat
PSR data is created and stored in CSE data partition. In platforms that employ CSE Lite SKU firmware, a firmware downgrade involves clearing of CSE data partition which results in PSR data being lost. In order to backup PSR data before initiating firmware downgrade, CSE Lite firmware supports a command to do this. This command works only after memory has been initialized. So the CSE firmware downgrade can be done only in post-RAM stage. CSE firmware sync actions will be moved to early ramstage to support this. Moving CSE firmware sync actions to ramstage results in cse_get_bp_info command taking additional boot time of ~45-55ms. To avoid this, cse_get_bp_info will be sent in early romstage and the response will be stored in cbmem to avoid sending the command again, and re-use in ramstage. This patch adds a CBMEM ID to store this CSE Boot Partition Info response in cbmem. BUG=b:273207144 Change-Id: I914befadab4ad0ac197435e2a2c4343a796b2b1b Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com> Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78052 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: sridhar siricilla <siricillasridhar@gmail.com>
2023-09-13soc/intel/cmd/blk/cse: Shorten CBMEM field name for better alignmentDinesh Gehlot
This patch shortens the name of the CBMEM field CBMEM_ID_CSE_INFO from "CSE SPECIFIC INFORMATION" to "CSE SPECIFIC INFO" to improve the alignment of the text on the screen. The functionality of the field has not been changed. BUG=NA Test=Boot verified on rex board. Change-Id: I39c716dab7d02d49e7d552cff77d544a1c168433 Signed-off-by: Dinesh Gehlot <digehlot@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77743 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-08arch to drivers/intel: Fix misspellings & capitalization issuesMartin Roth
Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: Ic52f01d1d5d86334e0fd639b968b5eed43a35f1d Reviewed-on: https://review.coreboot.org/c/coreboot/+/77633 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-29commonlib: Add ELOG_TYPE_FW_SPLASH_SCREEN eventLogSubrata Banik
This patch adds a new eventLog type ELOG_TYPE_FW_SPLASH_SCREEN to support logging when we show firmware splash screen to the user. BUG=b:284799726 TEST=Event shows in eventlog when user selects BMP_LOGO and HAVE_FSP_LOGO_SUPPORT configs. Change-Id: Id1572ecb83ca025ff65608e7ae4f3a065024f6d4 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77507 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-25commonlib: Add PSR backup eventlog typesKrishna Prasad Bhat
Add new eventlog types to support logging of Platform Service Record (PSR) backup related messages. Eventlog entries are added on PSR data backup success/failure and also when PSR data is lost. BRANCH=None BUG=b:273207144 TEST=Verify elog event added after PSR data backup command is sent cse_lite: PSR_HECI_FW_DOWNGRADE_BACKUP command sent ... ELOG: Event(B9) added with size 10 at 2023-07-27 06:44:49 UTC Change-Id: I01ce3f7ea24ff0fdbb7a202ec3c75973b59d4c14 Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com> Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77004 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-18commonlib: Remove unused CBMEM IDSubrata Banik
This patch removes unused CBMEM ID named `CBMEM_ID_CSE_PARTITION_VERSION`. BUG=b:285405031 TEST=Able to build and boot google/rex w/o any compilation error. Change-Id: I83f53b7f64bdef62a8ee2061d5a9c9e22bc4b8a4 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77179 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-18soc/intel/cmn/cse: Refactor CSE RW FW Version implementationSubrata Banik
This patch introduces a CSE firmware specific data in order to store Intel CSE and associated firmware related information which requires a sync between Pre-RAM and Post-RAM phase. This information will be used further to retrieve currently running CSE RW firmware instead of fetching the version information by sending a HECI cmd (which consumes 7ms-15ms depending upon the CSE operational state). Current implementation attempts to simply the CSE RW FW version store and retrieval operations as below * CSE sync in romstage (aka Pre-RAM) - Relying on .bss segment to store the CSE info data in absence of real physical memory and sync back into the CBMEM once available (after FSP-M exits). * CSE sync in ramstage (aka Post-RAM) - Directly stored the CSE RW version into the CBMEM (as CBMEM is online). BUG=b:285405031 TEST=Able to build and boot google/rex. Verified CSE RW FW version (for LITE SKU) is getting displayed without impacting the boot time. w/o this patch: 10:start of ramstage         722,257 (43) 17:starting LZ4 decompress (ignore for x86)  723,777 (1,520) w/ this patch: 10:start of ramstage                         722,257 (43) 17:starting LZ4 decompress (ignore for x86)  723,777 (1,520) Change-Id: Ia873af512851a682cf1fac0e128d842562a316ab Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77174 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
2023-08-17soc/intel: Update all references to ESE as ISSEUsha P
Intel has rebranded ESE as ISSE (Intel Silicon Security Engine),so all references to ESE is updated to ISSE in the current coreboot code. BUG=None TEST=Build all the variants based on Intel Meteor Lake SoC Signed-off-by: Usha P <usha.p@intel.com> Change-Id: I1f8785704706d56a35e94a0f3386bc551cd1f263 Reviewed-on: https://review.coreboot.org/c/coreboot/+/77241 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-08-14commonlib,console,nb,sb,security: Add SPDX licenses to MakefilesMartin Roth
To help identify the licenses of the various files contained in the coreboot source, we've added SPDX headers to the top of all of the .c and .h files. This extends that practice to Makefiles. Any file in the coreboot project without a specific license is bound to the license of the overall coreboot project, GPL Version 2. This patch adds the GPL V2 license identifier to the top of all makefiles in the commonlib, console, northbridge, security, and southbridge directories that don't already have an SPDX license line at the top. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I02804a10d0b0355e41271a035613d9f3dfb122f8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68985 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2023-08-05commonlib/fsp_relocate: Fix pe_relocate() return value on successJeremy Compostella
Similarly to te_relocate(), on success pe_relocate() should return 0. It has never been an issue so far as pe_relocate() return value is not tested. Change-Id: I8e531662952d12e1f0ffa34042dab778ea602bfc Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76891 Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Anil Kumar K <anil.kumar.k@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2023-08-01commonlib/tpm_log_serialized.h: Use C99 flexible arraysElyes Haouas
Use C99 flexible arrays instead of older style of one-element or zero-length arrays. It allows the compiler to generate errors when the flexible array does not occur at the end in the structure. Change-Id: I16ac584781214350355e0625f8a2eca39a37cf85 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76841 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-08-01commonlib/timestamp_serialized.h: Use C99 flexible arraysElyes Haouas
Use C99 flexible arrays instead of older style of one-element or zero-length arrays. It allows the compiler to generate errors when the flexible array does not occur at the end in the structure. Change-Id: Ibd1e4bc96a2f5eea746328a09d123629c20b272c Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76847 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-07-31commonlib/bsd/cbfs_serialized.h: Use C99 flexible arraysElyes Haouas
Use C99 flexible arrays instead of older style of one-element or zero-length arrays. It allows the compiler to generate errors when the flexible array does not occur at the end in the structure. Change-Id: I00807a435a21e078c89f797cfd0b00d03604ea0e Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76786 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-30include/commonlib/bsd/mem_chip_info.h: Use C99 flexible arraysElyes Haouas
Use C99 flexible arrays instead of older style of one-element or zero-length arrays. It allows the compiler to generate errors when the flexible array does not occur at the end in the structure. Change-Id: Ia1d597c0e3e86db8c13829e58a8a27d9de1480b4 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76788 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-30commonlib/fsp_relocate.c: Use C99 flexible arraysElyes Haouas
Use C99 flexible arrays instead of older style of one-element or zero-length arrays. It allows the compiler to generate errors when the flexible array does not occur at the end in the structure. Change-Id: I52b5a83e7e484889bfef5a4e45a0279fadd58890 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76784 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-07-30commonlib/coreboot_tables.h: Use C99 flexible arraysElyes Haouas
Use C99 flexible arrays instead of older style of one-element or zero-length arrays. It allows the compiler to generate errors when the flexible array does not occur at the end in the structure. Change-Id: I495605190b2c6cd11c7f78727ab4611e10b4d9d3 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76785 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-07-04util/cbmem: add parsing of TPM logs per specsSergii Dmytruk
CBMEM can contain log in different forms (at most one is present): - coreboot-specific format (CBMEM_ID_TPM_CB_LOG exported as LB_TAG_TPM_CB_LOG) - TPM1.2 format (CBMEM_ID_TCPA_TCG_LOG) - TPM2 format (CBMEM_ID_TPM2_TCG_LOG) The last two follow specifications by Trusted Computing Group, but until now cbmem couldn't print them. These formats were added not so long ago in: - commit 4191dbf0c9a5 ("security/tpm: add TPM log format as per 1.2 spec") - commit 53db677586e3 ("security/tpm: add TPM log format as per 2.0 spec") These changes make cbmem utility check for existence of TPM1.2/TPM2 logs in CBMEM and add code necessary for parsing and printing of their entries. TEST=`cbmem -L` for CONFIG_TPM1=y case TCPA log: Specification: 1.21 Platform class: PC Client TCPA log entry 1: PCR: 2 Event type: Action Digest: 5622416ea417186aa1ac32b32c527ac09009fb5e Event data: FMAP: FMAP TEST=`cbmem -L` for CONFIG_TPM2=y case TPM2 log: Specification: 2.00 Platform class: PC Client TPM2 log entry 1: PCR: 2 Event type: Action Digests: SHA256: 68d27f08cb261463a6d004524333ac5db1a3c2166721785a6061327b6538657c Event data: FMAP: FMAP Change-Id: Ib76dc7dec56dd1789a219539a1ac05a958f47a5c Ticket: https://ticket.coreboot.org/issues/425 Signed-off-by: Krystian Hebel <krystian.hebel@3mdeb.com> Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68749 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-25commonlib/post_codes.h: Fix POST_EXIT_PCI_SCAN_BUS descriptionlilacious
Description of POST_EXIT_PCI_SCAN_BUS indicates the opposite of what its name suggests. Secondly, POST_ENTER_PCI_SCAN_BUS and POST_EXIT_PCI_SCAN_BUS have identical comments, which appears to be a copy-paste issue. Change the description accordingly. Change-Id: Ifc920651255bacf033cac39f0208d817f9ee84fc Signed-off-by: lilacious <yuchenhe126@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76047 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-23commonlib/console/post_code.h: Change post code prefix to POSTCODElilacious
The prefix POSTCODE makes it clear that the macro is a post code. Hence, replace related macros starting with POST to POSTCODE and also replace every instance the macros are invoked with the new name. The files was changed by running the following bash script from the top level directory. sed -i'' '30,${s/#define POST/#define POSTCODE/g;}' \ src/commonlib/include/commonlib/console/post_codes.h; myArray=`grep -e "^#define POSTCODE_" \ src/commonlib/include/commonlib/console/post_codes.h | \ grep -v "POST_CODES_H" | tr '\t' ' ' | cut -d ' ' -f 2`; for str in ${myArray[@]}; do splitstr=`echo $str | cut -d '_' -f2-` grep -r POST_$splitstr src | \ cut -d ':' -f 1 | xargs sed -i'' -e "s/POST_$splitstr/$str/g"; grep -r "POST_$splitstr" util/cbfstool | \ cut -d ':' -f 1 | xargs sed -i'' -e "s/POST_$splitstr/$str/g"; done Change-Id: I25db79fa15f032c08678f66d86c10c928b7de9b8 Signed-off-by: lilacious <yuchenhe126@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76043 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-06-23{commonlib/drivers}: Have option to store MRC version inside CBMEMSubrata Banik
This patch introduces CBMEM ID to store the MRC version (similar to existing implementation that stores the FSP-M version inside CBMEM ID) inside cbmem so the version information is available across the different coreboot stages. For example: * romstage: Use the CBMEM ID version information to check if the MRC cache is valid and need to erase the MRC cache * ramstage: Use the CBMEM ID to store the MRC cache into the non-volatile space. BUG=b:261689642 TEST=Able to build and boot google/rex and dump the MRC version as below. cbmem --list CBMEM table of contents: NAME ID START LENGTH ... 21. MRC VERSION 5f43524d 75ffeb60 00000004 ... localhost ~ # cbmem -r 5f43524d | hexdump 00000000 01 12 07 00 Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I91f735239b33c6f8ba41c076048903e4b213c6a2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75921 Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-06soc/intel/common/crashlog: Add support for IOE diePratikkumar Prajapati
Intel Meteor Lake SOC has a separate I/O Expander (IOE) die. SRAM from this IOE die contains crashlog records for the IPs of the IOE die. This patch adds functions with empty implementation using __weak attribute for IOE die related crashlog, changes common data structures while maintaining backwards compatibility, and support for filling IOE crashlog records, guarded by SOC_INTEL_IOE_DIE_SUPPORT config and makes cl_get_pmc_sram_data function as weak because it needs SOC specific implementation. Bug=b:262501347 TEST=Able to build. With Meteor Lake SOC related patch, able to capture and decode crashlog Change-Id: Id90cf0095258c4f7003e4c5f2564bb763e687b75 Signed-off-by: Pratikkumar Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75475 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-05-28commonlib/bsd/tpm_log_defs.h: replace macro with enumHimanshu Sahdev
replace multiple existing EV_* defines with enum ec_enum. Signed-off-by: Himanshu Sahdev <himanshu.sahdev@intel.com> Change-Id: Id58fc12134915cbeb41cccb54aae9bc3f7dde4b8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75324 Reviewed-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-05-15commonlib: compiler.h: Add __printf macroJeremy Compostella
This patch adds the `__printf' macro to comply with checkpatch following warning: Prefer __printf(1, 2) over __attribute__((format(printf, 1, 2))) BRANCH=firmware-brya-14505.B TEST=Successful compilation with `__printf(1, 2)' instead of `__attribute__((format(printf, 1, 2)))' Change-Id: Ic2d90478ab0955c2ad0955e8cff5be76bfb2e741 Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75159 Reviewed-by: Cliff Huang <cliff.huang@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-04-21{commonlib, soc/intel/cmn/cse}: Store CSE firmware version into CBMEMSubrata Banik
The patch implements an API that stores the CSE firmware version in the CBMEM table. The API will be called from RAMSTAGE based on boot state machine BS_PRE_DEVICE/BS_ON_EXIT Additionally, renamed ramstage_cse_fw_sync() to ramstage_cse_misc_ops() in order to add more CSE related operations at ramstage. This patch also adds a configuration option, 'SOC_INTEL_STORE_CSE_FPT_PARTITION_VERSION', which enables the storage of firmware version information in CBMEM memory. This information can be used to identify the firmware version that is currently installed on the system. The option depends on the `DRIVERS_INTEL_ISH` config and platform should be flexible enough to opt out from enabling this feature. The cost of sending HECI command to read the CSE FPT is significant (~200ms) hence, the idea is to read the CSE RW version on every cold reset (to cover the CSE update scenarios) and store into CBMEM to avoid the cost of resending the HECI command in all consecutive warm boots. Later boot stages can just read the CBMEM ID to retrieve the ISH version if required. Finally, ensure this feature is platform specific hence, getting enabled for the platform that would like to store the ISH version into the CBMEM and parse to perform some additional work. BUG=b:273661726 TEST=Able to build and boot google/marasov. Signed-off-by: Dinesh Gehlot <digehlot@google.com> Change-Id: I923049d2f1f589f87e1a29e1ac94af7f5fccc2c8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74256 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-04-04commonlib: Add new "DMU load completed" TSBora Guvendik
990:CSME ROM started execution 0 944:CSE sent 'Boot Stall Done' to PMC 47,000 945:CSE started to handle ICC configuration 225,000 (178,000) 946:CSE sent 'Host BIOS Prep Done' to PMC 225,000 (0) 947:CSE received 'CPU Reset Done Ack sent' from PMC 516,000 (291,000) 991:Die Management Unit (DMU) load completed 587,000 (71,000) 0:1st timestamp 597,427 (10,427) BUG=b:259366109 TEST=Boot to OS, check cbmem -t Change-Id: I4d2da820f39c40ea864d15d25a94a68497b2af3d Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74047 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-03commonlib/coreboot_tables.h: Fix typo in enum type nameAngel Pons
Fix a typo in an enum's type name, "tmp" ---> "tpm". The enum type is not used anywhere in the coreboot tree. Change-Id: Ie7529e7ee80aa9661ec053da8211c2c3295b3942 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74120 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer Reviewed-by: Benjamin Doron <benjamin.doron00@gmail.com> Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
2023-04-02commonlib/coreboot_tables.h: Replace spaces with tabsAngel Pons
Indent with tabs for the sake of consistency with the rest of the code. Change-Id: Ibd325a7a8348cc1f9023e54dceab40d02a0df233 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74119 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Benjamin Doron <benjamin.doron00@gmail.com> Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
2023-03-04security/tpm: add TPM log format as per 2.0 specSergii Dmytruk
Used by default for all boards with TPM2 which don't specify log format explicitly. Change-Id: I0fac386bebab1b7104378ae3424957c6497e84e1 Ticket: https://ticket.coreboot.org/issues/422 Ticket: https://ticket.coreboot.org/issues/423 Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68748 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2023-03-04security/tpm: add TPM log format as per 1.2 specSergii Dmytruk
Used by default for all boards with TPM1 which don't specify log format explicitly. Ticket: https://ticket.coreboot.org/issues/423 Change-Id: I89720615a75573d44dd0a39ad3d7faa78f125843 Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68747 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2023-03-03lib: set up specific purpose memory as LB_MEM_SOFT_RESERVEDJonathan Zhang
CXL (Compute Express Link) [1] is a cache-coherent interconnect standard for processors, memory expansion and accelerators. CXL memory is provided through CXL device which is connected through CXL/PCIe link, while regular system memory is provided through DIMMs plugged into DIMM slots which are connected to memory controllers of processor. With CXL memory, the server's memory capacity is increased. CXL memory is in its own NUMA domain, with longer latency and added bandwidth, comparing to regular system memory. Host firmware may present CXL memory as specific purpose memory. Linux kernel dax driver provides direct access to such differentiated memory. In particular, hmem dax driver provides direct access to specific purpose memory. Specific purpose memory needs to be represented in e820 table as soft reserved, as described in [2]. Add IORESOURCE_SOFT_RESERVE resource property to indicate (memory) resource that needs to be soft reserved. Add soft_reserved_ram_resource macro to allow soc/mb code to add memory resource as soft reserved. [1] https://www.computeexpresslink.org/ [2] https://web.archive.org/web/20230130233752/https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?h=v5.10.32&id=262b45ae3ab4bf8e2caf1fcfd0d8307897519630 Signed-off-by: Jonathan Zhang <jonzhang@fb.com> Change-Id: Ie70795bcb8c97e9dd5fb772adc060e1606f9bab0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52585 Reviewed-by: Marc Jones <marc@marcjonesconsulting.com> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-02-16commonlib/bsd, libpayload: Do not include helpers.h in stddef.hThomas Heijligen
`stddef.h` should only provide the definitions defined by ISO or Posix. The included `commonlib/bsd/helpers.h` provide a lot of non standard definitions that may interfere with definitions from the application. Change-Id: Ia71edbc3ffe6694ff4b971decf3a41f915264bc8 Signed-off-by: Thomas Heijligen <src@posteo.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70116 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-08commonlib/storage: Add attach callback to sdhci_ctrlrShelley Chen
Adding a attach callback function pointer in case a platform needs to execute anything before the standard initialization of the sdhci mem controller. BUG=b:254092907 BRANCH=None TEST=emerge-herobrine coreboot Change-Id: I0f37ec09d083922cad5ecd3c47b184cf3311fe2d Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72633 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Douglas Anderson <dianders@chromium.org>
2023-02-07bsd/cb_err: Add error code for UEFI variable storePatrick Rudolph
Add a new set of errors that will be used by the introduced EFI non-volatile variable store in flash. Change-Id: I6baea9fb138d1a2755d22a3d587105793adb9c90 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61960 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-02-07src: Move POST_BOOTBLOCK_CAR to common postcodes and use itMartin Roth
This moves the definition for POST_BOOTBLOCK_CAR from the intel-specific postcodes into the common postcode list, and uses it for the cache-as-RAM init as needed. Because POST_BOOTBLOCK_CAR was set to 0x20 in some spots and 0x21 in most of the others, the values were consolidated into 0x21. This will change the value on some platforms. Any conflicts should get sorted out later in the conversion process. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I8527334e679a23006b77a5645f919aea76dd4926 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71596 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2023-02-02commonlib: Add ELOG_TYPE_FW_EARLY_SOL eventLog typeTarun Tuli
Add a new eventLog type of ELOG_TYPE_FW_EARLY_SOL to support logging when we show early signs of life to the user. BUG=b:266113626 TEST=event shows in eventlog after CSE sync and/or MRC Change-Id: I3bd5a250c0be824dbbad0236cee7d61a1ffdbc6c Signed-off-by: Tarun Tuli <tarun.tuli@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72670 Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Julius Werner <jwerner@chromium.org>
2023-01-16commonlib/storage: Add common eMMC functionsShelley Chen
Now that multiple platforms are trying to initialize eMMC in coreboot instead of depthcharge, lets move common functionality into commonlib instead of copying the same functionality between multiple platforms. Note for consistency, changed name of set_early_mmc_wake_status() to mmc_set_early_wake_status(). Also adding an mmc_send_cmd1() function for retrieving the Operating Conditions Register (OCR) contents. BUG=b:218406702 BRANCH=None TEST=emerge-herobrine coreboot chromeos-bootimage flash onto villager device and make sure still boots ChromeOS Change-Id: Id00535b05bbd379081712601ef10e762c1831747 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71827 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-01-14commonlib/storage: fix int-to-pointer-cast errorShelley Chen
When pulling in commonlib/storage/pci_sdhci.c into herobrine, am seeing an "error: cast to pointer from integer of different size [-Werror=int-to-pointer-cast]", so fixing that. BUG=b:254092907 BRANCH=None TEST=emerge-herobrine coreboot Make sure that we can build without errors Change-Id: Ib1718f156708a619f7eeb181e19b1a8c620de1f8 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71828 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2023-01-11security/tpm: make tspi/crtm.c agnostic to log formatSergii Dmytruk
Change-Id: I3013bd5f29f1412fbe646dc74d8946704b750a66 Ticket: https://ticket.coreboot.org/issues/423 Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69445 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2023-01-11treewide: stop calling custom TPM log "TCPA"Sergii Dmytruk
TCPA usually refers to log described by TPM 1.2 specification. Change-Id: I896bd94f18b34d6c4b280f58b011d704df3d4022 Ticket: https://ticket.coreboot.org/issues/423 Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69444 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2023-01-07vc/google: Add and use POST_CODE_CLEAR definitionMartin Roth
The CR50 code clears the post code value. Add this as a #define. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: If3b73a3159ac8ac9ab08c6ff705b0ca289ab453c Reviewed-on: https://review.coreboot.org/c/coreboot/+/71592 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jon Murphy <jpmurphy@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-22coreboot_tables: Make existing alignment conventions more explicitJulius Werner
There seem to be some recurring vague concerns about the alignment of coreboot table entries. While the existing implementation has been producing tables with a well-defined alignment (4 bytes) for a long time, the code doesn't always make it very clear. This patch adds an explicit constant to codify that alignment, assertions to check it after each entry, and adds explicit padding to the few entry structures that were relying on compiler padding to return a correct sizeof() value. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: Iaeef29ef255047a855066469e03b5481812e5975 Reviewed-on: https://review.coreboot.org/c/coreboot/+/70158 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Jakub Czapiga <jacz@semihalf.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Peter Stuge <peter@stuge.se>
2022-12-15mem_chip_info: Fix potential overflowJulius Werner
The calculation for mem_chip_info_total_density_bytes() may already overflow in the intermediate 32-bit calculations before being assigned to the 64-bit result variable. Fix that. Fixes Coverity issue: CID 1501510 BRANCH=corsola Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I73da014c953381974c6ede2b17586b68675bde2d Reviewed-on: https://review.coreboot.org/c/coreboot/+/70764 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-12-12commonlib/clamp.h: Add more clamping functionsAngel Pons
Add more clamping functions that work with different types. Change-Id: I14cf335d5a54f769f8fd9184450957e876affd6b Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64175 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-09mem_chip_info: Update to new formatJulius Werner
The original version of the mem_chip_info structure does not record rank information and does not allow precise modeling of certain DDR configurations, so it falls short on its purpose to compile all available memory information. This patch updates the format to a new layout that remedies these issues. Since the structure was introduced so recently that no firmware using it has been finalized and shipped yet, we should be able to get away with this without accounting for backwards compatibility. BRANCH=corsola Cq-Depend: chromium:3980175 Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: If34e6857439b6f6ab225344e5b4dd0ff11d8d42a Reviewed-on: https://review.coreboot.org/c/coreboot/+/68871 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Xixi Chen <xixi.chen@mediatek.corp-partner.google.com>
2022-12-06drivers/intel/fsp2_0: Update MRC cache in ramstageReka Norman
Currently the MRC cache is updated in romstage, immediately after returning from FSP-M. Since cbmem is not cached in romstage, the update is slow (~6 ms on nissa). Specifically, the new MRC data returned by the FSP is stored in the FSP reserved memory in cbmem, so hashing the new data is slow. Move the MRC cache update to ramstage, where cbmem is cached. On nissa, this saves ~5 ms of boot time. Before: 552:finished loading ChromeOS VPD (RW) 631,667 (16) 3:after RAM initialization 637,703 (6,036) 4:end of romstage 650,307 (12,603) After: 552:finished loading ChromeOS VPD (RW) 631,832 (15) 3:after RAM initialization 633,002 (1,169) 4:end of romstage 645,582 (12,580) In ramstage, save_mrc_data() takes ~138 us. BUG=b:242667207 TEST=MRC caching still works as expected on nivviks - after clearing the MRC cache, memory is retrained on the next boot, but cached data is used on subsequent boots. Change-Id: Ie6aa2dee83a3ab8913830746593935d36a034b8d Signed-off-by: Reka Norman <rekanorman@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67669 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-12-05commonlib: Add essential comments for ELOG_CROS_DIAG_RESULTHsuan Ting Chen
ELOG_CROS_DIAG_RESULT_* codes should be consistent with the enum definition of enumerated histograms. Hence add comments based on the requirements of enum histograms in histogram guidelines. BUG=b:4047421 TEST=none Change-Id: I1a1a7c863d5aa9496649f81dc94fd79a6ad482df Signed-off-by: Hsuan Ting Chen <roccochen@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70145 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-25commonlib/fsp_relocate.c: Fix cbfstool build on 32-bit hostWerner Zeh
On a 32-bit host, uintptr_t is defined as 'unsigned int' instead of 'unsigend long int' like on a 64-bit host. When cbfstool is built on a 32-bit host, the printk format specifier '%lx' expects a 'long int' while new_addr is of type 'uintptr_t', aka 'unsigned int'. This in the end leads to a build error. To fix this and make it build on both, 32- and 64-bit hosts, use PRIxPTR as the format specifier. This macro will be resolved at compile time in the right way on both, 32- and 64-bit hosts. Test=Build cbfstool on 32- and 64-bit hosts. Change-Id: Ia917d2ed31778f3a29c0a6c7368f74c15319b099 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69682 Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-11-22src/commonlib: Remove unnecessary space after castsElyes Haouas
Change-Id: Ib20f02cc9e5be0efea8bc29fce6bd148adf28ead Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69817 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-17commonlib/storage/sdhci.c: Remove "ERROR: " from log messageElyes Haouas
It is no longer necessary to explicitly add "ERROR: " in front of BIOS_ERR message. Change-Id: I36e2785ae567d82339212140c1bde0876dfd450d Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69622 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-11-12device & commonlib: Update pci_scan_bus postcodesMartin Roth
The function pci_scan_bus had 3 post codes in it: 0x24 - beginning 0x25 - middle 0x55 - end I got rid of the middle postcode and used 0x25 for the code signifying the end of the function. I don't think all three are needed. 0x24 & 0x25 postcodes are currently also used in intel cache-as-ram code. Those postcodes should be adjusted to avoid conflicting. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I19c9d5e256505b64234919a99f73a71efbbfdae3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69201 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-11-10/: Remove "ERROR: "/"WARNING: " prefixes from log messagesElyes Haouas
It is no longer necessary to explicitly add "ERROR: "/"WARNING: " in front of every BIOS_ERR/BIOS_WARN message. Change-Id: I22ee6ae15c3d3a848853c5460b3b3c1795adf2f5 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69405 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-11-08arch/x86 & commonlib: Add macros for postcodes used in x86/tablesMartin Roth
The 0x9a, 0x9b, and 0x9c postcodes are not used anywhere else in the coreboot tree other than in arch/x86/tables.c. Add macros to standardize these postcodes. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I16be65ffa3f0b253fe4a9bb7bfb97597a760ad3f Reviewed-on: https://review.coreboot.org/c/coreboot/+/69200 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-11-04commonlib: Fix AMD MP2 BUFFER idMartin Roth
Cut and paste error. Signed-off-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Change-Id: Iae6213ac99bc5c64fd5dcd681c7922eafa011fc0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69165 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-10-29commonlib...cbmem_id.h: Add AMD STB buffer IDs for CBMEMMartin Roth
- CBMEM_ID_AMD_STB Main Spill-to-DRAM buffer. 2 to 16MiB. - CBMEM_ID_AMD_MP2 Debug buffer. 128KiB Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I27157ad65df992bcdd0e0d15a6d01b96e24067c0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68926 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>