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2017-06-22arch/x86/smbios: Fix scope of variable declarationNico Huber
Fix up for 1b5eda0 (arch/x86/smbios: Fix undefined behavior) which introduced the variable `tmp` and used it out of scope. Should fix coverity CID 1376385 (Memory - illegal accesses (RETURN_LOCAL)). Change-Id: I8d4f664fc54faf6beb432b939dda4ddf93cf5d3e Found-by: Coverity Scan #1376385 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/20279 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Ryan Salsamendi <rsalsamendi@hotmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2017-06-22arch/x86: Make rdrand.c clang friendlyStefan Reinauer
rdrand64() is not clang friendly. Actually it looks like the function is incorrect on 32bit x86 for all compilers including gcc, but gcc won't care because the function is never called on x86: src/arch/x86/rdrand.c:51:15: error: invalid output size for constraint '=a' : "=a" (*rand), "=qm" (carry)); ^ 1 error generated. Guard the code correctly if ENV_X86_64 is not set. Change-Id: Ia565897f5e4caaaccfcb02cf1245b150272dff68 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/20298 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2017-06-20arch/x86/smbios: Fix undefined behaviorRyan Salsamendi
Fixes report found by undefined behavior sanitizer. Dereferencing a pointer that's not aligned to the size of access is undefined behavior. The report triggered for smbios_cpu_vendor(). Also fixes the same issue in smbios_processor_name() found by inspection. Change-Id: I1b7d08655edce729e107a5b6e61ee509ebde33b6 Signed-off-by: Ryan Salsamendi <rsalsamendi@hotmail.com> Reviewed-on: https://review.coreboot.org/20154 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
2017-06-20arch/x86/ebda: Change memcpy() to endian wrappersRyan Salsamendi
Change memcpy()s and memset()s to endian.h wrappers for consistency and safety. Add zero_n() wrapper to safely clear memory. Change-Id: If155d82608c81992f05eae4d2223de6f506e98c5 Signed-off-by: Ryan Salsamendi <rsalsamendi@hotmail.com> Reviewed-on: https://review.coreboot.org/20240 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-06-14arch/x86: Fix undefined behaviorRyan Salsamendi
Fixes report found by undefined behavior sanitizer. Dereferencing a pointer that is not aligned to the size of access is undefined behavior. Switch to memcpy() for unaligned write to EBDA_LOWMEM. Change other write16()s in setup_ebda() to memcpy() for consistency. Change-Id: I79814bd47a14ec59d84068b11d094dc2531995d9 Signed-off-by: Ryan Salsamendi <rsalsamendi@hotmail.com> Reviewed-on: https://review.coreboot.org/20132 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
2017-06-08arch/x86/acpigen: Add additional opcodesPatrick Rudolph
Add additional ACPI opcodes, that are going to be used in the following commits. Change-Id: I20c3aa5a1412e5ef68831027137e9ed9e26ddbc9 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/20087 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2017-06-07src: change coreboot to lowercaseMartin Roth
The word 'coreboot' should always be written in lowercase, even at the start of a sentence. Change-Id: I7945ddb988262e7483da4e623cedf972380e65a2 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/20029 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-06-02arch/arm/include/armv7/arch: Correct keyword organization in cpu.hLogan Carlson
Move the inline keyword in between the static keyword and the return type. Change-Id: Ibacc5ee9fabff7fec2abd5534312cf3ab1bb28cf Signed-off-by: Logan Carlson <logancarlson@google.com> Reviewed-on: https://review.coreboot.org/19991 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
2017-06-02arch/arm: Correct checkpatch errorsLogan Carlson
Correct whitespace issues in arch/arm and arch/arm64. Enclose complex values in parenthesis. Change-Id: I74b68f485adff1e6f0fa433e51e12b59ccea654b Signed-off-by: Logan Carlson <logancarlson@google.com> Reviewed-on: https://review.coreboot.org/19989 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2017-05-30arch: Unify basic cache clearing APIJulius Werner
Caching is a very architecture-specific thing, but most architectures have a cache in general. Therefore it can be useful to have a generic architecture-independent API to perform simple cache management tasks from common code. We have already standardized on the dcache_clean/invalidate naming scheme that originally comes from ARM in libpayload, so let's just do the same for coreboot. Unlike libpayload, there are other things than just DMA coherency we may want to achieve with those functions, so actually implement them for real even on architectures with cache-snooping DMA like x86. (In the future, we may find applications like this in libpayload as well and should probably rethink the API there... maybe move the current functionality to a separate dma_map/unmap API instead. But that's beyond scope of this patch.) Change-Id: I2c1723a287f76cd4118ef38a445339840601aeea Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/19788 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
2017-05-30arch/x86: Add function to determine if we're currently running from CARJulius Werner
This patch adds a simple function that can be used to check if CAR_GLOBALs are currently being read from CAR or from DRAM. Change-Id: Ib7ad0896a691ef6e89e622b985417fedc43579c1 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/19787 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
2017-05-30arm64: Align cache maintenance code with libpayload and ARM32Julius Werner
coreboot and libpayload currently use completely different code to perform a full cache flush on ARM64, with even different function names. The libpayload code is closely inspired by the ARM32 version, so for the sake of overall consistency let's sync coreboot to that. Also align a few other cache management details to work the same way as the corresponding ARM32 parts (such as only flushing but not invalidating the data cache after loading a new stage, which may have a small performance benefit). Change-Id: I9e05b425eeeaa27a447b37f98c0928fed3f74340 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/19785 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-05-27CBMEM: Clarify CBMEM_TOP_BACKUP function usageKyösti Mälkki
The deprecated LATE_CBMEM_INIT function is renamed: set_top_of_ram -> set_late_cbmem_top Obscure term top_of_ram is replaced: backup_top_of_ram -> backup_top_of_low_cacheable get_top_of_ram -> restore_top_of_low_cacheable New function that always resolves to CBMEM top boundary, with or without SMM, is named restore_cbmem_top(). Change-Id: I61d20f94840ad61e9fd55976e5aa8c27040b8fb7 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/19377 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
2017-05-22arch/x86/include: Use IS_ENABLED() macroNico Huber
Change-Id: I0f9a92e595ec765d47f89f0023ff69636ee406af Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/19761 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
2017-05-183rdparty/arm-trusted-firmware: Update to upstream masterMartin Roth
Submodule 3rdparty/arm-trusted-firmware 236c27d21f..3944adca59 This brings in 241 new commits from the upstream arm-trusted-firmware repository, merged to the upstream tree between December 30, 2016 and March 18, 2017. 3944adca Merge pull request #861 from soby-mathew/sm/aarch32_fixes .. e0f083a0 fiptool: Prepare ground for expanding the set of images at runtime Also setup ATF builds so that unused functions don't break the build. They're harmless and they don't filter for these like we do. Change-Id: Ibf5bede79126bcbb62243808a2624d9517015920 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/18954 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2017-05-18CBMEM: Add config CBMEM_TOP_BACKUPKyösti Mälkki
AGESA and binaryPI boards have no easy way to determine correct cbmem_top() location early enough when GFXUMA is enabled, so they will use these functions with EARLY_CBMEM_INIT as well. At the end of AmdInitPost() the decisions of UMA base and size have not been written to hardware yet. The decisions are stored inside AGESA heap object we cannot locate from coreboot proper until after AmdInitEnv(). Modify code such that weak backup functions are only defined for LATE_CBMEM_INIT; they are somewhat troublesome to handle. Change-Id: Ifef4f75b36bc6dee6cd56d1d9164281d9b2a4f2a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/19306 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-05-16arch/arm64: Use variables of the right size for msr/mrs opcodesPatrick Georgi
They do 64bit accesses, and gcc does the necessary fix ups to handle 32bit values as zero-padded 64bit values. clang, however, isn't happy with it. Change-Id: I9c8b9fe3a1adc521e393c2e2a0216f7f425a2a3e Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/19661 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-05-12commonlib: Move drivers/storage into commonlib/storageLee Leahy
Move drivers/storage into commonlib/storage to enable access by libpayload and indirectly by payloads. * Remove SD/MMC specific include files from include/device * Remove files from drivers/storage * Add SD/MMC specific include files to commonlib/include * Add files to commonlib/storage * Fix header file references * Add subdir entry in commonlib/Makefile.inc to build the SD/MMC driver * Add Kconfig source for commonlib/storage * Rename *DEVICE* to *COMMONLIB* * Rename *DRIVERS_STORAGE* to *COMMONLIB_STORAGE* TEST=Build and run on Galileo Gen2 Change-Id: I4339e4378491db9a0da1f2dc34e1906a5ba31ad6 Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/19672 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-05-01arch/x86: Share storage data structures between early stagesLee Leahy
Define a common area in CAR so that the storage data structures can be shared between stages. TEST=Build and run on Reef Change-Id: I20a01b850a31df9887a428bf07ca476c8410d33e Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/19300 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2017-04-25arch/x86: Add read64 and write64 functionsMarshall Dawson
Create new functions similar to read and write of other sizes. Change-Id: I35a08c498f25227233604c65c45b73b1c44fae1f Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/19394 Tested-by: build bot (Jenkins) Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-04-18x86/acpigen: Fix BufferSize of ResourceTemplateNico Huber
Don't start counting the buffer size amidst the BufferSize field itself. This should help with a regression introduced in Linux with [1] which checks the BufferSize field. [1] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=57707a9a778 Change-Id: I7349c8e281c41384491d730dfeac3336f29992f7 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/19284 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-04-17arch/x86/acpi: Allow "transparent" ACPI device namesTimothy Pearson
Certain devices, such as the northbridge on AMD Opteron systems, do not require a node in the ACPI device path. Allow such devices to be passed over by the ACPI path generator if the device-specific ACPI name function returns a zero-length (non-NULL) string. Change-Id: Iffffc9a30b395b0bd6d60e411439a437e89f554e Signed-off-by: Timothy Pearson <tpearson@raptorengineering.com> Reviewed-on: https://review.coreboot.org/19281 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-04-08arch/x86: remove CAR global migration when postcar stage is usedAaron Durbin
When a platform is using postcar stage it's by definition not tearing down cache-as-ram from within romstage prior to loading ramstage. Because of this property there's no need to migrate CAR_GLOBAL variables to cbmem. Change-Id: I7c683e1937c3397cbbba15f0f5d4be9e624ac27f Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/19215 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2017-04-03arch/x86/acpigen: Allow writing buffers larger than 256 bytesRizwan Qureshi
Currently only 256 bytes can be written at a time using the acpigen_write_return_byte_buffer or acpigen_write_byte_buffer API's and there can be cases where the buffer size can exceed this, hence increase the number of bytes that can be written. Change-Id: Ifaf508ae1d5c0eb2629ca112224bfeae1c644e58 Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Signed-off-by: Sowmya V <v.sowmya@intel.com> Reviewed-on: https://review.coreboot.org/18966 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-28Remove libverstage as separate library and source file classJulius Werner
In builds without CONFIG_VBOOT_SEPARATE_VERSTAGE, verstage files are linked directly into the bootblock or the romstage. However, they're still compiled with a separate "libverstage" source file class, linked into an intermediate library and then linked into the final destination stage. There is no obvious benefit to doing it this way and it's unclear why it was chosen in the first place... there are, however, obvious disadvantages: it can result in code that is used by both libverstage and the host stage to occur twice in the output binary. It also means that libverstage files have their separate compiler flags that are not necessarily aligned with the host stage, which can lead to weird effects like <rules.h> macros not being set the way you would expect. In fact, VBOOT_STARTS_IN_ROMSTAGE configurations are currently broken on x86 because their libverstage code that gets compiled into the romstage sets ENV_VERSTAGE, but CAR migration code expects all ENV_VERSTAGE code to run pre-migration. This patch resolves these problems by removing the separate library. There is no more difference between the 'verstage' and 'libverstage' classes, and the source files added to them are just treated the same way a bootblock or romstage source files in configurations where the verstage is linked into either of these respective stages (allowing for the normal object code deduplication and causing those files to be compiled with the same flags as the host stage's files). Tested this whole series by booting a Kevin, an Elm (both with and without SEPARATE_VERSTAGE) and a Falco in normal and recovery mode. Change-Id: I6bb84a9bf1cd54f2e02ca1f665740a9c88d88df4 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/18302 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-28vboot: Move remaining features out of vendorcode/google/chromeosJulius Werner
This patch attempts to finish the separation between CONFIG_VBOOT and CONFIG_CHROMEOS by moving the remaining options and code (including image generation code for things like FWID and GBB flags, which are intrinsic to vboot itself) from src/vendorcode/google/chromeos to src/vboot. Also taking this opportunity to namespace all VBOOT Kconfig options, and clean up menuconfig visibility for them (i.e. some options were visible even though they were tied to the hardware while others were invisible even though it might make sense to change them). CQ-DEPEND=CL:459088 Change-Id: I3e2e31150ebf5a96b6fe507ebeb53a41ecf88122 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/18984 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-28vboot: Remove CHIPSET_PROVIDES_VERSTAGE_MAIN_SYMBOL Kconfig optionJulius Werner
CHIPSET_PROVIDES_VERSTAGE_MAIN_SYMBOL allows the SoC directory to provide its own main() symbol that can execute code before the generic verstage code runs. We have now established in other places (e.g. T210 ramstage) a sort of convention that SoCs which need to run code in any stage before main() should just override stage_entry() instead. This patch aligns the verstage with that model and gets rid of the extra Kconfig option. This also removes the need for aliasing between main() and verstage(). Like other stages the main verstage code is now just in main() and can be called from stage_entry(). Change-Id: If42c9c4fbab51fbd474e1530023a30b69495d1d6 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/18978 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2017-03-28arm64: Fix verstage to use proper assembly versions of mem*()Julius Werner
Due to an unfortunate race between adding verstage support and reverting an earlier hack that disabled the optimized assembly versions of memcpy(), memmove() and memset() on ARM64, it seems that we never enabled the optimized code for the verstage. This should be fixed so that all stages use the same architecture support code. Change-Id: I0bf3245e346105492030f4b133729c4d11bdb3ff Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/18976 Tested-by: build bot (Jenkins)
2017-03-20arch/x86: Fix most of remaining issues detected by checkpatchLee Leahy
Fix the following errors and warnings detected by checkpatch.pl: ERROR: do not use assignment in if condition ERROR: trailing statements should be on next line ERROR: Macros with complex values should be enclosed in parentheses ERROR: switch and case should be at the same indent WARNING: char * array declaration might be better as static const WARNING: else is not generally useful after a break or return WARNING: storage class should be at the beginning of the declaration WARNING: void function return statements are not generally useful WARNING: break is not useful after a goto or return WARNING: Single statement macros should not use a do {} while (0) loop WARNING: sizeof *t should be sizeof(*t) WARNING: Comparisons should place the constant on the right side of the test TEST=Build and run on Galileo Gen2 Change-Id: I39d49790c5eaeedec5051e1fab0b1279275f6e7f Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/18865 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-03-19ramstage: Align stack to 16 bytesKyösti Mälkki
Some SSE instructions could take 128bit memory operands from stack. AGESA vendorcode was always built with SSE enabled, but until now stack alignment was not known to cause major issues. Seems like GCC-6.3 more likely emits instructions that depend on the 16 byte alignment of stack. Change-Id: Iea3de54f20ff242105bce5a5edbbd76b04c0116c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/18823 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-17arch/x86: Wrap lines at 80 columnsLee Leahy
Fix the following warning detected by checkpatch.pl: WARNING: line over 80 characters TEST=Build and run on Galileo Gen2 Change-Id: I3495cd30d1737d9ee728c8a9e72bd426d7a69c37 Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/18864 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-17arch/x86: Fix prefer errors detected by checkpatchLee Leahy
Fix the following warnings detected by checkpatch.pl: WARNING: Prefer 'unsigned int' to bare use of 'unsigned' WARNING: plain inline is preferred over __inline__ TEST=Build and run on Galileo Gen2 Change-Id: I8ba98dfe04481a7ccf4f3b910660178b7e22a4a7 Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/18863 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-17arch/x86: Fix space issues detected by checkpatchLee Leahy
Fix the following errors and warnings detected by checkpatch.pl: ERROR: space required before the open parenthesis '(' ERROR: space prohibited after that open parenthesis '(' ERROR: space prohibited before that close parenthesis ')' ERROR: space prohibited after that open square bracket '[' ERROR: space required after that ',' (ctx:VxV) ERROR: space prohibited before that ',' (ctx:WxW) ERROR: space required after that ';' (ctx:VxV) ERROR: spaces required around that ':' (ctx:ExV) ERROR: spaces required around that ':' (ctx:VxW) ERROR: spaces required around that ':' (ctx:WxV) ERROR: spaces required around that '=' (ctx:VxV) ERROR: spaces required around that '+=' (ctx:VxV) ERROR: spaces required around that '<=' (ctx:WxV) ERROR: spaces required around that '||' (ctx:VxW) ERROR: space prohibited before that '++' (ctx:WxO) ERROR: need consistent spacing around '+' (ctx:WxV) ERROR: spaces required around that '<' (ctx:WxV) ERROR: spaces required around that '<' (ctx:VxV) ERROR: need consistent spacing around '>>' (ctx:WxV) ERROR: "(foo*)" should be "(foo *)" ERROR: "foo* bar" should be "foo *bar" ERROR: "foo * bar" should be "foo *bar" ERROR: code indent should use tabs where possible WARNING: space prohibited between function name and open parenthesis '(' WARNING: unnecessary whitespace before a quoted newline WARNING: please, no spaces at the start of a line WARNING: please, no space before tabs WARNING: Unnecessary space before function pointer arguments TEST=Build and run on Galileo Gen2 Change-Id: I2d7e1a329c6b2e8ca9633a97b595566544d7fd33 Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/18862 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-17arch/x86: Fix issues with braces detected by checkpatchLee Leahy
Fix the following errors and warnings detected by checkpatch.pl: ERROR: open brace '{' following function declarations go on the next line ERROR: that open brace { should be on the previous line ERROR: else should follow close brace '}' WARNING: braces {} are not necessary for any arm of this statement WARNING: braces {} are not necessary for single statement blocks TEST=Build and run on Galileo Gen2 Change-Id: I13d1967757e106c8300a15baed25d920c52a1a95 Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/18861 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-16acpi_device: Add macro for GpioInt that uses both polarityDuncan Laurie
GPIO edge interrupts can report that they are ActiveBoth and will generate an interrupt event on both rising and falling edges. Add a macro so this type of GPIO interrupt can be used. BUG=b:35581264 BRANCH=none TEST=successfully use this interrupt type on Eve Change-Id: I91408386538e442bddcacc9840e0aa14370a446c Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/18834 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-03-16acpi_device: Prefix IRQ macros with ACPIDuncan Laurie
Switch some IRQ_* macros to ACPI_IRQ_* instead so they do not fail at compile time if they are used. BUG=b:35581264 BRANCH=none TEST=successfully compile with ACPI_GPIO_IRQ_LEVEL_HIGH Change-Id: Id4040eca4c7c9d8f7b4f0add411d5d6fe5ed1eb8 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/18833 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins)
2017-03-15acpi: device: Add macro for active high level triggered IRQDuncan Laurie
Add the missing macro for ACPI_IRQ_LEVEL_HIGH so it can get used by devicetree when necessary. BUG=b:35585307 BRANCH=none TEST=Add rt5514 SPI device with active high level IRQ on Eve board and check that it is enumerated in the kernel Change-Id: I25c7b035a198efb218f0f6b4ba3f4a1bf532bcea Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/18815 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-03-02acpi: Update the ACPI ID for corebootDuncan Laurie
The newly assigned ACPI ID for coreboot is 'BOOT' http://www.uefi.org/acpi_id_list Use this new range of ACPI IDs of "BOOTxxxx" for coreboot specific ACPI objects instead of the placeholder range of "GOOGCBxx". Change-Id: I10b30b5a35be055c220c85b14a06b88939739a31 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/18521 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-02-24src/arch/x86: Remove non-ascii charactersMartin Roth
Change-Id: Ie0d35c693ed5cc3e890279eda289bd6d4416d9e6 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/18376 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-02-24arm-trusted-firmware: Disable a couple of warnings for GCC 6.2Martin Roth
- Remove warnings about code using deprecated declarations such as: plat/mediatek/mt8173/bl31_plat_setup.c: In function 'bl31_platform_setup': plat/mediatek/mt8173/bl31_plat_setup.c:175:2: warning: 'arm_gic_setup' is deprecated [-Wdeprecated-declarations] include/drivers/arm/arm_gic.h:44:6: note: declared here: void arm_gic_setup(void) __deprecated; - Disable pedantic warnings to get rid of these warnings: In file included from plat/mediatek/mt8173/bl31_plat_setup.c:36:0: plat/mediatek/mt8173/include/mcucfg.h:134:21: error: enumerator value for 'MP1_CPUCFG_64BIT' is not an integer constant expression [-Werror=pedantic] MP1_CPUCFG_64BIT = 0xf << MP1_CPUCFG_64BIT_SHIFT Change-Id: Ibf2c4972232b2ad743ba689825cfe8440d63e828 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/17995 Tested-by: build bot (Jenkins) Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-02-22arch/x86/acpigen: Provide helper functions for enabling/disabling GPIOFurquan Shaikh
In order to allow GPIOs to be set/clear according to their polarity, provide helper functions that check for polarity and call set/clear SoC functions for generating ACPI code. BUG=None BRANCH=None TEST=Verified that the ACPI code generated remains the same as before for reef. Change-Id: Ie8bdb9dc18e61a4a658f1447d6f1db0b166d9c12 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/18427 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2017-02-22acpi: Add ACPI_ prefix to IRQ enum and struct namesFurquan Shaikh
This is done to avoid any conflicts with same IRQ enums defined by other drivers. BUG=None BRANCH=None TEST=Compiles successfully Change-Id: I539831d853286ca45f6c36c3812a6fa9602df24c Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/18444 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-02-20arch/x86: add functions to generate random numbersRobbie Zhang
Using x86 RDRAND instruction, two functions are supplied to generate a 32bit or 64bit number. One potential usage is the sealing key generation for SGX. BUG=chrome-os-partner:62438 BRANCH=NONE TEST=Tested on Eve to generate a 64bit random number. Change-Id: I50cbeda4de17ccf2fc5efc1fe04f6b1a31ec268c Signed-off-by: Robbie Zhang <robbie.zhang@intel.com> Reviewed-on: https://review.coreboot.org/18362 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-02-20riscv: Suppress invalid coverity errorsMartin Roth
Coverity is detecting 'sp' as a variable which has not been initialized. This is obviously not correct, so this patch *TRIES* to mark it as false I'm not positive that this will work because the annotation needs to go on the line above the error, but this error is inside of a # define. Does the whole #define count as one line? Can it go on the line above the #define in the .h file? Does it have to precede every line where the #define is used? The documentation doesn't make this clear. Should suppress coverity issues: 1368525 & 1368527 uninit_use: Using uninitialized value sp. Change-Id: Ibae5e206c4ff47991ea8a11b6b59972b24b71796 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/18247 Tested-by: build bot (Jenkins) Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
2017-02-19acpi_device: Add macros for GPIO interruptsDuncan Laurie
Add individual macros for the various interrupt types so they can be used in devicetree. BUG=chrome-os-partner:58666 TEST=nothing uses this yet, will be used in an upcoming commit Change-Id: I2a569f60fcc0815835615656b09670987036b848 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/18392 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-02-19acpi_device: Move power resource function to generic codeDuncan Laurie
Move the function that adds a power resource block from i2c/generic to the acpi device code at src/arch/x86/acpi_device.c so it can be used by more drivers. BUG=chrome-os-partner:61233 TEST=verify SSDT table generation is unchanged Change-Id: I0ffb61a4f46028cbe912e85c0124d9f5200b9c76 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/18391 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-02-16spi: Add function callback to get configuration of SPI busFurquan Shaikh
Add a new callback to spi_ctrlr structure - get_config - to obtain configuration of SPI bus from the controller driver. Also, move common config definitions from acpi_device.h to spi-generic.h BUG=chrome-os-partner:59832 BRANCH=None TEST=Compiles successfully Change-Id: I412c8c70167d18058a32041c2310bc1c884043ce Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/18337 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2017-02-14src/Kconfig: Move bootblock behavior to arch/x86 as TODO suggestedMartin Roth
The four options are only used in X86: - BOOTBLOCK_SIMPLE - BOOTBLOCK_NORMAL - BOOTBLOCK_SOURCE - SKIP_MAX_REBOOT_CNT_CLEAR Move them all into src/arch/x86/Kconfig - this puts them in the chipset menu instead of general setup. Verified that this makes no significant changes to any config file. Change-Id: I2798ef67a8c6aed5afac34322be15fdf0c794059 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/17909 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins)
2017-02-04x86/acpi: Add VFCT tablePatrick Rudolph
Add VFCT table to provide PCI Optiom Rom for AMD graphic devices. Useful for GNU Linux payloads and embedded dual GPU systems. Tested on Lenovo T500 with AMD RV635 as secondary gpu. Original Change-Id: I3b4a587c71e7165338cad3aca77ed5afa085a63c Signed-off-by: Patrick Rudolph <siro@das-labor.org> Change-Id: I4dc00005270240c048272b2e4f52ae46ba1c9422 Reviewed-on: https://review.coreboot.org/18192 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-01-31build system: mark sub-make invocations as parallelizablePatrick Georgi
We rely on gnu make, so we can expect the jobserver to be around in parallel builds, too. Avoids some make warnings and slightly speeds up the build if those sub-makes are executed (eg for arm-trusted-firmware and vboot). Change-Id: I0e6a77f2813f7453d53e88e0214ad8c1b8689042 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/18263 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2017-01-24arch/x86: do not define type of SPIN_LOCK_UNLOCKEDPatrick Georgi
This fixes building coreboot with -std=gnu11 on gcc 4.9.x Also needs fix ups for asus/kcma-d8 and asus/kgpe-d16 due to the missing type. Change-Id: I920d492a1422433d7d4b4659b27f5a22914bc438 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/18220 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2017-01-16riscv: Move mcall numbers to mcall.h, adjust their namesJonathan Neuschäfer
The new name and location make more sense: - The instruction used to call into machine mode isn't called "ecall" anymore; it's mcall now. - Having SBI_ in the name is slightly wrong, too: these numbers are not part of the Supervisor Binary Interface, they are just used to forward SBI calls (they could be renumbered arbitrarily without breaking an OS that's run under coreboot). Also remove mcall_dev_{req,resp} and the corresponding mcall numbers, which are no longer used. Change-Id: I76a8cb04e4ace51964b1cb4f67d49cfee9850da7 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/18146 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2017-01-16riscv: get SBI calls to workRonald G. Minnich
SBI calls, as it turned out, were never right. They did not set the stack correctly on traps. They were not correctly setting the MIP instead of the SIP (although this was not really well documented). On Harvey, we were trying to avoid using them, and due to a bug in SPIKE, our avoidance worked. Once SPIKE was fixed, our avoidance broke. This set of changes is tested and working with Harvey which, for the first time, is making SBI calls. It's not pretty and we're going to want to rework trap_util.S in coming days. Change-Id: Ibef530adcc58d33e2c44ff758e0b7d2acbdc5e99 Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/18097 Tested-by: build bot (Jenkins)
2017-01-06arch/x86: fix cmos post logging in non romcc bootblockAaron Durbin
cmos_post_init() is called in src/arch/x86/bootblock_simple.c, and that function is reponsible for bootstrapping the cmos post register contents. Without this function being called none of the cmos post functionality works correctly. Therefore, add a call to lib/bootblock.c which the C_ENVIRONMENT_BOOTBLOCK SoCs use. BUG=chrome-os-partner:61546 Change-Id: I2e3519f2f3f2c28e5cba26b5811f1eb0c2a90572 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/18043 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-12-21soc/intel/apollolake: allow ApolloLake SoC to use FSP CAR InitBrenton Dong
FSP v2.0 Driver supports TempRamInit & TempRamExit APIs to initialize & tear down Cache-As-Ram. Add TempRamInit & TempRamExit usage to ApolloLake SoC when CONFIG_FSP_CAR is enabled. Verified on Intel Leaf Hill CRB and confirmed that Cache-As-Ram is correctly set up and torn down using the FSP v2.0 APIs without coreboot implementation of CAR init/teardown. Change-Id: Ifd6fe8398ea147a5fb8c60076b93205bb94b1f25 Signed-off-by: Brenton Dong <brenton.m.dong@intel.com> Reviewed-on: https://review.coreboot.org/17063 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-21drivers/intel/fsp2_0: add FSP TempRamInit & TempRamExit API supportBrenton Dong
FSP v2.0 Specification adds APIs TempRamInit & TempRamExit for Cache-As-Ram initialization and teardown. Add fsp2_0 driver support for TempRamInit & TempRamExit APIs. Verified on Intel Leaf Hill CRB and confirmed that Cache-As-Ram is correctly set up and torn down using the FSP v2.0 APIs without coreboot implementation of CAR init/teardown. Change-Id: I482ff580e1b5251a8214fe2e3d2d38bd5f3e3ed2 Signed-off-by: Brenton Dong <brenton.m.dong@intel.com> Reviewed-on: https://review.coreboot.org/17062 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-20riscv: enable counters via m[us]counterenRonald G. Minnich
The user and supervisor counters could not be safely enabled before as the register numbers were not finalized. Now that everyone agrees, we can enable them. Until we are sure the toolchains are caught up, we use the hardcode name with the register names in comments. As soon as toolchains settle down we'll do one more pass and convert to the symbolic names. Tested on lowrisc bitstream and SPIKE simulator. Change-Id: I21fe5cac44fafe4b7806e004c179aa27541be4b6 Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: https://review.coreboot.org/17920 Tested-by: build bot (Jenkins) Reviewed-by: Alex Bradbury <asb@lowrisc.org> Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-by: Andrew Waterman <aswaterman@gmail.com>
2016-12-18ACPI S3: Signal successful bootKyösti Mälkki
Just before jumping to OS wakeup vector do the same tasks to signal coreboot completion that would be done before entry to payload on normal boot path. Change-Id: I7514c498f40f2d93a4e83a232ef4665f5c21f062 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17794 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-12-18riscv: Add support for timer interruptsRonald G. Minnich
RISCV requires that timer interrupts be handled in machine mode and delegated as necessary. Also you can only reset the timer interrupt by writing to mtimecmp. Further, you must write a number > mtime, not just != mtime. This rather clumsy situation requires that we write some value into the future into mtimecmp lest we never be able to leave machine mode as the interrupt either is not cleared or instantly reoccurs. This current code is tested and works for harvey (Plan 9) timer interrupts. Change-Id: I8538d5fd8d80d9347773c638f5cbf0da18dc1cae Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: https://review.coreboot.org/17807 Tested-by: build bot (Jenkins) Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
2016-12-17Revert "arch/x86/smbios: Correct manufacturer ID"Nico Huber
This reverts commit c86da67436827c25919a2f5966049485a58fc984. Alas, I have to disagree with this in every single line. The comment added to the top of the file only applies to a single function therein which sits over a hundred lines below. That's not much helpful. More- over, the link in the comment is already down ofc. The comment is also irritating as it doesn't state in which way (enco- ding!) it applies to the code, which presumably led to the wrong in- terpretation of the IDs. At last, if anything should have changed it is the strings, the IDs are resolved to. `smbios_fill_dimm_manufacturer_from_id()` has to resolve the IDs it gets actually fed and not a random selection from any spec. Since I digged into it, here's why the numbers are correct: The func- tion started with the SPD encoding of DDR3 in mind. There, the lower byte is the number of a "bank" of IDs with an odd-parity in the upper most bit. The upper byte is the ID within the bank. The "correction" was to clear the parity bit for naught. The function was later exten- ded with IDs in the DDR2-SPD encoding (which is actually 64-bit not 16). There, a byte, starting from the lowest, is either an ID below 127 plus odd-parity, or 127 which means look in the next byte/bank. Unused bytes seem to be filled with 0xff, I guess from the 0xff2c. Change-Id: Icdb48e4f2c102f619fbdca856e938e85135cfb18 Reviewed-on: https://review.coreboot.org/17873 Tested-by: build bot (Jenkins) Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2016-12-16x86: Configure premem cbmem console sizeNaresh G Solanki
Sometime preram cbmem logs are truncated due to lack of space (default preram cbmem console size is 0xc00). Provide Kconfig option to configure preram cbmem console size so that mainboard can configure it to required value. Change-Id: I221d9170c547d41d8bd678a3a8b3bca6a76ccd2e Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com> Reviewed-on: https://review.coreboot.org/17839 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-16acpi_device: Add special HID for DT namespaceFurquan Shaikh
BUG=chrome-os-partner:60194 BRANCH=None TEST=Compiles successfully Change-Id: I0fe146cf2235c7c4ad3ea5589ed556884de3a368 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/17842 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-12-11ACPI S3: Hide acpi_slp_typeKyösti Mälkki
Change-Id: I48a20e34f11adc7c61d0ce6b3c005dbd712fbcac Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/10360 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-09postcar_loader: Support LATE_CBMEM_INIT boardsKyösti Mälkki
Create postcar_frame object without placing stack in CBMEM. This way same cache_as_ram.inc code can be used unmodified. Change-Id: Ic5ed404ce268ee881e9893dd434534231aa2bc88 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17700 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-08cpu/x86: allow AP callbacks after MP initAaron Durbin
There are circumstances where the APs need to run a piece of code later in the boot flow. The current MP init just parks the APs after MP init is completed so there's not an opportunity to target running a piece of code on all the APs at a later time. Therefore, provide an option, PARALLEL_MP_AP_WORK, that allows the APs to perform callbacks. BUG=chrome-os-partner:60657 BRANCH=reef Change-Id: I849ecfdd6641dd9424943e246317cd1996ef1ba6 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/17745 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
2016-12-08buildsystem: Drop explicit (k)config.h includesKyösti Mälkki
We have kconfig.h auto-included and it pulls config.h too. Change-Id: I665a0a168b0d4d3b8f3a27203827b542769988da Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17655 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-12-07PCI ops: MMCONF_SUPPORT_DEFAULT is requiredKyösti Mälkki
Doing PCI config operations via MMIO window by default is a requirement, if supported by the platform. This means chipset or CPU code must enable MMCONF operations early in bootblock already, or before platform-specific romstage entry. Platforms are allowed to have NO_MMCONF_SUPPORT only in the case it is actually not implemented in the silicon. Change-Id: Id4d9029dec2fe195f09373320de800fcdf88c15d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17693 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-06CPU: Declare cpu_phys_address_size() for all archKyösti Mälkki
Resource allocator and 64-bit PCI BARs will need it and PCI use is not really restricted to x86. Change-Id: Ie97f0f73380118f43ec6271aed5617d62a4f5532 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17733 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-06CPU: Move SMM prototypes under x86Kyösti Mälkki
Change-Id: Iefbc17dcfcf312338d94b2c2945c7fac3b23bff6 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17732 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-12-06PCI ops: Rename pcie_xx() to pci_mmio_xx()Kyösti Mälkki
Change-Id: I7fa65197b8165b9b0b74937f9ba455c48308da37 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17530 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-06PCI ops: Define read-modify-write routines globallyKyösti Mälkki
Change-Id: I7d64f46bb4ec3229879a60159efc8a8408512acd Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17690 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-06intel PCI ops: Remove explicit PCI MMCONF accessKyösti Mälkki
MMCONF was explicitly used here to avoid races of 0xcf8/0xcfc access being non-atomic and/or need to access 4kiB of PCI config space. All these platforms now have MMCONF_SUPPORT_DEFAULT. I liked the style of code in pci_mmio_cfg.h more, and used those to replace the ones in io.h. Change-Id: Ib5e6a451866c95d1edb9060c7f94070830b90e92 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17689 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-06riscv: Stub out sbi_(un)mask_interruptJonathan Neuschäfer
Linux needs these SBI calls, but so far it seems to work when they don't do anything. Change-Id: I2cd0bb3ab91e89805fed84ec87e4a48ce70c3a46 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/17593 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2016-12-06arch/riscv/mcall.c: Return the correct memory base and sizeJonathan Neuschäfer
Change-Id: Ibf471787ccb4f5393b0af737a9f7fc47b853a41a Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/17594 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2016-12-01arch/x86: cache postcar in stage cacheAaron Durbin
Stash and reload postcar stage in the stage cache for increased S3 resume speed. It's impact is small (2 ms or so), but there's no need to go to the boot media on resume to reload something that was already loaded. This aligns with the same paths we take on ramstage as well. Change-Id: I4313794826120853163c7366e81346858747ed0a Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/17649 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-12-01romstage_handoff: add helper to determine resume statusAaron Durbin
Instead of having callers query the romstage handoff resume status by inspecting the object themselves add romstage_handoff_is_resume() so that the same information can be queried easily. Change-Id: I40f3769b7646bf296ee4bc323a9ab1d5e5691e21 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/17647 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-11-28Build system: Update HAVE_CMOS_DEFAULTMartin Roth
- Don't build the cmos.default file into cbfs if USE_OPTION_TABLE isn't specified. - Don't allow HAVE_CMOS_DEFAULT if HAVE_OPTION_TABLE isn't set. Change-Id: I92401e892f09fc95d4b3fd7418cdbd10ed033fa8 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/17454 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-11-24arch/x86/acpigen: Write DSM method with multiple UUID'sNaresh G Solanki
Enable generic way of writing DSM method which can write acpi table for multiple UUID's. Change-Id: Ic1fbdc0647e8fdc50ffa407887feb19a63cb48e4 Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com> Reviewed-on: https://review.coreboot.org/17424 Tested-by: build bot (Jenkins) Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-11-21arch/x86: don't create new gdt in cbmem for relocatable ramstageAaron Durbin
When running with relocatable ramstage, the gdt loaded from c_start.S is already in CBMEM (high memory). Thus, there's no need to create a new copy of the gdt and reload. Change-Id: I2750d30119fee01baf4748d8001a672d18a13fb0 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/17504 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-11-20riscv: map first 4GiB of physical address spaceRonald G. Minnich
o The first 4G of physical address space is now mapped at 0. o The first 4G of physical address space is now mapped at 1 << 38. o The first 2G of DRAM (2 - 4 GiB of physical address space) is now mapped at the top of memory save for the last 4K i.e. at 0xffffffff80000000, with SBI page at the very top. Of these, we hope to remove the *most* of the last one once the gcc toolchain can handle linking programs that can run at "top 33 bits of address not all ones (but bit 63 set)". The 4K mapping of the top of the 64 bit address space will always remain, however, for SBI calls. Change-Id: I77b151720001bddad5563b0f8e1279abcea056fa Reviewed-on: https://review.coreboot.org/17403 Tested-by: build bot (Jenkins) Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
2016-11-20arch/x86 GDT: Fix orphan debug outputKyösti Mälkki
On S3 resume path, CBMEM_ID_GDT already exists but we only printed the final "ok" string. Always tell GDT is about to be moved. Change-Id: Ic91c5389cf4d47d28a6c54db152c18541c413bc1 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17500 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-17arch/x86/acpigen: Implement acpigen functions to return integer & stringNaresh G Solanki
Add ACPI method to return integer & string. Change-Id: I2a668ccadecb71b71531e2eb53a52015fca96738 Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com> Reviewed-on: https://review.coreboot.org/17450 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-11-17arm64: arm_tf: Do not build raw bl31.bin binaryJulius Werner
coreboot's build system picks up the BL31 image as an ELF from the ARM Trusted Firmware submodule and inserts it into CBFS. However, the generic 'bl31' build target we run in the ARM Trusted Firmware build system also generates a raw bl31.bin binary file. We don't need that binary, and with the recently added support for multiple non-contiguous program segments in BL31 it can grow close to 4GB in size (by having one section mapped near the start and one near the end of the address space). To avoid clogging up people's hard drives with 4GB of zeroes, let's only build the target we actually need. BRANCH=gru BUG=chrome-os-partner:56314,chromium:661124 TEST=FEATURES=noclean emerge-kevin coreboot, confirm that there's no giant build/3rdparty/arm-trusted-firmware/bl31.bin file left in the build artifacts, and that we still generate .d prerequisite files. Change-Id: I8e7bd50632f7831cc7b8bec69025822aec5bad27 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 31699820f4c36fd441a3e7271871af4e1474129f Original-Change-Id: Iaa073ec11dabed7265620d370fcd01ea8c0c2056 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/407110 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/17380 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-11-17arch/x86/acpigen: acpigen buffer size fixNaresh G Solanki
In function definition of acpigen_write_byte_buffer, buffer size written using acpigen_emit_byte gives wrong results in generated AML code for buffer size greater than one. Write buffer size using acpigen_write_integer as per ACPI spec 5.0 section 20.2.5.4 BufferOp. Change-Id: I0dcb25b24a1b4b592ad820c95f7c2df67a016594 Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com> Reviewed-on: https://review.coreboot.org/17444 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-11-16arch/x86/acpigen: Fix acpigen for If (Lequal (...))Furquan Shaikh
acpigen_write_if_lequal is used to generate ACPI code to check if two operands are equal, where operand1 is an ACPI op and operand2 is an integer. Update name of function to reflect this and fix code to write integer instead of emitting byte for operand2. TEST=Verified by disassembling SSDT on reef that ACPI code generated for If with operand2 greater than 1 is correct. If ((Local1 == 0x02)) { Return (0x01) } Else { Return (Buffer (One) { 0x00 /* . */ }) } Change-Id: If643c078b06d4e2e5a084b51c458dd612d565acc Reported-by: Naresh G Solanki <naresh.solanki@intel.com> Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/17421 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-14riscv: add a variable to control trap managementRonald G. Minnich
This variable can be set in a debugger (e.g. Spike) to finely control which traps go to coreboot and which go to the supervisor. Change-Id: I292264c15f002c41cf8d278354d8f4c0efbd0895 Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: https://review.coreboot.org/17404 Tested-by: build bot (Jenkins) Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
2016-11-13riscv: change payload() to pass the config string pointer as arg0Ronald G. Minnich
The riscv 1.9 standard defines a textual config string to be passed to kernels and hypervisors. Change the payload function to pass this string in a0. Change-Id: I3be7f1712accf2d726704e4c970f22749d3c3f36 Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: https://review.coreboot.org/17254 Tested-by: build bot (Jenkins) Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
2016-11-12riscv: start to use the configstring functionsRonald G. Minnich
These functions will allow us to remove hardcodes, as long as we can verify the qemu and lowrisc targets implement the configstring correctly. Hence, for the most part, we'll start with mainboard changes first. Define a new config variable, CONFIG_RISCV_CONFIGSTRING, which has a default value that works on all existing systems but which can be changed as needed for a new SOC or mainboard. Change-Id: I7dd3f553d3e61f1c49752fb04402b134fdfdf979 Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: https://review.coreboot.org/17256 Tested-by: build bot (Jenkins) Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
2016-11-09ACPI S3: Remove HIGH_MEMORY_SAVE where possibleKyösti Mälkki
Add implementation to use actual requirements of ramstage size for S3 resume backup in CBMEM. The backup covers complete pages of 4 KiB. Only the required amount of low memory is backed up when ACPI_TINY_LOWMEM_BACKUP is selected for the platform. Enable this option for AGESA and binaryPI, other platforms (without RELOCATABLE_RAMSTAGE) currently keep their romstage ramstack in low memory for s3 resume path. Change-Id: Ide7ce013f3727c2928cdb00fbcc7e7e84e859ff1 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/15255 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
2016-11-07arch/x86/acpigen: Add OperationRegion & Field methodNaresh G Solanki
Add acpigen_write_opregion that generates ACPI AML code for OperationRegion, region name, region space, region length & region size are inputs. Add acpigen_write_field that generates ACPI AML code for Field. Operation region name & field list are inputs. Change-Id: I578834217d39aa3b0d409eb8ba4b5f7a31969fa8 Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com> Reviewed-on: https://review.coreboot.org/17113 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins)
2016-11-07riscv: Unify SBI call implementations under arch/riscv/Jonathan Neuschäfer
Note that currently, traps are only handled by the trap handler installed in the bootblock. The romstage and ramstage don't override it. TEST=Booted emulation/spike-qemu and lowrisc/nexys4ddr with a linux payload. It worked as much as before (Linux didn't boot, but it made some successful SBI calls) Change-Id: Icce96ab3f41ae0f34bd86e30f9ff17c30317854e Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/17057 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2016-11-02riscv: Add a bandaid for the new toolchainRonald G. Minnich
After I did a new toolchain build, I found the the mhartid register value is wrong for Spike. The docs seem to agree with Spike, not the code the toolchain produces? Until such time as the bitstreams and toolchain can find a way to agree, just hardcode it. We've been playing this game for two years now so this is hardly a new approach. This is intentionally ugly because we really need the toolchains and emulators and bitstreams to sync up, and that's not happening yet. Lowrisc allegedly implements the v1.9 spec but it's PTEs are clearly 1.7. Once it all settles down we can just use constants supplied by the toolchain. I hope the syncup will have happened by the workshop in November. This gets spike running again. Change-Id: If259bcb6b6320ef01ed29a20ce3d2dcfd0bc7326 Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: https://review.coreboot.org/17183 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
2016-10-25arch/x86/acpigen_dsm: Add support for DSM typesFurquan Shaikh
Currently, the only supported DSM type is I2C HID(3CDFF6F7-4267-4555-AD05-B30A3D8938DE). This provides the required callbacks for generating ACPI AML codes for different function identifiers for I2C HID. BUG=chrome-os-partner:57846 Change-Id: Ia403e11f7ce4824956e3c879547ec927478db7b1 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/17091 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-10-25arch/x86/acpigen: Add support for _DSM method generationFurquan Shaikh
Add acpigen_write_dsm that generates ACPI AML code for _DSM method. Caller should provide set of callbacks with callback[i] corresponding to function index i of DSM method. Local0 and Local1 should not be used in any of the callbacks. BUG=chrome-os-partner:57846 Change-Id: Ie18cba080424488fe00cc626ea50aa92c1dbb199 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/17090 Tested-by: build bot (Jenkins) Reviewed-by: Alexander Couzens <lynxis@fe80.eu> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-10-25arch/x86/acpigen: Add more functions to ACPIGEN libraryFurquan Shaikh
1. If (LEqual (Op1, Op2)) 2. ToBuffer (src, dst) 3. ToInteger (src, dst) 4. Buffer (n) { op1, op2 .... } 5. Return ( ) BUG=chrome-os-partner:57846 Change-Id: I24fe647c690b2dd4849f0c53b2672ac7a2caa2de Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/17088 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-10-24RISCV: Clean up the common architectural codeRonald G. Minnich
This version of coreboot successfully starts a Harvey (Plan 9) kernel as a payload, entering main() with no supporting assembly code for startup. The Harvey port is not complete so it just panics but ... it gets started. We provide a standard payload function that takes a pointer argument and makes the jump from machine to supervisor mode; the days of kernels running in machine mode are over. We do some small tweaks to the virtual memory code. We temporarily disable two functions that won't work on some targets as register numbers changed between 1.7 and 1.9. Once lowrisc catches up we'll reenable them. We add the PAGETABLES to the memlayout.ld and use _pagetables in the virtual memory setup code. We now use the _stack and _estack from memlayout so we know where things are. As time goes on maybe we can kill all the magic numbers. Change-Id: I6caadfa9627fa35e31580492be01d4af908d31d9 Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: https://review.coreboot.org/17058 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-10-24arch/x86/acpigen: Add support for interacting with GPIOsFurquan Shaikh
Since reading/toggling of GPIOs is platform-dependent task, provide an interface with common functions to generate ACPI AML code for manipulating GPIOs: 1. acpigen_soc_read_rx_gpio 2. acpigen_soc_get_tx_gpio 3. acpigen_soc_set_tx_gpio 4. acpigen_soc_clear_tx_gpio Provide weak implementations of above functions. These functions are expected to be implemented by every SoC that uses ACPI. This allows drivers to easily generate ACPI AML code to interact GPIOs. BUG=chrome-os-partner:55988 Change-Id: I3564f15a1cb50e6ca6132638447529648589aa0e Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/17080 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-10-24arch/x86/acpigen: Add new functions to acpigen libraryFurquan Shaikh
Add functions to support generation of following AML operations: 1. PowerResource 2. Store 3. Or 4. And 5. Not 6. Debug 7. If 8. Else 9. Serialized method BUG=chrome-os-partner:55988 Change-Id: I606736b38e6a55ffdc3e814b6ae0fa367ef7595b Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/17079 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
2016-10-24arch/x86/acpigen: Clean up acpigen libraryFurquan Shaikh
Instead of using hard-coded values for emitting op codes and prefix codes, define and use enum constants. With this change, it becomes easier to read the code as well. BUG=chrome-os-partner:55988 Change-Id: I6671b84c2769a8d9b1f210642f3f8fd3d902cca2 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/17078 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-10-18arch/riscv: In trap handler, don't print SP twiceJonathan Neuschäfer
The stack pointer (SP) is already printed in print_trap_information. Don't print it again in handle_misaligned_{load,store}. Change-Id: I156cf5734a16605decc2280e54e6db3089e094a2 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/16996 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>