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2019-12-19src: Remove unused 'include <arch/cpu.h>'Elyes HAOUAS
Change-Id: Iaa236f07aed52ccb8c4839047894a14a9446a109 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36080 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-12-19src/arch: Remove unused <stdlib.h>Elyes HAOUAS
Change-Id: I79f065703b5249ca9630b06de7142bc52675076e Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32820 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-19src/arch/arm: Remove unused 'include <stdint.h>'Elyes HAOUAS
Change-Id: I35f3559d68866a734666b3a18038bdae628703c8 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37501 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-19arch/x86: Drop uses of ROMCC_BOOTBLOCKArthur Heymans
Change-Id: Ia0405fdd448cb31b3c6ca3b3d76e49e9f430bf74 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37339 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2019-12-19Drop ROMCC code and header guardsArthur Heymans
Change-Id: I730f80afd8aad250f26534435aec24bea75a849c Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37334 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2019-12-16arch/x86: Make X86 stages select ARCH_X86Arthur Heymans
Also, don't define the default as this results in spurious lines in the .config. TEST: Build all boards with where config.h differed with BUILD_TIMELESS=1 and remained the same Change-Id: Ic77b696f493d7648f317f0ba0a27fdee5212961e Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31316 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-14bootblock: Provide some common prototypesKyösti Mälkki
The split of bootblock initialisation to cpu, northbridge and southbridge is not specific to intel at all, create new header <arch/bootblock.h> as AMD will want some of these too. Change-Id: I702cc6bad4afee4f61acf58b9155608b28eb417e Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37429 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-12-12acpigen: Add methods for mutex operationsPatrick Rudolph
Tested on Linux 5.2: Dumped and decoded the ACPI tables using iasl. Change-Id: I79310b0f9e2297cf8428d11598935164caf95968 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37637 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-12-11printf: Automatically prefix %p with 0xJulius Werner
According to the POSIX standard, %p is supposed to print a pointer "as if by %#x", meaning the "0x" prefix should automatically be prepended. All other implementations out there (glibc, Linux, even libpayload) do this, so we should make coreboot match. This patch changes vtxprintf() accordingly and removes any explicit instances of "0x%p" from existing format strings. How to handle zero padding is less clear: the official POSIX definition above technically says there should be no automatic zero padding, but in practice most other implementations seem to do it and I assume most programmers would prefer it. The way chosen here is to always zero-pad to 32 bits, even on a 64-bit system. The rationale for this is that even on 64-bit systems, coreboot always avoids using any memory above 4GB for itself, so in practice all pointers should fit in that range and padding everything to 64 bits would just hurt readability. Padding it this way also helps pointers that do exceed 4GB (e.g. prints from MMU config on some arm64 systems) stand out better from the others. Change-Id: I0171b52f7288abb40e3fc3c8b874aee14b9bdcd6 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37626 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: David Guckian
2019-12-06arch|cpu/x86: Add Kconfig option for x86 reset vectorMarshall Dawson
Prepare for an implementation supporting the reset vector in RAM and not the traditional 0xfffffff0. Add a Kconfig symbol that can be used in place of hardcoded values. Change-Id: I6a814f7179ee4251aeeccb2555221616e944e03d Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37485 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-12-05arm64: Print a char to UART early in exception handlerJulius Werner
Over time our printk() seems to acquire more and more features... which is nice, but it also makes it a little less robust when something goes wrong. If the wrong global is trampled by some buffer overflow, it suddenly doesn't print anymore. It would be nice to have at least some way to tell that we triggered a real exception in that case. With this patch, arm64 exceptions will print a '!' straight to the UART before trying any of the more fancy printk() stuff. It's not much but it should tell the difference between an exception and a hang and hopefully help someone dig in the right direction sooner. This violates loglevels (which is part of the point), but presumably when you have a fatal exception you shouldn't care about that anymore. Change-Id: I3b08ab86beaee55263786011caa5588d93bbc720 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37465 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-05arm64: Bump exception stack size to 2KBJulius Werner
To avoid trampling over interesting exception artifacts on the real stack, our arm64 systems switch to a separate exception stack when entering an exception handler. We don't want that to use up too much SRAM so we just set it to 512 bytes. I mean it just prints a bunch of registers, how much stack could it need, right? Quite a bit it turns out. The whole vtxprintf() call stack goes pretty deep, and aarch64 generally seems to be very generous with stack space. Just the varargs handling seems to require 128 bytes for some reason, and the other stuff adds up too. In the end the current implementation takes 1008 bytes, so bump the exception stack size to 2K to make sure it fits. Change-Id: I910be4c5f6b29fae35eb53929c733a1bd4585377 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37464 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2019-12-05arm64: Correctly unmask asynchronous SError interruptsJulius Werner
Arm CPUs have always had an odd feature that allows you to mask not only true interrupts, but also "external aborts" (memory bus errors from outside the CPU). CPUs usually have all of these masked after reset, which we quickly learned was a bad idea back when bringing up the first arm32 systems in coreboot. Masking external aborts means that if any of your firmware code does an illegal memory access, you will only see it once the kernel comes up and unmasks the abort (not when it happens). Therefore, we always unmask everything in early bootblock assembly code. When arm64 came around, it had very similar masking bits and we did the same there, thinking the issue resolved. Unfortunately Arm, in their ceaseless struggle for more complexity, decided that having a single bit to control this masking behavior is no longer enough: on AArch64, in addition to the PSTATE.DAIF bits that are analogous to arm32's CPSR, there are additional bits in SCR_EL3 that can override the PSTATE setting for some but not all cases (makes perfect sense, I know...). When aborts are unmasked in PSTATE, but SCR.EA is not set, then synchronous external aborts will cause an exception while asynchronous external aborts will not. It turns out we never intialize SCR in coreboot and on RK3399 it comes up with all zeroes (even the reserved-1 bits, which is super weird). If you get an asynchronous external abort in coreboot it will silently hide in the CPU until BL31 enables SCR.EA before it has its own console handlers registered and silently hangs. This patch resolves the issue by also initializing SCR to a known good state early in the bootblock. It also cleans up some bit defintions and slightly reworks the DAIF unmasking... it doesn't actually make that much sense to unmask anything before our console and exception handlers are up. The new code will mask everything until the exception handler is installed and then unmask it, so that if there was a super early external abort we could still see it. (Of course there are still dozens of other processor exceptions that could happen which we have no way to mask.) Change-Id: I5266481a7aaf0b72aca8988accb671d92739af6f Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37463 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2019-12-04Change all clrsetbits_leXX() to clrsetbitsXX()Julius Werner
This patch changes all existing instances of clrsetbits_leXX() to the new endian-independent clrsetbitsXX(), after double-checking that they're all in SoC-specific code operating on CPU registers and not actually trying to make an endian conversion. This patch was created by running sed -i -e 's/\([cs][le][rt]bits\)_le\([136][624]\)/\1\2/g' across the codebase and cleaning up formatting a bit. Change-Id: I7fc3e736e5fe927da8960fdcd2aae607b62b5ff4 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37433 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2019-12-03src: Add missing include <stdlib.h>Elyes HAOUAS
Change-Id: I17dc2fed6c6518daf5af286788c98c049088911e Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37366 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2019-11-30kill CAR_GLOBAL_MIGRATION leftoversArthur Heymans
Change-Id: Ia3b2c10af63cd0cab42dc39f479cb69bc4df9124 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37055 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-30arch/x86/car.ld: Drop CAR_GLOBAL regionArthur Heymans
Change-Id: Id66fd0528987fb3e464d400cf9ccac98752fb8f5 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37327 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-30arch/*/*/early_variables.h: drop unused filesArthur Heymans
Kill off NO_GLOBAL_MIGRATION finally! Change-Id: Ieb7d9f5590b3a7dd1fd5c0ce2e51337332434dbd Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37054 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-30arch/x86/cache.h: Use ENV_CACHE_AS_RAM macroArthur Heymans
Change-Id: Ic7b088a04165bb24b9ebcebc1580a96ce0fdfcc8 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37063 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-11-29arch/x86/exception.c: Drop CAR_GLOBAL_MIGRATION supportArthur Heymans
Change-Id: I9e0d62d45e5b11a0c2f0867633cde2378f305ec8 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37048 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-28arch/arm/include: Remove unused armv7 types.hJacob Garber
This header was originally copied from the Linux kernel. However, these days all fixed-width integers are defined in stdint.h, and all of the other typedefs in this file are kernel-specific and aren't used anywhere, so we can drop it. Change-Id: I6ee7acb5e12f4b4b7c4325cedcfee36b93ab6a3d Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37257 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-11-26arch/x86: SMBIOS: Improve core count reportingAndrey Petrov
Current code uses CPUID leaf 0x1, EBX bits 16:23 to determine number for "core count". However, it turns out this number has little to do with real number of cores. According to SDM vol 2A, it stays for "maximum number of addressable IDs for logical processors in this physical package". This does not seem to take into account fusing of giving processor. The new code determines 'core count' by dividing thread-level cpus by reported logical cores. This seems to be the only way to arrive to number of cores as it is reported in official CPU datasheet. TEST=tested on OCP monolake Change-Id: Id4ba9e3079f92ffe38f9104ffcfafe62582dd259 Signed-off-by: Andrey Petrov <anpetrov@fb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36941 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2019-11-25Kconfig: Drop the C_ENVIRONMENT_BOOTBLOCK symbolArthur Heymans
The romcc bootblock will be deprecated soon and most platforms use C_ENVIRONMENT_BOOTBLOCK already. This patch drops the CONFIG_C_ENVIRONMENT_BOOTBLOCK symbol and adds CONFIG_ROMCC_BOOTBLOCK where needed. Change-Id: I773a76aade623303b7cd95ebe9b0411e5a7ecbaf Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37154 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2019-11-23Kconfig: comply to Linux 5.3's Kconfig language rulesPatrick Georgi
Kconfig became stricter on what it accepts, so accomodate before updating to a new release. Change-Id: I92a9e9bf0d557a7532ba533cd7776c48f2488f91 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37156 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2019-11-22arch/acpigen.h: Correct PARENT_PREFIX encoding valueElyes HAOUAS
The encoding value for PARENT_PREFIX is 0x5e. (ACPI specification version 6.3 page 1073) Change-Id: Ibbacb8b445157b377772f09572f87f8300a278dd Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36652 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-22Makefiles: Remove -D__PRE_RAM__Kyösti Mälkki
All cases of testing for __PRE_RAM__ have been converted to equivalent ENV_xxx definitions from <rules.h>. Change-Id: Ib6cd598f17109cc1072818cebe4791f7410c3428 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37075 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-11-22arch/x86: Remove spinlocks inside CARKyösti Mälkki
This was only used with amdfam10h-15h, where cache coherency between nodes was supposed to be guaranteed with this code. We could want a cleaner and more generic approach for this, possibly utilising .data sections. Change-Id: I00da5c2b0570c26f2e3bb464274485cc2c08c8f0 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34929 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-11-21arch/x86: Remove copy_and_run()Kyösti Mälkki
Nothing but a wrapper for run_ramstage() with an ugly name. Change-Id: Ie443a27cf18f829496ddadcc19c4ebec6a0b5a59 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/30389 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-11-21cpu/amd/fam10: Drop supportArthur Heymans
Relocatable ramstage, postcar stage and C_ENVIRONMENT_BOOTBLOCK are now mandatory features, which this platform lacks. Change-Id: I3c69f158a5667783292161815f9ae61195b5e03b Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36963 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-21drivers/intel/fsp1_0: Drop supportArthur Heymans
No platform is using this. Change-Id: I3ea6df4d9ce9043755f319f699adc189d754df1f Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36985 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2019-11-20Remove MIPS architectureJulius Werner
The MIPS architecture port has been added 5+ years ago in order to support a Chrome OS project that ended up going nowhere. No other board has used it since and nobody is still willing or has the expertise and hardware to maintain it. We have decided that it has become too much of a mainenance burden and the chance of anyone ever reviving it seems too slim at this point. This patch eliminates all MIPS code and MIPS-specific hacks. Change-Id: I5e49451cd055bbab0a15dcae5f53e0172e6e2ebe Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34919 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-19lib/fmap: Disable pre-RAM cache for FSP 1.0Julius Werner
Due to the way CAR teardown is handled in FSP 1.0, the results of car_get_var_ptr() aren't always reliable, which can break things when running with FMAP cache. It might be possible to fix this but would make the code rather complicated, so let's just disable the feature on these platforms and hope they die out soon. Also allow this option to be used by platforms that don't have space for the cache and want to save a little more code. Change-Id: I7ffb1b8b08a7ca3fe8d53dc827e2c8521da064c7 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36937 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-11-18include: Make stdbool.h a separate fileJulius Werner
This patch moves the traditional POSIX stdbool.h definitions out from stdint.h into their own file. This helps for using these definitions in commonlib code which may be compiled in different environments. For coreboot everything should chain-include this stuff via types.h anyway so nothing should change. Change-Id: Ic8d52be80b64d8e9564f3aee8975cb25e4c187f5 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36837 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-11-14lib/fmap: Add optional pre-RAM cacheJulius Werner
This patch adds an optional pre-RAM cache for the FMAP which most platforms should be able to use, complementing the recently added post-RAM FMAP cache in CBMEM. vboot systems currently read the FMAP about half a dozen times from flash in verstage, which will all be coalesced into a single read with this patch. It will also help future vboot improvements since when FMAP reads become "free" vboot doesn't need to keep track of so much information separately. In order to make sure we have a single, well-defined point where the new cache is first initialized, eliminate the build-time hardcoding of the CBFS section offsets, so that all CBFS accesses explicitly read the FMAP. Add FMAP_CACHEs to all platforms that can afford it (other than the RISC-V things where I have no idea how they work), trying to take the space from things that look like they were oversized anyway (pre-RAM consoles and CBFS caches). Change-Id: I2820436776ef620bdc4481b5cd4b6957764248ea Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36657 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Joel Kitching <kitching@google.com>
2019-11-13arch/x86: Correctly determine number of enabled coresAndrey Petrov
Instead of using MAX of (cores_enabled, MAX_CPUS), use MIN which is correct. TEST=tested with dmidecode Change-Id: Id0935f48e73c037bb7c0e1cf36f94d98a40a499c Signed-off-by: Andrey Petrov <anpetrov@fb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36662 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-11-12arch/x86/car.ld: Rename suffix _start/_endArthur Heymans
This is more in line with how linker symbol for regions are defined. Change-Id: I0bd7ae59a27909ed0fd38e6f7193816cb57e76af Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36695 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-11-11console,boot_state: Exclude printk() from reported timesKyösti Mälkki
Use monotonic timer to accumulate the time spent in console code. For bootblock and romstage, only stage total is reported. For ramstage each boot_state is reported individually. Change-Id: Id3998bab553ff803a93257a3f2c7bfea44c31729 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36574 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-11-10arch/x86: Remove EARLY_EBDA_INIT supportArthur Heymans
This is unused now. Change-Id: Ie8bc1d6761d66c5e1dda40c34c940cdba90646d2 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36363 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-11-10lib/Kconfig: Remove RAMSTAGE_CBMEM_TOP_ARGArthur Heymans
All targets now have the _cbmem_top_ptr symbol populated via calling arguments or in the nvidia/tegra210 case worked around by populating it with cbmem_top_chipset explicitly at the start of ramstage, so the Kconfig guarding this behavior can be removed. Change-Id: Ie7467629e58700e4d29f6e735840c22ed687f880 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36422 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Michael Niewöhner Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-10arch/riscv: Pass cbmem_top to ramstage via calling argumentArthur Heymans
Tested on the Qemu-Virt target both 32 and 64 bit. Change-Id: I5c74cd5d3ee292931c5bbd2e4075f88381429f72 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36558 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-06arch/x86: Create preprocessed __ROMCC__ bootblock sourceKyösti Mälkki
Output file is used only as a debugging aid. Change-Id: Iea9e1a66409659b47dfa3945c63fa1a7874de1ca Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35602 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-11-06arch/riscv: Use FDT from calling argument when using FITArthur Heymans
Only FIT payloads provide their own FDT. Change-Id: Id08a12ad7b72ad539e934a133acf2c4a5bcdf1f9 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36599 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-06arch/riscv: Rename `stages.c` to `romstage.c`Nico Huber
It's only used for romstage and is incompatible to ramstages. The latter get `cbmem_top` passed as a third argument now. Also drop comments that don't apply to this file anymore. Change-Id: Ibabb022860f5d141ab35922f30e856da8473b529 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36611 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-11-05arch/riscv: Don't link `stages.c` into ramstageNico Huber
It's superseded by `ramstage.S`. Change-Id: I81648da2f2af3ad73b3b51471c6fa2daac0540b1 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36610 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-05security/vboot: Removed vboot_prepare from vboot_locatorWim Vervoorn
When prog_locate() is called in the stage VBOOT is starting from and the image to be loaded is not the target image vboot_prepare() may be called too early. To prevent this vboot_prepare() is removed from the vboot_locator structure. This allows more control over the start of the vboot logic. To clarify the change the vboot_prepare() has been renamed to vboot_run_logic() and calls to initialize vboot have been added at the following places: postcar_loader: when VBOOT starts in ROMSTAGE romstage_loader: when VBOOT starts in BOOTBLOCK ramstage_loader: when VBOOT starts in ROMSTAGE BUG=N/A TEST=tested on facebook fbg1701 Change-Id: Id5e8fd78458c09dd3896bfd142bd49c2c3d686df Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36543 Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-04cpu/qemu-x86: Add x86_64 bootblock supportPatrick Rudolph
Add support for x86_64 bootblock on qemu. Introduce a new approach to long mode support. The previous patch set generated page tables at runtime and placed them in heap. The new approach places the page tables in memory mapped ROM. Introduce a new tool called pgtblgen that creates x86 long mode compatible page tables and writes those to a file. The file is included into the CBFS and placed at a predefined offset. Add assembly code to load the page tables, based on a Kconfig symbol and enter long in bootblock. The code can be easily ported to real hardware bootblock. Tested on qemu q35. Change-Id: Iec92c6cea464c97c18a0811e2e91bc22133ace42 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35680 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-11-04arch/mips: Pass cbmem_top to ramstage via calling argumentArthur Heymans
This allows to use a common cbmem_top implementation. Change-Id: I85efe3899607854c36d0ec594868f690eb724a7f Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36421 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-11-04soc/nvidia/tegra210: Populate _cbmem_top_ptrArthur Heymans
On this platform the ramstage is run on a different core so passing cbmem_top via calling arguments is not an option. To work around this populate _cbmem_top_ptr with cbmem_top_chipset which is also used in romstage. Change-Id: I8799c12705e944162c05fb7225ae21d32a2a882b Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36557 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-04arch/ppc64: Pass cbmem_top to ramstage via calling argumentArthur Heymans
This avoids the need for a platform specific implementation of cbmem_top. HOW TO TEST? There is no serial console for the qemu target... Change-Id: I68aa09a46786eba37c009c5f08642445805b08eb Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36276 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marty E. Plummer <hanetzer@startmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-11-04smbios: Create a type for smbios_enclosure_typeMathew King
Add a name to the SMBIOS enclosure type enum and use it as the return type for smbios_mainboard_enclosure_type. BUG=b:143701965 TEST=compiles Change-Id: I816e17f0de2b0c119ddab638e57b0652f53f5b61 Signed-off-by: Mathew King <mathewk@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36516 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-04arch/x86/Kconfig: drop unused BOOTBLOCK_SAVE_BIST_AND_TIMESTAMPElyes HAOUAS
Change-Id: I199a4b7771192abf7e7489e84db43b04776dd7b2 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36509 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-03arch/arm64: Pass cbmem_top to ramstage via calling argumentArthur Heymans
This solution is very generic and can in principle be implemented on all arch/soc. Currently the old infrastructure to pass on information from romstage to ramstage is left in place and will be removed in a follow-up commit. Nvidia Tegra will be handled in a separate patch because it has a custom ramstage entry. Instead trying to figure out which files can be removed from stages and which cbmem_top implementations need with preprocessor, rename all cbmem_top implementation to cbmem_top_romstage. Mechanisms set in place to pass on information from rom- to ram-stage will be replaced in a followup commit. Change-Id: I86cdc5c2fac76797732a3a3398f50c4d1ff6647a Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36275 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-11-03arch/arm: Pass cbmem_top to ramstage via calling argumentArthur Heymans
This solution is very generic and can in principle be implemented on all arch/soc. Instead trying to figure out which files can be removed from stages and which cbmem_top implementations need with preprocessor, rename all cbmem_top implementation to cbmem_top_romstage. Mechanisms set in place to pass on information from rom- to ram-stage will be placed in a followup commit. Change-Id: If31f0f1de17ffc92c9397f32b26db25aff4b7cab Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36145 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-11-03arch/x86: Use the stage argument to implement cbmem_topArthur Heymans
Currently all stages that need cbmem need an implementation of a cbmem_top function. On FSP and AGESA platforms this proves to be painful and a pointer to the top of lower memory if often passed via lower memory (e.g. EBDA) or via a PCI scratchpad register. The problem with writing to lower memory is that also need to be written on S3 as one cannot assume it to be still there. Writing things on S3 is always a fragile thing to do. A very generic solution is to pass cbmem_top via the program argument. It should be possible to implement this solution on every architecture. Instead trying to figure out which files can be removed from stages and which cbmem_top implementations need with preprocessor, rename all cbmem_top implementation to cbmem_top_romstage. TESTED on qemu-x86. Change-Id: I6d5a366d6f1bc76f26d459628237e6b2c8ae03ea Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36144 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2019-11-03cpu/x86/tsc: Flip and rename TSC_CONSTANT_RATE to UNKNOWN_TSC_RATEKyösti Mälkki
The x86 timers are a bit of a mess. Cases where different stages use different counters and timestamps use different counters from udelays. The original intention was to only flip TSC_CONSTANT_RATE Kconfig to NOT_CONSTANT_TSC_RATE. The name would be incorrect though, those counters do run with a constant rate but we just lack tsc_freq_mhz() implementation for three platforms. Note that for boards with UNKNOWN_TSC_RATE=y, each stage will have a slow run of calibrate_tsc_with_pit(). This is easy enough to fix with followup implementation of tsc_freq_mhz() for the platforms. Implementations with LAPIC_MONOTONIC_TIMER typically will not have tsc_freq_mhz() implemented and default to UNKNOWN_TSC_RATE. However, as they don't use TSC for udelay() the slow calibrate_tsc_with_pit() is avoided. Because x86/tsc_delay.tsc was using two different guards and nb/via/vx900 claimed UDELAY_TSC, but pulled UDELAY_IO implementation, we also switch that romstage to use UDELAY_TSC. Change-Id: I1690cb80295d6b006b75ed69edea28899b674b68 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33928 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-11-01arch/acpi.h: Use the predefined typedef acpi_addr_tHimanshu Sahdev
Use already declared typedef and modify the usage accordingly. Change-Id: Icc8413050bfae896d78605416aaaaa6a52eb39f1 Signed-off-by: Himanshu Sahdev <himanshusah@hcl.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36429 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-11-01lib/cbmem_top: Add a common cbmem_top implementationArthur Heymans
This adds a common cbmem_top implementation to all coreboot target. In romstage a static variable will be used to cache the result of cbmem_top_romstage. In ramstage if CONFIG_RAMSTAGE_CBMEM_TOP_ARG is set a global variable needs to be populated by the stage entry with the value passed via the calling arguments. if CONFIG_RAMSTAGE_CBMEM_TOP_ARG is not set the same implementation as will be used as in romstage. Change-Id: Ie767542ee25483acc9a56785ce20a885e9a63098 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36273 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-10-30Program loading: Handoff cbmem_top via calling argumentsArthur Heymans
There are a lot of different implementations to pass information from romstage to ramstage. These could all be unified by passing this information via cbmem. Often however these methods exist for that very purpose. This solves this by passing cbmem_top via the programs arguments. Change-Id: Id2031f7bb81ce65fc318313c270eb1fbae3b2114 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36272 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-30arch/x86/boot.c: Pass arguments when running programsArthur Heymans
Payloads can use coreboot tables passed on via arguments instead of via a pointer in lower memory. Stages can make use of the argument to pass on information. Change-Id: Ie0f44e9e1992221e02c49d0492cdd2a3d9013560 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36143 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-30arch/x86/Makefile.inc: Use the 'all' target to add common sourcesArthur Heymans
Change-Id: Ibbd418656c32f56be2b00481068e8499421b147c Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36002 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-10-29arch/x86/*.S: use defines instead of hardcoded valuesPatrick Rudolph
As preparation for x86_64 clean the assembly code and introduce arch/ram_segs.h similar to existing arch/rom_segs.h. Replace open coded segment values with the defines from the new header. Change-Id: Ib006cd4df59951335506b8153e9347450ec3403e Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36321 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-28arch/x86: Populate more fields in SMBIOS type 4Andrey Petrov
If CPUID leaf 0x16 is available (Skylake and later) use it to obtain current and maximum speed. Otherwise call weak function that can be provided elsewhere (cpu/soc/mainboard). Also, populate "core enabled" with the same value as "core count". TEST=tested on OCP Monolake with dmidecode -t processor Change-Id: Ie5d88dacae6623dfa0ceb3ca1bb5eeff2adda103 Signed-off-by: Andrey Petrov <anpetrov@fb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36283 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2019-10-28arch/x86: Move max cpuid leaf function into arch/x86Andrey Petrov
This cpuid function (0) is same across Intel and AMD so having it in arch/x86 seems like a good idea. Change-Id: I38f1c40bceac38ed6428f74b08bf60b971644f5a Signed-off-by: Andrey Petrov <anpetrov@fb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36282 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2019-10-27src/[arch-lib]: change "unsigned" to "unsigned int"Martin Roth
Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: Ibb7b48a7a144421aff29acbb7ac30968ae5fe5ab Reviewed-on: https://review.coreboot.org/c/coreboot/+/36329 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-10-25arch/acpi.h: Convert MADT APIC type names to all capsHimanshu Sahdev
Convert names to all capital in enum acpi_apic_types. Use of these names in corresponding type assign for I/O APIC Structure. Change-Id: Iab2f6d8f645677734df753f8bf59fde4205ce714 Signed-off-by: Himanshu Sahdev <himanshusah@hcl.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36197 Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-25arch/acpi.h: Use the aforementioned typedef acpi_table_headerHimanshu Sahdev
Use already declared typedef and modify the usage accordingly. Change-Id: Icf12ab9059be444fbe252b26e70214b1ef062c72 Signed-off-by: Himanshu Sahdev <himanshusah@hcl.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36194 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-24arch/acpi.h: Use of typedef for acpi_vfctHimanshu Sahdev
Use of typedef and modify the usage accordingly. Change-Id: I875ef2fa31e65750233fa8da2b76d8db5db44f2d Signed-off-by: Himanshu Sahdev <himanshusah@hcl.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36193 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
2019-10-24arch/acpi.h: Use of typedef for acpi_vfct_image_hdrHimanshu Sahdev
Use of typedef and modify the usage accordingly. Change-Id: I65581702a60dbd286cb3910c6eeef5f9e1853cf1 Signed-off-by: Himanshu Sahdev <himanshusah@hcl.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36184 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
2019-10-20src: Remove unused 'include <string.h>'Elyes HAOUAS
Change-Id: I2a94c3b6282e9915fd2b8136b124740c8a7b774c Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36082 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-10-08arch/x86: Don't allow separate verstage to boot from romcc bootblockArthur Heymans
CONFIG_VBOOT_SEPARATE_VERSTAGE has a dependency on C_ENVIRONMENT_BOOTBLOCK so Kconfig already guards against this. Change-Id: I8f963a27f9023fd4c6ebc418059d57e00e4dfb4c Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35824 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-04arch/x86/acpi: Add SSDT for QEMUPatrick Rudolph
Add a SSDT on qemu and place BOOT0000 inside it to allow testing the google firmware kernel module in qemu. Tested on Qemu Q35. Change-Id: Ibd1b2c2f4fc3db9ae8f338b0d53b2d00ea2c4190 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35382 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HIMANSHU SAHDEV <sahdev.himan@gmail.com> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2019-10-01cpu/intel/common: Move intel_ht_sibling() to common folderPatrick Rudolph
Make intel_ht_sibling() available on all platforms. Will be used in MP init to only write "Core" MSRs from one thread on HyperThreading enabled platforms, to prevent race conditions and resulting #GP if MSRs are written twice or are already locked. Change-Id: I5d000b34ba4c6536dc866fbaf106b78e905e3e35 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35619 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-09-30arch/x86: Fix __ROMCC__ automatic prerequisitiesKyösti Mälkki
While the list of prerequisities is not created with romcc, we need to simulate it since different set of header files will is used. Change-Id: Ib799c872b5280e2035126f9660e04e51acc4b1a8 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35601 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-28cpu,device/: Remove some __SIMPLE_DEVICE__ and __ROMCC__ useKyösti Mälkki
Change-Id: I62d7450c8e83eec7bf4ad5d0709269a132fd0499 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35649 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-09-28arch/arm,mips: Use generic PCI MMCONFKyösti Mälkki
We need the stub header file. If PCI was implemented, assume generic MMIO mapped configuration space would work here. Change-Id: Ia731e5c5a6725fe22ab8b0398cafa1127ed90891 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35648 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-09-26arch/: Replace __BOOTBLOCK__ with ENV_BOOTBLOCKKyösti Mälkki
Change-Id: I294a3fd7be57b505cd209f7c2718a05770786c51 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35599 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-09-14arch/x86: Replace some __PRE_RAM__ useKyösti Mälkki
Change-Id: I4d8db430f8cd0bf0f161fc5cef052f153e59e2bc Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35390 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-14arch/x86: Remove acpi_fail_wakeup() and cbmem_fail_resume()Kyösti Mälkki
Unused since commit d46b8d5. Change-Id: If0f1e0381dd7698f842dc1288ff222a4d5d4783c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35389 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-14arm64: Uprev Arm TF and adjust to BL31 parameter changesJulius Werner
This patch uprevs the Arm Trusted Firmware submodule to the new upstream master (commit 42cdeb930). Arm Trusted Firmware unified a bunch of stuff related to BL31 handoff parameters across platforms which involved changing a few names around. This patch syncs coreboot back up with that. They also made header changes that now allow us to directly include all the headers we need (in a safer and cleaner way than before), so we can get rid of some structure definitions that were duplicated. Since the version of entry point info parameters we have been using has been deprecated in Trusted Firmware, this patch switches to the new version 2 parameter format. NOTE: This may or may not stop Cavium from booting with the current pinned Trusted Firmware blob. Cavium maintainers are still evaluating whether to fix that later or drop the platform entirely. Tested on GOOGLE_KEVIN (rk3399). Change-Id: I0ed32bce5585ce191736f0ff2e5a94a9d2b2cc28 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34676 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2019-09-13timestamps: Remove TIMESTAMP_CACHE_IN_BSSKyösti Mälkki
This was implemented for LATE_CBMEM_INIT support which has already been deprecated. Change-Id: I39225ba675bc3389e051e15b400a905431969715 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35375 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-13arch/x86/bootblock_crt0.S: Leverage eax in protected mode entryHimanshu Sahdev aka CunningLearner
Leverage already used eax register in bootblock_protected_mode_entry. Avoid another register ebx just for preserving eax value as it is not needed and is not used at all after moving the value into mm0. Allow EBX to be preserved for other usage. Change-Id: Ia668b78f2f97cf026692f1fe63ff8a382a162474 Signed-off-by: Himanshu Sahdev <himanshusah@hcl.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35292 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-11arch/x86: Cache the TSEG region at the top of ramSubrata Banik
This patch adds new API for enabling caching for the TSEG region and setting up required MTRR for next stage. BUG=b:140008206 TEST=Build and boot CML-Hatch. Change-Id: I59432c02e04af1b931d77de3f6652b0327ca82bb Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34995 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-09-11arch/x86: Restrict use of _car_global[start|end]Kyösti Mälkki
Restrict the use of symbol names _car_global_[start|end] to be used exclusively with CAR_GLOBAL_MIGRATION=y. They just alias the start and end of .bss section in CAR. Change-Id: I36c858a4f181516d4c61f9fd1d5005c7d2c06057 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35034 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2019-09-11arch/x86: Drop _car_relocatable_data symbolsKyösti Mälkki
These have become aliases to _car_global_[start|end]. Change-Id: Ibdcaaafdc0e4c6df4a795474903768230d41680d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35033 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2019-09-11arch/x86: Move ehci_dbg_info outside _car_relocatable_dataKyösti Mälkki
As code already used CBMEM hooks to switch from CAR to CBMEM it was never necessary to have the structure declared inside _car_relocatable_data. Switch to use car_[get|set]_ptr is mostly for consistency, but should also enable use of usbdebug with FSP1.0 romstage. Change-Id: I636251085d84e52a71a1d5d27d795bb94a07422d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35288 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-09-11timestamps: Improve collection for ENV_ROMSTAGE_OR_BEFOREKyösti Mälkki
Keep track of the active timestamp table location using a CAR_GLOBAL variable. Done this way, the entire table can be located outside _car_relocatable_data and we only switch the pointer to CBMEM and copy the data before CAR gets torn down. Fix comments about requirements of timestamp_init() usage. Remove timestamp_cache from postcar and ramstage, as CBMEM is available early on. Change-Id: I87370f62db23318069b6fd56ba0d1171d619cb8a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35032 Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-10AUTHORS: Move src/arch/x86 copyrights into AUTHORS fileMartin Roth
As discussed on the mailing list and voted upon, the coreboot project is going to move the majority of copyrights out of the headers and into an AUTHORS file. This will happen a bit at a time, as we'll be unifying license headers at the same time. Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: Ifd4329905847d9dd06de67b9a443c8ee50c0e7a7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/35177 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-09-09arch/x86: Refactor CAR_GLOBAL quirk for FSP1.0Kyösti Mälkki
These platforms return to romstage from FSP only after already having torn CAR down. A copy of the entire CAR region is available and discoverable via HOB. Previously, CBMEM console detected on-the-fly that CAR migration had happened and relocated cbmem_console_p accoringlin with car_sync_var(). However, if the CAR_GLOBAL pointing to another object inside CAR is a relative offset instead, we have a more generic solution that can be used with timestamps code as well. Change-Id: Ica877b47e68d56189e9d998b5630019d4328a419 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35140 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-06superio/common: Add ssdtgen for generic SuperIOsPatrick Rudolph
Add a generic SuperIO ACPI generator, dropping the need to include additional code in DSDT for SuperIO. It generates a device HID based on the decoded I/O range. Tested on Supermicro X11SSH-TF using AST2400. The SSDT contains no errors and all devices are present. Possible TODOs: * Add "enter config" and "exit config" bytes * Generate support methods to enter and exit config mode * Generate support methods to query, change or disable current resource settings on specific LDNs Change-Id: I2716ae0580d68e5d4fcc484cb1648a2cdc1f4ca0 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33033 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-09-02soc/intel/common/timer: Make TSC frequency calculation dynamicallySubrata Banik
tsc_freq_mhz() had a static table of Intel CPU families and crystal clock, but it is possible to calculate the crystal clock speed dynamically, and this is preferred over hardcoded table. On SKL/KBL/CML CPUID.15h.ecx = nominal core crystal clock = 0 Hz hence we had to use static table to calculate crystal clock. Recommendation is to make use of CPUID.16h where crystal clock frequency was not reported by CPUID.15h to calculate the crystal clock. BUG=b:139798422, b:129839774 TEST=Able to build and boot KBL/CML/ICL. Change-Id: If660a4b8d12e54b39252bce62bcc0ffcc967f5da Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35148 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: V Sowmya <v.sowmya@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-02arch/ppc64: move misc.c to qemu-power8 as timer.cMarty E. Plummer
Its entirely no-op and is getting in the way of real hardware timers for power9/talos ii. Change-Id: I2d21d4ac3d1a7d3f099ed6ec4faf10079b1ee1d1 Signed-off-by: Marty E. Plummer <hanetzer@startmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35082 Reviewed-by: Timothy Pearson <tpearson@raptorengineering.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-31arch/x86: Remove WB attribute from 0..CACHE_TMP_RAMTOPKyösti Mälkki
Platforms using postcar are with RELOCATABLE_RAMSTAGE=y. They don't benefit from having low-memory set as writeback-cacheable. This also fixes regression from CB:34893 that caused some random hangs with more recent intel SoCs in ramstage. BUG=b:140250314 Change-Id: Ia66910a6c85286f5c05823b87d48edc7e4ad9541 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35161 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-08-30arm64: Rename arm_tf.c/h to bl31.c/hJulius Werner
This patch renames arm_tf.c and arm_tf.h to bl31.c and bl31.h, respectively. That name is closer to the terminology used in most functions related to Trusted Firmware, and it removes the annoying auto-completion clash between arm64/arm_tf.c and arm64/armv8. Change-Id: I2741e2bce9d079b1025f82ecb3bb78a02fe39ed5 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34677 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2019-08-29arch/arm64: Make ARM64 stages select ARCH_ARM64Arthur Heymans
Also don't define the default as this result in spurious lines in the .config. The only difference in config.h is on boards with the Nvidia tegra210 SOC that now select ARCH_ARM64, because its ramstage runs in that mode. The resulting binary is identical however. Change-Id: Iaa9cd902281e51f823717f6ea4c72e5736fefb31 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31315 Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-29arch/arm: Make ARM stages select ARCH_ARMArthur Heymans
This removes the need to select ARCH_ARM in SOC Kconfig Also don't define the default as this result in spurious lines in the .config. Change-Id: I1ed4a71599641db606510e5304b9f0acf9b7eb88 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31313 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-29arch/x86: Fix clearing .bss sectionKyösti Mälkki
Using stosl clears 4 bytes at a time. Change-Id: Ie54fcfcb7e5a2a5a88d988476aa69b2a163e919c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35139 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2019-08-29arch/x86: remove weak car_stage_entry() symbolAaron Durbin
Many (if not all) platforms have moved to using consistent boot flow constructs where a weak car_stage_entry() is no longer necessary to avoid the complexity of handling the numerous and different boot flow combinations. The weak symbol is just causing issues so remove it. Change-Id: I7e7897c0609aac8eef96a08bb789374b2403956d Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35135 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-28arch/x86/postcar: unexpose postcar_commit_mtrrs() symbolAaron Durbin
postcar_commit_mtrrs() isn't used outside the postcar_loader compilation unit. Make it static to reduce API surface area. Additionally the return value was not being utilized. Modify the return type to be void to align with the current usage. Change-Id: If07f34467941d00de731489867e485cfff80ea63 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35130 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-08-28AUTHORS: Move src/arch/ppc64 copyrights into AUTHORS fileMartin Roth
As discussed on the mailing list and voted upon, the coreboot project is going to move the majority of copyrights out of the headers and into an AUTHORS file. This will happen a bit at a time, as we'll be unifying license headers at the same time. Additional changes in this patch: - Move descriptions below the license header Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: I51d5b1f01ff47ed752761116e3f32cb9e168584f Reviewed-on: https://review.coreboot.org/c/coreboot/+/34637 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-27AUTHORS: Move src/arch/mips copyrights into AUTHORS fileMartin Roth
As discussed on the mailing list and voted upon, the coreboot project is going to move the majority of copyrights out of the headers and into an AUTHORS file. This will happen a bit at a time, as we'll be unifying license headers at the same time. Additional changes in this patch: - Remove comments saying that a file is based on another file from the coreboot project. Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: If61689db67c58f0d66ab96ca749bfcd589935ce2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/34607 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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