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2019-05-13src/arch/x86: Use core apic id to get cpu_index()Subrata Banik
This cpu_index() implementation assumes that cpu_index() function might always getting called from coreboot context (ESP stack pointer will always refer to coreboot). This might not be true in case of proposed PI spec MP_SERVICES_PPI implementation, where FSP context (stack pointer refers to fsp) will request to get cpu_index(), natural alignment logic will use ESP and retrieve struct cpu_info *ci from (stack_top - 8 byte). This is not the place where cpu_index is actually stored by ramstage c_start.S Hence this patch tries to remove those dependencies while retrieving cpu_index(), rather it uses cpuid to fetch lapic id and matches with cpus_default_apic_id[] variable to return correct cpu_index(). BRANCH=none BUG=b:79562868 TEST=Ensures functions can be run on APs without any failure and cpu_index() also provides correct index number. Change-Id: I55023a3e0cf42f0496d45bc6af8ead447f402350 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/26346 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-05-12nb/intel/snb: Drop NORTHBRIDGE_INTEL_IVYBRIDGENico Huber
We keep the support, though. Just now that `libgfxinit` is fixed, we don't need the distinction anymore. Causally, we also don't need CPU_INTEL_MODEL_306AX any more. TEST=Played tint on kontron/ktqm77. Score 606 Change-Id: Id1e33c77f44a66baacba375cbb2aeb71effb7b76 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32737 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-05-12arch/cpu: Rename mp_get_apic_id() and add_cpu_map_entry() functionSubrata Banik
This patch renames mp_get_apic_id() to cpu_get_apic_id() and add_cpu_map_entry() to cpu_add_map_entry() in order access it outside CONFIG_PARALLEL_MP kconfig scope. Also make below changes - Make cpu_add_map_entry() function available externally to call it from mp_init.c and lapic_cpu_init.c. BRANCH=none BUG=b:79562868 Change-Id: I6a6c85df055bc0b5fc8c850cfa04d50859067088 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32701 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-05-07smbios: Walk over PCI devicetree to fill type 9Patrick Rudolph
Use the devicetree values for type 9 slots. Tested on Lenovo T520. Change-Id: I1961d8af2d21f755ff52ad58804ea9b31d2a5b9b Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32308 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2019-05-06arch/x86: Remove unused filePatrick Rudolph
The file is no longer used by any code. Remove it. Change-Id: I73f06cac11201dc37218d352ab995cf4f012c36a Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32584 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2019-05-01arch/x86/acpi: Update VT-d DMA remapping structure flags settingJohn Zhao
DMA remapping structure flags settings are Bit 0: INTR_REMAP, Bit 1: X2APIC_OPT_OUT, Bit 2: DMA_CTRL_PLATFORM_OPT_IN_FLAG, Bits 3-7: Reserved (0). BUG=b:130351429 TEST=Image built and kernel booted to kernel. Signed-off-by: John Zhao <john.zhao@intel.com> Change-Id: Iaf4764a9062756cadc335d1932b0da8628797f5f Reviewed-on: https://review.coreboot.org/c/coreboot/+/32516 Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-26ACPI: Add RHSA and ANDD structures for DMAR tableJohn Zhao
Remapping Hardware Status Affinity (RHSA) structure is applicable for platforms supporting non-uniform memory. An ACPI Name-space Device Declaration (ANDD) structure uniquely represents an ACPI name-space enumerated device capable of issuing DMA requests in the platform. Add RHSA and ANDD structures support for DMAR table generation. BUG=b:130351429 TEST=Image built and booted to kernel Change-Id: I042925a7c03831061870d9bca03f11bf25aeb3e7 Signed-off-by: John Zhao <john.zhao@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32189 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-04-26x86/acpi: Add Kconfig to toggle 8259 reportingNico Huber
Change-Id: If3c9783ebc41c103c915788139d91644b805f397 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/29832 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2019-04-23arch/x86/car.ld: Make the vboot tpm log symbols conditionalArthur Heymans
Without VBOOT_MEASURED_BOOT there is no need for these symbols. Change-Id: I96391b7817c79f760713c67bc469164b5514879e Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32383 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-04-23smbios: Add memory type 9 system slot supportLijian Zhao
Add SMBIOS type 9 system slots into coreboot, the definiation is up to date with SMBIOS spec 3.2 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Change-Id: Ibcfa377c260083203c1daf5562e103001f76b257 Reviewed-on: https://review.coreboot.org/c/coreboot/+/32293 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-04-23ACPI: Clarify serial bus revision and specific revisionElyes HAOUAS
Serial bus revision [Byte 3] and serial bus specific revision [Byte 9] are not the same. Change-Id: I366f62e6aa0e9c0dfbc1ec17adeebc42a0e777eb Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32329 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
2019-04-23src: include <assert.h> when appropriateElyes HAOUAS
Change-Id: Ib843eb7144b7dc2932931b9e8f3f1d816bcc1e1a Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/26796 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: David Guckian
2019-04-23src: Use include <console/console.h> when appropriateElyes HAOUAS
Change-Id: Iddba5b03fc554a6edc4b26458d834e47958a6b08 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32214 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: David Guckian
2019-04-23src: Add missing include 'console.h'Elyes HAOUAS
Change-Id: Ie21c390ab04adb5b05d5f9760d227d2a175ccb56 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32122 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2019-04-22arch/x86/car.ld: Also check mrc.bin heap for IvybridgeArthur Heymans
Sandy- and ivybridge use the same mrc.bin that has the heap in an awkward location. Change-Id: If985a48c6703c8a86d8051e67595cf0fd409d99a Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32385 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-04-19smbios: Fix copy paste errorPatrick Rudolph
As reported by Coverity Scan CID 1400679. Change-Id: I526b78a0697b7eb3c3dc75974c3a3a714b3d343f Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32313 Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-19smbios: Add type 17 device/bank locator overrideLijian Zhao
Current SMBIOS type 17 device and bank locator string is like "Channel-x-Dimm-x" and "Bank-x", x is deciminal number. Give silicon or mainboard vendor a chance to replace with something matches with silkscreen. Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Change-Id: I54f7282244cb25a05780a3cdb9d1f5405c600513 Reviewed-on: https://review.coreboot.org/c/coreboot/+/32279 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2019-04-19acpi: Upgrade acpi generate headerLijian Zhao
Sync acpigen.h content to match with laetst acpica, the link is https://github.com/acpica/acpica/blob/master/source/include/amlcode.h, and revision is 20190405. The purspose of the change is just make spec up to date. Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Change-Id: If5f5da70eb66472ddf5df0d72ca85de41faac128 Reviewed-on: https://review.coreboot.org/c/coreboot/+/32328 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-04-17soc/intel/common/timer: Calculate TSC frequency based on CPUID 0x15Subrata Banik
This patch ensures to follow Intel SDM Vol 3B Sec 18.7.3 to calculate nominal TSC frequency. As per SDM recommendation: For any processor in which CPUID.15H is enumerated and MSR_PLATFORM_INFO[15:8] (which gives the scalable bus frequency) is available, a more accurate frequency can be obtained by using CPUID.15H This patch also adds header file to capture Intel processor model number. BUG=b:129839774 TEST=Boot ICL platform and calculate TSC frequency using below methods 1. TSC freq calculated based on MSR 0xCE tsc: Detected 1600.000 MHz processor 2. TSC freq calculated based on CPUID 0x15 tsc: Detected 1612.800 MHz TSC Method 2 actually reduce ~25ms of boot performance time. Note: Method 2 is recommended from gen 6 processor onwards. Change-Id: I9ff4b9159a94e61b7e634bd6095f7cc6d7df87c7 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32283 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
2019-04-09arch/x86/smbios: Reference type 7Patrick Rudolph
Fill in the handle to cache entries of type 7 in the type 4 structure. Tested on Intel Sandy Bridge (Lenovo T520). All 3 caches are referenced. Change-Id: Idf876b0c21c65f72a945d26c5898074b140763f8 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32132 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
2019-04-09arch/x86/smbios: Add type 7Patrick Rudolph
The SMBIOS spec requires type 7 to be present. Add the type 7 fields and enums for SMBIOS 3.1+ and fill it with the "Deterministic Cache Parameters" as available on Intel and AMD. As CPUID only provides partial information on caches, some fields are set to unknown. The following fields are supported: * Cache Level * Cache Size * Cache Type * Cache Ways of Associativity Tested on Intel Sandy Bridge (Lenovo T520). All 4 caches are displayed in dmidecode and show the correct information. Change-Id: I80ed25b8f2c7b425136b2f0c755324a8f5d1636d Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32131 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
2019-04-09arch/x86/cpu: Add functions to determine CPU vendorPatrick Rudolph
Add two functions to determine if CPU is made by a specific vendor. Use Kconfig symbols to allow link time optimizations. Change-Id: I1bd6c3b59cfd992f7ba507bc9f9269669920b24f Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32130 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Julien Viard de Galbert <coreboot-review-ju@vdg.name> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-04-07device/pci: Rewrite PCI MMCONF with symbol referenceKyösti Mälkki
The effect of pointer aliasing on writes is that any data on CPU registers that has been resolved from (non-const and non-volatile) memory objects has to be discarded and resolved. In other words, the compiler assumes that a pointer that does not have an absolute value at build-time, and is of type 'void *' or 'char *', may write over any memory object. Using a unique datatype for MMIO writes makes the pointer to _not_ qualify for pointer aliasing with any other objects in memory. This avoid constantly resolving the PCI MMCONF address, which is a derived value from a 'struct device *'. Change-Id: Id112aa5e729ffd8015bb806786bdee38783b7ea9 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31752 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-29src: Use include <reset.h> when appropriateElyes HAOUAS
Change-Id: I3b852cae4ef84d257bf1e5486447583bdd16b441 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/29301 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-03-29arch/x86/smbios(type4): Write processor_upgrade fieldElyes HAOUAS
Change-Id: I1bf5ac6c411720d349df8fd706015c6835758cd0 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/29529 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-27Revert "src/arch: An upgrade of SMBIOS to latest version 3.2"Nico Huber
This reverts commit b7daf7e8fa18de7bfb3cd102791bc6af89bac4b6. The review was spread across four different change-ids. Of course, not all comments were addressed, now coverity complains too. Change-Id: If5dbc1ae37120330ab192fb15eb4984afc84a7af Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32059 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-03-25Fix up remaining boolean uses of CONFIG_XXX to CONFIG(XXX)Julius Werner
This patch cleans up remaining uses of raw boolean Kconfig values I could find by wrapping them with CONFIG(). The remaining naked config value warnings in the code should all be false positives now (although the process was semi-manual and involved some eyeballing so I may have missed a few). Change-Id: Ifa0573a535addc3354a74e944c0920befb0666be Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31813 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-03-22src/arch: An upgrade of SMBIOS to latest version 3.2Francois Toguo
This is the second of 2 patches upgrading the SMBIOS interface to the latest 3.2 First patch is in mosys. Newer required fields are added to various types definitions BUG=NONE TEST=Boot to OS on GLK Sparky Change-Id: Iab98e063874c9738e48a387cd91341d266391156 Signed-off-by: Francois Toguo <francois.toguo.fotso@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31997 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
2019-03-22arch/mips: Fix <arch/mmio.h> prototypesKyösti Mälkki
These signatures need to be consistent across different architectures. Change-Id: Ide8502ee8cda8995828c77fe1674d8ba6f3aa15f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31995 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-03-21vboot: standardize on working data sizeJoel Kitching
Previously, the size of memory made for vboot_working_data through the macro VBOOT2_WORK was always specified in each individual memlayout file. However, there is effectively no reason to provide this customizability -- the workbuf size required for verifying firmware has never been more than 12K. (This could potentially increase in the future if key sizes or algorithms are changed, but this could be applied globally rather than for each individual platform.) This CL binds the VBOOT2_WORK macro to directly use the VB2_WORKBUF_RECOMMENDED_DATA_SIZE constant as defined by vboot API. Since the constant needs to be used in a linker script, we may not include the full vboot API, and must instead directly include the vb2_constants.h header. BUG=b:124141368, b:124192753 TEST=Build locally for eve TEST=util/lint/checkpatch.pl -g origin/master..HEAD TEST=util/abuild/abuild -B -e -y -c 50 -p none -x TEST=make clean && make test-abuild BRANCH=none CQ-DEPEND=CL:1504490 Change-Id: Id71a8ab2401efcc0194d48c8af9017fc90513cb8 Signed-off-by: Joel Kitching <kitching@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31474 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-03-21src/arch/mips: Fix checkpatch warnings and errorsAsami Doi
This patch will fix these checkpatch errors in src/arch/mips/. - src/arch/mips/ashldi3.c:22: WARNING: Prefer 'unsigned int' to bare use of 'unsigned' - src/arch/mips/bootblock_simple.c:35: WARNING: braces {} are not necessary for any arm of this statement Change-Id: Ic859913b93dc8ed6ff64b551c8a6baf72d28c75a Signed-off-by: Asami Doi <d0iasm.pub@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31938 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-03-21arch/ppc64: Add <arch/mmio.h> stubsKyösti Mälkki
The work may be incomplete, we only have an emulation power8 at the moment in the tree. Change-Id: Icdaa0995c8610dcc636923cc79b8455dfaeaa057 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31996 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Timothy Pearson <tpearson@raptorengineering.com>
2019-03-20src: Use 'include <string.h>' when appropriateElyes HAOUAS
Drop 'include <string.h>' when it is not used and add it when it is missing. Also extra lines removed, or added just before local includes. Change-Id: Iccac4dbaa2dd4144fc347af36ecfc9747da3de20 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31966 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-03-19src: Drop unused 'include <cbfs.h>'Elyes HAOUAS
Change-Id: If5c5ebacd103d7e1f09585cc4c52753b11ce84d0 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31953 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-03-16x86/smbios: Untangle system and board tablesNico Huber
We were used to set the same values in the system and board tables. We'll keep the mainboard values as defaults for the system tables, so nothing changes unless somebody overrides the system table hooks. Change-Id: I3c9c95a1307529c3137647a161a698a4c3daa0ae Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/29477 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2019-03-16device/pci_ops: Have only default PCI bus ops availableKyösti Mälkki
In the current state of the tree we do not utilise the mechanism of having per-device overrides for PCI bus ops. This change effectively inlines all PCI config accessors for ramstage as well. Change-Id: I11c37cadfcbef8fb5657dec6d620e6bccab311a4 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31753 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-03-16device/pci_ops: Reuse romstage PCI config for ramstageKyösti Mälkki
By changing the signatures we do not need to define PCI config accessors separately for ramstage. Change-Id: I9364cb34fe8127972c772516a0a0b1d281c5ed00 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31685 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-03-14arch/x86: Fix PCI IO config accessorKyösti Mälkki
In case PCI_IO_CFG_EXT=n parameter 'reg' was not properly truncated to 8 bits and it would overflow to dev.fn part of the register. A similar thing could happen with 'dev' but that value originates from PCI_DEV() macro unlike 'reg'. Change-Id: Id2888e07fc0f2b182b4633a747c1786e5c560678 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31847 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-14arch/x86: Optimise PCI IO config accessorKyösti Mälkki
By design only 'reg' parameter can have the two least- significant bits set. As 'reg' is often a constant, '0xCFC + (reg & 3)' resolves to an immediate value already at buildtime, unlike (addr & 3) which depends of a constant (but non-immediate) value of 'dev' in ramstage. Change-Id: I6e729fe800c92b1ce4994ad2b4203072fa75a958 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31754 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-14x86/acpi: Only sort CPU IDs if more than one availableWerner Zeh
Sorting makes only sense if there are at least two entries available. Change-Id: If40638bf1fe24dcff4b7839967445fb4218184f8 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31853 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-03-14x86/acpi: Fix Coverity issue CID 1399153Werner Zeh
This patch fixes Coverity issue CID 1399153: Uninitialized variables (UNINIT) Change-Id: I736b532c687612912271317b8941e69f41af00ba Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31782 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-13device/pci_ops: Rename 'where' to 'reg'Kyösti Mälkki
One could understand 'where' as bus, device, function or register. Make it clear it is register. Change-Id: I95d0330ba40510e48be70ca1d8f58aca66c8f695 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31846 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-03-13device/pci_ops: Unify signaturesKyösti Mälkki
Use fixed width types and const pointers for dev. Change-Id: Ide3b70238479ad3e1869ed22aa4fa0f1ff8aa766 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31845 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-03-08coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX)Julius Werner
This patch is a raw application of find src/ -type f | xargs sed -i -e 's/IS_ENABLED\s*(CONFIG_/CONFIG(/g' Change-Id: I6262d6d5c23cabe23c242b4f38d446b74fe16b88 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31774 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-03-07src/device/Kconfig: Include the discrete VGA OpROM at config UIMike Banon
Create the way of adding the discrete VGA OpROM at config UI (alternative to ./cbfstool ./cb.rom add -f vgabios_dgpu.bin -n pci1002,6663.rom -t optionrom ) DGPU options are accessible only if CONFIG_VGA_BIOS is enabled. Signed-off-by: Mike Banon <mikebdp2@gmail.com> Change-Id: I0a7bf0fe95c833cf3df0c7cb20fc27b6ab218c5a Reviewed-on: https://review.coreboot.org/c/coreboot/+/31449 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-03-07prog_loader: Associate TS_END_ROMSTAGE timestamp with postcar if existSubrata Banik
This patch adds timestamp for "end of romstage" with postcar if platform has selected postcar as dedicated stage. If postcar stage doesn't exist then "end of romstage" timestamp will get call while starting of ramstage as exist today. TEST=It's been observed that "end of romstage" timestamp doesn't appear in "cbmem -t" log when ramstage is not getting executed. As part of this fix "end of romstage" timestamp is showing in "cbmem -t" log on Intel platform where POSTCAR is a dedicated stage. Change-Id: I17fd89296354b66a5538f85737c79145232593d3 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31608 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-03-07arch/x86/postcar: Add separate timestamp for postcar stageSubrata Banik
This patch adds dedicated timestamp value for postcar stage. TEST=Able to see "start of postcar" and "end of postcar" timestamp while executing cbmem -t after booting to chrome console. > cbmem -t 951:returning from FspMemoryInit 20,485,324 (20,103,067) 4:end of romstage 20,559,235 (73,910) 100:start of postcar 20,560,266 (1,031) 101:end of postcar 20,570,038 (9,772) Change-Id: I084f66949667ad598f811d4233b4e639bc4c113e Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31762 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-03-07security/tpm: Fix TCPA log featurePhilipp Deppenwiese
Until now the TCPA log wasn't working correctly. * Refactor TCPA log code. * Add TCPA log dump fucntion. * Make TCPA log available in bootblock. * Fix TCPA log formatting. * Add x86 and Cavium memory for early log. Change-Id: Ic93133531b84318f48940d34bded48cbae739c44 Signed-off-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/29563 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-03-06arch/x86: Prepare GDT for x86_64Patrick Rudolph
Make GDT a separate table and don't reuse GDT descriptor as unused first field of GDT. Required for separate x86_64 GDT descriptor, pointing to the same GDT. Tested on qemu. Change-Id: I513329b67d49ade1055bc07cf7b93ff2e0131e0b Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31769 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-06nb/intel/sandybridge: Reserve CAR region with !NATIVE_RAMINITKyösti Mälkki
Fail builds if MRC blobs pool heap would get corrupted by CAR relocatable data from coreboot proper. Add runtime logging how much pool was required. Change-Id: Ibc771b592b35d77be81fce87769314fe6bb84c87 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31150 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-06device/pci_ops: Change ramstage PCI accessor signaturesKyösti Mälkki
This reduces parameter passing and visibility of parsing struct *dev to PCI bus:dev.fn. Change-Id: Ie4232ca1db9cffdf21ed133143acfb7517577736 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31750 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-03-04arch/io.h: Separate MMIO and PNP opsKyösti Mälkki
Change-Id: Ie32f1d43168c277be46cdbd7fbfa2445d9899689 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/31699 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-04device/pnp: Add header files for PNP opsKyösti Mälkki
Change-Id: Ifda495420cfb121ad32920bb9f1cbdeef41f6d3a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/31698 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-04device/mmio.h: Add include file for MMIO opsKyösti Mälkki
MMIO operations are arch-agnostic so the include path should not be arch/. Change-Id: I0fd70f5aeca02e98e96b980c3aca0819f5c44b98 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/31691 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-04arch/io.h: Drop unnecessary includeKyösti Mälkki
Change-Id: I91158452680586ac676ea11c8589062880a31f91 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/31692 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-04arch/io.h: Fix PCI and PNP simple typedefsKyösti Mälkki
Provide clean separation for PCI and PNP headers, followup will also move PNP outside <arch/io.h>. Change-Id: I85db254d50f18ea34a5e95bc517eac4085a5fafa Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/31690 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-03-04arch/x86/acpi: Remove obsolete acpi_gen_regaddr resv fieldElyes HAOUAS
Since ACPI v2.c, this field is access_size. Currently, coreboot is using ACPI v3,so we can drop '.resv' field. Change-Id: I7b3b930861669bb05cdc8e81f6502476a0568fe0 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/31701 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-03-03device/pci_ops: Drop parameter from pci_bus_default_ops()Kyösti Mälkki
A default is a build-time static value, fallback. Return value does not depend of input parameter. Change-Id: I43ae28f465fb46391519ec97a2a50891d458c46d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/31679 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-03device/pci_ops: Drop unused parameterKyösti Mälkki
Drop the bus parameter, we do not use it. It would still be possible to do per-bus selection by evaluating the bus number, but currently we do not have need for that either. Change-Id: I09e928b4677d9db2eee12730ba7b3fdd8837805c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/31678 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-03-03device/pci_ops: Avoid name collisionsKyösti Mälkki
Having different signatures for the PCI config accessors prevents them from having the same name in different stages. For now, work around this using __SIMPLE_DEVICE__. Change-Id: I20f56cfe3ac7dc4421e62a99ca91f39a857c0ccf Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/31677 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-03-03arch/x86/acpi: Clean up commentsElyes HAOUAS
As we are running ACPI v3.0, references to older than v3.0 are removed. Change-Id: I0cce0035ed2b952d59cc1a4a9e6017dae67ef6db Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/31689 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-03-01device/pci: Fix PCI accessor headersKyösti Mälkki
PCI config accessors are no longer indirectly included from <arch/io.h> use <device/pci_ops.h> instead. Change-Id: I2adf46430a33bc52ef69d1bf7dca4655fc8475bd Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/31675 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-03-01src/arch/x86/acpi.c: Update ACPI table's revision numbersElyes HAOUAS
Change-Id: I22020bd156536ee8f23a267d7c7b2d7af6c7cfeb Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/29579 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-by: Martin Roth <martinroth@google.com>
2019-03-01ACPI: Rename FADT model and set it to zeroElyes HAOUAS
INT_MODEL defined in ACPI 1.0 and renamed to reserved since V 2.0. The value for this field is zero but 1 is allowed to maintain compatibility with ACPI 1.0. So set this value to zero as we are using greater version than ACPI 1.0. Change-Id: I910ead4e5618c958a7989f4c309a3a4bb938e31a Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/29986 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: David Guckian Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-02-26ACPI: Fill asl_compiler_revision field left emptyElyes HAOUAS
Change-Id: I1075e872e5cb1990bd330b88bb03322ab9338e86 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/31607 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-02-26acpi: Sort the reported APIC-IDs in the MADT tableWerner Zeh
coreboot performs MP-Init in a parallel way. That leads to the fact that the order, in which the CPUs are woken up, can vary from boot to boot. The creation of the MADT table just parses the devicetree and takes the CPUs reported there as it is for creating the single local APIC entries. Therefore, the OS will see different order of CPUs. There are CPUs out there (like Apollo Lake for example) which have shared caches on core-level and if the order is random this can end up in assigning cores to different tasks or even OSes (in a virtual environment) which uses the same cache. This in turn will produce performance penalties across these distributed tasks/OSes. Though there is a way to discover the core- and cache-topology it will in the end be necessary to take the APIC-ID into account. To simplify it, one can achieve the same output by sorting the APIC-IDs in an ascending order. This will lead to the fact that CPUs that share a given cache will be reported right next to each other in the MADT. Change-Id: Ida74f9f00a4e2a03107a2124014403de60462735 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/31545 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-02-25ACPI: Enum only used ACPI tablesElyes HAOUAS
enum contained redundant names and wasn't exhaustive anyway. Change-Id: I4d74ff61c555c5953932efbd7edccfd3157cb5be Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/31592 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-02-23arch/x86/smbios.c: Remove duplicated 'processor_upgrade'Elyes HAOUAS
Change-Id: I3500a648631c91f3a0812c7e661440743ed6a1e1 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/31555 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-02-22arch/arm64: Add PCI config support in romstageKyösti Mälkki
Change-Id: I9cc3dc51764f24b986434080f480932dceb8d133 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/31307 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-02-22vboot: fix STARTS_IN_BOOTBLOCK/_ROMSTAGE logicJoel Kitching
Fix up the logic of when to include VBOOT2_WORK symbols on x86, which are only needed when VBOOT_STARTS_IN_BOOTBLOCK is enabled. Also correct the value of the __PRE_RAM__ macro in the case that VBOOT_STARTS_IN_ROMSTAGE is selected. In this case, DRAM is already up and verstage should not be considered pre-ram. BUG=b:124141368, b:124192753 TEST=Build locally for eve TEST=util/lint/checkpatch.pl -g origin/master..HEAD TEST=util/abuild/abuild -B -e -y -c 50 -p none -x TEST=make clean && make test-abuild BRANCH=none Change-Id: Ie51e8f93b99ab230f3caeede2a33ec8b443e3d7a Signed-off-by: Joel Kitching <kitching@google.com> Reviewed-on: https://review.coreboot.org/c/31541 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-02-22symbols.h: Add macro to define memlayout region symbolsJulius Werner
When <symbols.h> was first introduced, it only declared a handful of regions and we didn't expect that too many architectures and platforms would need to add their own later. However, our amount of platforms has greatly expanded since, and with them the need for more special memory regions. The amount of code duplication is starting to get unsightly, and platforms keep defining their own <soc/symbols.h> files that need this as well. This patch adds another macro to cut down the definition boilerplate. Unfortunately, macros cannot define other macros when they're called, so referring to region sizes as _name_size doesn't work anymore. This patch replaces the scheme with REGION_SIZE(name). Not touching the regions in the x86-specific <arch/symbols.h> yet since they don't follow the standard _region/_eregion naming scheme. They can be converted later if desired. Change-Id: I44727d77d1de75882c72a94f29bd7e2c27741dd8 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/31539 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-02-21ACPI: Correct asl_compiler_revision valueElyes HAOUAS
Change-Id: I91b54b43c8bb5cb17ff86a6d9afa95f265ee49df Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/31431 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-02-21SMBIOS: Fix bios versionElyes HAOUAS
Change-Id: I142f08ed3c2704b8fde6d176f23772f5d6b33e85 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/31437 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-02-20walkcbfs: Only compile on x86_32Patrick Rudolph
The current implementation was designed for x86_32, so don't attempt to compile it on x86_64 until it is fixed. Fixes compilation error on x86_64. Change-Id: Ibd87dc2979f6d45a988119c06c5f9e61b3e86171 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/c/31467 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-02-15SMBIOS: Update BIOS Information (Type 0) to version V3.2.0Elyes HAOUAS
Add Extended BIOS ROM Size field. Change-Id: Iec35c8c66210f0ddc07a2ca6f976a1f8fc53037d Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/31416 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-02-13riscv: Add initial support for 32bit boardsPhilipp Hug
* Adding separate targets for 32bit and 64bit qemu * Using the riscv64 toolchain for 32bit builds requires setting -m elf32lriscv * rv32/rv64 is currently configured with ARCH_RISCV_RV32/RV64 and not per stage. This should probably be changed later. TEST=Boots to "Payload not loaded." on 32bit qemu using the following commands: util/riscv/make-spike-elf.sh build/coreboot.rom build/coreboot.elf qemu-system-riscv32 -M virt -m 1024M -nographic -kernel build/coreboot.elf Change-Id: I35e59b459d1770df10b51fe9e77dcc474d7c75a0 Signed-off-by: Philipp Hug <philipp@hug.cx> Reviewed-on: https://review.coreboot.org/c/31253 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: ron minnich <rminnich@gmail.com>
2019-02-11device/pci_ops: Apply some symmetry in headersKyösti Mälkki
To make PCI driver side arch-agnostic, function declarations have to be in symmetrical header file locations. From the driver side, the correct file to include is now <device/pci_ops.h> Change-Id: I8076a4867fd7472beaae0a021dcf0d9c7c905871 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/31306 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-02-11device/pci_ops: Move common pci_mmio_cfg.hKyösti Mälkki
It is expected that method of accessing PCI configuration register space via memory-mapped region is arch-agnostic. Change-Id: Ide6baa00d611953aeb324be0d3561f464395c5eb Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/31305 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-02-11device/pci_ops: Move questionable pci_locate() variantsKyösti Mälkki
These are defined for __SIMPLE_DEVICE__ when PCI enumeration has not happened yet. These should not really try to probe devices other than those on bus 0. It's hard to track but there maybe cases of southbridge being located on bus 2 and available for configuration, so I rather leave the code unchanged. Just move these out of arch/io.h because they cause build failures if one attempts to include <arch/pci_ops.h> before <arch/io.h>. There are two direct copies for ROMCC bootblocks to avoid inlining them elsewhere. Change-Id: Ida2919a5d83fe5ea89284ffbd8ead382e4312524 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/31304 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-02-11device/pci: Always define PCI_DEV()Kyösti Mälkki
This has uses outside ARCH_x86 and/or __PRE_RAM__. Change-Id: I2eec674ec5ba4ffe03a20db0f73cf87e5e4b4d0d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/31302 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-02-10arch/x86: Drop stale commentKyösti Mälkki
Change-Id: I1ba6dfb502ff053ccf82d2acc5fefbbfe09d647b Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/31294 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-02-10arch/x86: Drop some ROMCC remainsKyösti Mälkki
Change-Id: I62da8d0461774db8256e82deae0d5fe075f3faed Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/31293 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-02-09riscv: Use correct argument in a1 when invoking payloadPhilipp Hug
Fix a bug introduced by: 820dcfceb3901dbb00bb90c876e374126ca14e20 riscv: Simplify payload handling Put fdt into a1 correctly. Change-Id: I0dea7b88fde9d9a7365cb366917747d8110b9159 Signed-off-by: Philipp Hug <philipp@hug.cx> Reviewed-on: https://review.coreboot.org/c/31287 Reviewed-by: ron minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-02-08x86/acpi: Use PM_TABLET where appropriateDuncan Laurie
Instead of having SYSTEM_TYPE_DETACHABLE and SYSTEM_TYPE_TABLET use PM_MOBILE have them use PM_TABLET instead. Change-Id: If0ce51e522d36420ecd5b51bdfec6cca11c00333 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/31277 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-02-05Kconfig: Add system type entries for common enclosuresDuncan Laurie
These are more common system types and in some cases it is important to know when a device is a convertible or a tablet or detachable instead of just a laptop. This change will select the appropriate SMBIOS enclosure type based on the selected system type. This is important for the Intel Virtual Button driver as it does a check on the SMBIOS enclosure type and only enables the tablet mode events if it is set to convertible: https://patchwork.kernel.org/patch/10236253/ Change-Id: I148ec2329a1dd38ad55c60ba277a514c66376fcc Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/31206 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-02-05bootmem: add new memory type for BL31Ting Shen
After CL:31122, we can finally define a memory type specific for BL31, to make sure BL31 is not loaded on other reserved area. Change-Id: Idbd9a7fe4b12af23de1519892936d8d88a000e2c Signed-off-by: Ting Shen <phoenixshen@google.com> Reviewed-on: https://review.coreboot.org/c/31123 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-02-05arch/x86/acpigen: wrap _PLD in a packageMatt Delco
The ACPI spec has an asl example for _PLD in the form: Name (_PLD, Package (0x01) { ToPLD (PLD_Revision = 0x2) }) When I ported this to acpigen and diffed the results I noticed that the binary blob was no longer provided within a package. The ACPI spec (section 6.1.8 in version 6.2) defines _PLD as "a variable-length Package containing a list of Buffers". This commit changes acpigen_write_pld to use a package (the one existing caller I found isn't wrapping the result in a package so it doesn't look like it was intended for the callers of acpigen_write_pld to be responsible for using a package. BUG=none BRANCH=none TEST=Verified that after this change a package is use and the result of acpigen matches what was used in the original asl. Change-Id: Ie2db63c976100109bfe976553e52565fb2d2d9df Signed-off-by: Matt Delco <delco@chromium.org> Reviewed-on: https://review.coreboot.org/c/31162 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-02-05acpi: device: avoid empty property list in acpi_dp_writeMatt Delco
If an acpi_dp table has children but no properties then acpi_dp_write() will write out a properties UUID and package that contains no properties. The existing function will avoid writing out a UUID and empty package when no children exist, but it seems to assume that properties will always be used. With this change properties are handled in a manner akin to children so that a UUID and package are only written if properties exist. BUG=none BRANCH=none TEST=Confirmed that prior to this change a UUID and empty package was present for a device that had children but no properties. Verified that after this change the UUID and empty package are no longer present but the child UUID and package are still present. Change-Id: I6f5597713a1e91ca26b409f36b3ff9eb90a010af Signed-off-by: Matt Delco <delco@chromium.org> Reviewed-on: https://review.coreboot.org/c/31161 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-02-05intel/quark: Fix COMMONLIB_STORAGE in CARKyösti Mälkki
The allocation is not required before romstage, so it can be just another CAR_GLOBAL instead of polluting the linker script. Change-Id: I0738a655f6cc924fbed92ea630f85406e3f58c0b Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/31191 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-02-02usbdebug: Use fixed size fieldKyösti Mälkki
The structure is placed inside CBMEM, one should use types with fixed size. Seems we prefer to prepare for 64-bit builds even for MMIO pointers. Change-Id: I60382664a53650b225abc1f77c87ed4e121d429e Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/31182 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-02-02usbdebug: Fix reserve in CARKyösti Mälkki
We need sizeof(struct ehci_dbg_info) of 88 but only reserved 64 bytes. If usbdebug_hw_init() was called late in romstage, for some builds it would corrupt CAR_GLOBALs like console_inited variable and stop logging anything. Also change pointer initialisation such that glob_dbg_info will hit garbage collection for PRE_RAM stages. Change-Id: Ib49fca781e55619179aa8888e2d859560e050876 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/31174 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-02-02riscv: Show hart id in trap handlerPhilipp Hug
Also show hart id in trap information for easier debugging. Change-Id: I20acf86e1af111600c158295ae03b2167838d127 Signed-off-by: Philipp Hug <philipp@hug.cx> Reviewed-on: https://review.coreboot.org/c/31201 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: ron minnich <rminnich@gmail.com>
2019-02-02riscv: Simplify payload handlingXiang Wang
1. Simplify payload code and convert it to C 2. Save the FDT pointer to HLS (hart-local storage). 3. Don't use mscratch to pass FDT pointer as it is used for exception handling. Change-Id: I32bf2a99e07a65358a7f19b899259f0816eb45e8 Signed-off-by: Xiang Wang <wxjstz@126.com> Signed-off-by: Philipp Hug <philipp@hug.cx> Reviewed-on: https://review.coreboot.org/c/31179 Reviewed-by: ron minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-30selfload: check target memory type in selfload_checkTing Shen
Currently, selflock_check() verifies that the binary is loaded in an usable RAM area. Extend its functionality so we can also check that BL31 is loaded in a manually reserved area, and fail early if the range is not protected. Change-Id: Iecdeedd9e8da67f73ac47d2a82e85b306469a626 Signed-off-by: Ting Shen <phoenixshen@google.com> Reviewed-on: https://review.coreboot.org/c/31122 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-01-28src: Don't use a #defines like Kconfig symbolsElyes HAOUAS
This is spotted using ./util/lint/kconfig_lint To work around the issue, rename the prefix from `CONFIG_` to `CONF_`. Change-Id: Ia31aed366bf768ab167ed5f8595bee8234aac46b Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/31049 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-01-27src: Fix the warning "type 'hex' are always defined"Elyes HAOUAS
This is spotted using "./util/lint/kconfig_lint" While at it, do the check in C and not the preprocessor. Change-Id: Icfda267936a23d9d14832116d67571f42f685906 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/31050 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-01-24riscv: ARCH_RISCV_RV{32,64} selects ARCH_RISCVRonald G. Minnich
ARCH_RISCV_RV{32,64} will now select ARCH_RISCV. Change-Id: Ia7a1a8f0bfab20e91b8429dd6dd3e9a4180a0a5b Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: https://review.coreboot.org/c/31042 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Hug <philipp@hug.cx>
2019-01-17riscv: create Kconfig architecture features for new partsRonald G. Minnich
RISCV parts can be created with any one of four CPU modes enabled, with or without PMP, and with either 32 or 64 bit XLEN. In anticipation of parts to come, create the Kconfig variables for these architecture attributes. Change-Id: I32ee51b2a469c7684a2f1b477bdac040e972e253 Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: https://review.coreboot.org/c/30348 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-16buildsystem: Promote rules.h to default includeKyösti Mälkki
Does not fix 3rdparty/, *.S or *.ld or yet. Change-Id: I66b48013dd89540b35ab219d2b64bc13f5f19cda Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/17656 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-01-14arch/x86: Enforce CPU stack alignmentKyösti Mälkki
When rmodule is loaded CPU stack alignment is only guaranteed to 4kiB. Implementation of cpu_info() requires that each CPU sees its stack aligned to CONFIG_STACK_SIZE. Add one spare CPU for the stack reserve, such that alignment can be enforced runtime. Change-Id: Ie04956c64df0dc7bb156002d3d4f2629f92b340e Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/26302 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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