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2016-01-19arch/x86: Indent using tabs not spacesMartin Roth
No functional changes - just whitespace fixes. Signed-off-by: Martin Roth <martinroth@google.com> Change-Id: I8ffa87240bcbd3d657ed9dc619b5e5bf9de734d7 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12853 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-01-18header files: Fix guard name comments to match guard namesMartin Roth
This just updates existing guard name comments on the header files to match the actual #define name. As a side effect, if there was no newline at the end of these files, one was added. Change-Id: Ia2cd8057f2b1ceb0fa1b946e85e0c16a327a04d7 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12900 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-01-18arch/riscv: Add missing license headersMartin Roth
Most of these files are original to coreboot and get the standard coreboot GPL header. encoding.h and atomic.h are from the riscv codebase and have their license. Change-Id: I32506b0ecf88be2f5794dc1e312a6cd9b2a271ad Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12906 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2016-01-18arch/x86/Makefile.inc: Update symbol check macroMartin Roth
This was breaking the build on OS X, but also wasn't working correctly under linux anymore either. It wouldn't print the illegal symbols when it failed. - Split the generation of the offenders file from the actual check for offending symbols and just send all output to /dev/null. - Rewrite the check for offending symbols in a way that works with OS X. Tested by adding a global variable to romstage and verifying the failure is shown correctly. Verified that it works correctly with no illegal variables. Change-Id: I5b3ac32448851884d78c3b3449508ffe014119ab Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/13018 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-01-14arch/x86: add missing license headersMartin Roth
These were mostly written as part of the coreboot project, so get the standard coreboot license header. memmove.c came from the linux kernel, so also gets the standard coreboot v2 license header, but gets the added attribution that it was derived from the linux kernel. Unlike many coreboot files, this file may not be re-licensed as GPL V3. Change-Id: I1fdc26b543e059f7a42d4b886f7222f4c74b959d Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12916 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-01-14arch/x86/include: add missing license headersMartin Roth
These were all written as part of the coreboot project, so get the standard coreboot license header. Change-Id: I51e1e504b3bc7be2a00c9356d8775b87f2a1db5a Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12912 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-01-13arch/arm64: add missing license headersMartin Roth
These were all written as part of the coreboot project, so get the standard coreboot license header. Change-Id: I4fccc8055755816be64e9e1a185f1e6fcb2b89ae Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12911 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-01-13arch/arm: add missing license headersMartin Roth
These were all written as part of the coreboot project, so get the standard coreboot license header. Change-Id: I74438e8032c84f4190ef49f306969f7157234001 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12910 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-01-07Correct some common spelling mistakesMartin Roth
- occured -> occurred - accomodate -> accommodate - existant -> existent - asssertion -> assertion - manangement -> management - cotroller -> controller Change-Id: Ibd6663752466d691fabbdc216ea05f2b58ac12d1 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12850 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-01-07cpu/amd/microcode: Introduce CBFS access spinlock to avoid IOMMU failureTimothy Pearson
When microcode updates are enabled, this fixes an issue identical to that described in GIT hash 7b22d84d: * drivers/pc80: Add optional spinlock for nvram CBFS access Change-Id: Ib7e8cb171f44833167053ca98a85cca23021dfba Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/12063 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-06Revert "x86: Align CBFS on top of ROM"Aaron Durbin
This reverts commit 65e33c08a9a88c52baaadaf515b9591856115a77. This was the wrong logic to fix the master header. Change-Id: I4688034831f09ac69abfd0660c76112deabd62ec Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/12824 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2015-12-31imgtec/pistachio: Add SOC_REGISTERS memory regionIonela Voinescu
When used with a U-boot payload it will need this region identity mapped also, so we're defining it in preparation for that functionality. Change-Id: I27cee5b58cb899433b52bd06df07b5f2105212af Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com> Reviewed-on: https://review.coreboot.org/12768 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-12-29x86: Align CBFS on top of ROMNico Huber
Since the introduction of the new (interim?) master header, coreboot searches the whole ROM for CBFS entries. Fix that by aligning it on top of the ROM. Change-Id: I080cd4b746169a36462a49baff5e114b1f6f224a Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/12810 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2015-12-29mips: add coherency argument to identity mappingIonela Voinescu
In order for a U-boot payload to work properly the soc_registers region (device registers) needs to be mapped as uncached. Therefore, add a coherency argument to the identity mapping funcion which will establish the type of mapping. Change-Id: I26fc546378acda4f4f8f4757fbc0adb03ac7db9f Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com> Reviewed-on: https://review.coreboot.org/12769 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-18drivers/pc80: Add optional spinlock for nvram CBFS accessTimothy Pearson
When enabling the IOMMU on certain systems dmesg is spammed with I/O page faults like the following: AMD-Vi: Event logged [IO_PAGE_FAULT device=00:14.0 domain=0x000a address=0x000000fdf9103300 flags=0x0030] Decoding the faulting address: 0x000000fdf9103300 fdf91x Hypertransport system management region 33 SysMgtCmd (System Management Command) = 0x33 3 Base Command Type = 0x3: STPCLK (Stop Clock request) 3 SMAF (System Management Action Field) = [3:1] = 0x1 1 Signal State Bit Map = [0] = 0x1 Therefore, the error appears to be triggered by an upstream C1E request. This was eventually traced to concurrent access to the SP5100's SPI Flash controller by multiple APs during startup. Calls to the nvram read functions get_option and read_option call CBFS functions, which in turn make near-simultaneous requests to the SPI Flash controller, thus placing the SP5100 in an invalid state. This limitation is not documented in any public AMD errata, and was only discovered through considerable debugging effort. Change-Id: I4e61b1ab767b1b7958ac7c1cf20eee41d2261bef Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/12061 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2015-12-16x86/smbios: Return index 0 for empty stringsBen Gardner
Section 6.1.3 (Text Strings) of the SMBIOS specification states: If a string field references no string, a null (0) is placed in that string field. Change smbios_add_string() to do that. Change-Id: I9c28cb89dcfe2c8ef2366c23ee6203e15b7c2513 Signed-off-by: Ben Gardner <gardner.ben@gmail.com> Reviewed-on: https://review.coreboot.org/12697 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-16build system/x86: depend on directories before touch /empty targetsAlexander Couzens
$(objgenerated)/empty would touch files before the directory is created on parallel builds. Thanks to reproducible-builds.org for hitting this bug. Change-Id: I7565e9fe130b4e9deaf1c7b9d568ff90b00dda52 Signed-off-by: Alexander Couzens <lynxis@fe80.eu> Reviewed-on: https://review.coreboot.org/12717 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-12-15x86 acpi: remove ALIGN_CURRENT macroAaron Durbin
The ALIGN_CURRENT macro relied on a local variable name as well as being defined in numerous compilation units. Replace those instances with an acpi_align_current() inline function. Change-Id: Iab453f2eda1addefad8a1c37d265f917bd803202 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/12707 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-12-15src/console: Add x86 romstage spinlock option and printk spinlock supportTimothy Pearson
This paves the way for AP printk spinlock on AMD platforms Change-Id: Ice42a0d3177736bf6e1bc601092e413601866f20 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/11958 Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2015-12-10lib: remove assets infrastructureAaron Durbin
Now that only CBFS access is supported for finding resources within the boot media the assets infrastructure can be removed. Remove it. BUG=chromium:445938 BRANCH=None TEST=Built and ran on glados. Change-Id: I383fd6579280cf9cfe5a18c2851baf74cad004e9 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/12690 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-10cbfs/vboot: remove firmware component supportAaron Durbin
The Chrome OS verified boot path supported multiple CBFS instances in the boot media as well as stand-alone assets sitting in each vboot RW slot. Remove the support for the stand-alone assets and always use CBFS accesses as the way to retrieve data. This is implemented by adding a cbfs_locator object which is queried for locating the current CBFS. Additionally, it is also signalled prior to when a program is about to be loaded by coreboot for the subsequent stage/payload. This provides the same opportunity as previous for vboot to hook in and perform its logic. BUG=chromium:445938 BRANCH=None TEST=Built and ran on glados. CQ-DEPEND=CL:307121,CL:31691,CL:31690 Change-Id: I6a3a15feb6edd355d6ec252c36b6f7885b383099 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/12689 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-06Remove #ifdef checks on Kconfig symbolsMartin Roth
In coreboot, bool, hex, and int type symbols are ALWAYS defined. Change-Id: I58a36b37075988bb5ff67ac692c7d93c145b0dbc Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12560 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-04arch/x86/bootblock_normal: Update to use fewer registersMartin Roth
- Move initialization of entry to later in main. - Make boot_mode an unsigned char - no need to use int. - Remove unnecessary variable filenames. - Only get and try to boot fallback once. Change-Id: I823092c60dd8c2de0a36ec7fdbba3e68f6b7567a Test: compiled. Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12574 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-03arch/arm64: introduce mmu to bootblock and romstageJimmy Huang
We need mmu interfaces in these two stages for, 1. bootblock: to support mmu initialization in bootblock 2. romstage: to be able to add dram range to mmu table BRANCH=none BUG=none TEST=build pass Change-Id: I56dea5f958a48b875579f546ba17a5dd6eaf159c Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: cf72736bda2233f8e0bdd7a8ca3245f1d941ee86 Original-Change-Id: I1e27c0a0a878f7bc0ff8712bee640ec3fd8dbb8b Original-Signed-off-by: Jimmy Huang <jimmy.huang@mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/292665 Original-Commit-Ready: Yidi Lin <yidi.lin@mediatek.com> Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/12585 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2015-12-03arch/arm64: add DMA_COHERENT region macros to memlayoutJimmy Huang
BRANCH=none BUG=none TEST=build pass Change-Id: Ia997ce97ad42234ab020af7bd007d57d7191ee86 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 604ac738e33fdfbaf093989ea13162c8506b9360 Original-Change-Id: I636a1a38d0f5af97926d4446f3edb91a359cce4c Original-Signed-off-by: Jimmy Huang <jimmy.huang@mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/292551 Original-Commit-Ready: Yidi Lin <yidi.lin@mediatek.com> Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/12584 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-02build system: Add more files through cbfs-files instead of manual rulesPatrick Georgi
verstage, romstage, and payload can be added through infrastructure now. Change-Id: Ib9e612ae35fb8c0230175f5b8bca1b129f366f4b Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/12549 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-02x86/smm: Initialize SMM on some CPUs one-by-oneDamien Zammit
We currently race in SMM init on Atom 230 (and potentially other CPUs). At least on the 230, this leads to a hang on RSM, likely because both hyperthreads mess around with SMBASE and other SMM state variables in parallel without coordination. The same behaviour occurs with Atom D5xx. Change it so first APs are spun up and sent to sleep, then BSP initializes SMM, then every CPU, one after another. Only do this when SERIALIZE_SMM_INITIALIZATION is set. Set the flag for Atom CPUs. Change-Id: I1ae864e37546298ea222e81349c27cf774ed251f Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Signed-off-by: Damien Zammit <damien@zamaudio.com> Reviewed-on: https://review.coreboot.org/6311 Tested-by: build bot (Jenkins) Tested-by: BSI firmware lab <coreboot-labor@bsi.bund.de> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-12-01build system: strip quotes from CONFIG_CBFS_PREFIX in a single locationPatrick Georgi
Instead of having to remember to strip the quotes everywhere so that string comparisons (of which there are a few) match up, do it right at the beginning. Fixes building the image with a .config where CONFIG_CBFS_PREFIX contains quotes. Change-Id: I4d63341cd9f0bc5e313883ef7b5ca6486190c124 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/12578 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
2015-11-24Unify OBJCOPY arguments throughout various x86 stagesStefan Reinauer
Instead of having to have an ifeq() all across the code base, use $(target-objcopy). And correct target-objcopy to a value that objcopy actually understands. Change-Id: Id5dea6420bee02a044dc488b5086d109e806d605 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/11090 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-11-23arch/x86/acpi: Add IVRS table generation routinesTimothy Pearson
Change-Id: Ia5d97d01dc9ddc45f81d998d126d592a915b4a75 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/12043 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-11-17arm64: tegra132: tegra210: Remove old arm64/stage_entry.SJulius Werner
This patch removes the old arm64/stage_entry.S code that was too specific to the Tegra SoC boot flow, and replaces it with code that hides the peculiarities of switching to a different CPU/arch in ramstage in the Tegra SoC directories. BRANCH=None BUG=None TEST=Built Ryu and Smaug. !!!UNTESTED!!! Change-Id: Ib3a0448b30ac9c7132581464573efd5e86e03698 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/12078 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-11-17rules.h: Add ENV_ macros to detect current architectureJulius Werner
This patch expands the existing ENV_<stage> macros in <rules.h> with a set of ENV_<arch> macros which can be used to detect which architecture the current compilation unit is built for. These are more consistent than compiler-defined macros (like '#ifdef __arm__') and will make it easier to write small, architecture-dependent differences in common code (where we currently often use IS_ENABLED(CONFIG_ARCH_...), which is technically incorrect in a world where every stage can run on a different architecture, and merely kinda happened to work out for now). Also remove a vestigal <arch/rules.h> from ARM64 which was no longer used, and genericise ARM subarchitecture Makefiles a little to make things like __COREBOOT_ARM_ARCH__ available from all file types (including .ld). BUG=None TEST=Compiled Falco, Blaze, Jerry and Smaug. Change-Id: Id51aeb290b5c215c653e42a51919d0838e28621f Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/12433 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
2015-11-16arm64: Implement generic stage transitions for non-Tegra SoCsJulius Werner
The existing arm64 architecture code has been developed for the Tegra132 and Tegra210 SoCs, which only start their ARM64 cores in ramstage. It interweaves the stage entry point with code that initializes a CPU (and should not be run again if that CPU already ran a previous stage). It also still contains some vestiges of SMP/secmon support (such as setting up stacks in the BSS instead of using the stage-peristent one from memlayout). This patch splits those functions apart and makes the code layout similar to how things work on ARM32. The default stage_entry() symbol is a no-op wrapper that just calls main() for the current stage, for the normal case where a stage ran on the same core as the last one. It can be overridden by SoC code to support special cases like Tegra. The CPU initialization code is split out into armv8/cpu.S (similar to what arm_init_caches() does for ARM32) and called by the default bootblock entry code. SoCs where a CPU starts up in a later stage can call the same code from a stage_entry() override instead. The Tegra132 and Tegra210 code is not touched by this patch to make it easier to review and validate. A follow-up patch will bring those SoCs in line with the model. BRANCH=None BUG=None TEST=Booted Oak with a single mmu_init()/mmu_enable(). Built Ryu and Smaug. Change-Id: I28302a6ace47e8ab7a736e089f64922cef1a2f93 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/12077 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-11-11cpu/amd: Add CC6 supportTimothy Pearson
This patch adds CC6 power save support to the AMD Family 15h support code. As CC6 is a complex power saving state that relies heavily on CPU, northbridge, and southbridge cooperation, this patch alters significant amounts of code throughout the tree simultaneously. Allowing the CPU to enter CC6 allows the second level of turbo boost to be reached, and also provides significant power savings when the system is idle due to the complete core shutdown. Change-Id: I44ce157cda97fb85f3e8f3d7262d4712b5410670 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/11979 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-11-11arm/arm64: Generalize bootblock C entry pointJulius Werner
When we first added ARM support to coreboot, it was clear that the bootblock would need to do vastly different tasks than on x86, so we moved its main logic under arch/. Now that we have several more architectures, it turns out (as with so many things lately) that x86 is really the odd one out, and all the others are trying to do pretty much the same thing. This has already caused maintenance issues as the ARM32 bootblock developed and less-mature architectures were left behind with old cruft. This patch tries to address that problem by centralizing that logic under lib/ for use by all architectures/SoCs that don't explicitly opt-out (with the slightly adapted existing BOOTBLOCK_CUSTOM option). This works great out of the box for ARM32 and ARM64. It could probably be easily applied to MIPS and RISCV as well, but I don't have any of those boards to test so I'll mark them as BOOTBLOCK_CUSTOM for now and leave that for later cleanup. BRANCH=None BUG=None TEST=Built Jerry and Falco, booted Oak. Change-Id: Ibbf727ad93651e388aef20e76f03f5567f9860cb Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/12076 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2015-11-11arm64: mmu: Make page table manipulation work across stagesJulius Werner
In order to have a proper runtime-modifyable page table API (e.g. to remap DRAM after it was intialized), we need to remove any external bookkeeping kept in global variables (which do not persist across stages) from the MMU code. This patch implements this in a similar way as it has recently been done for ARM32 (marking free table slots with a special sentinel value in the first PTE that cannot occur as part of a normal page table). Since this requires the page table buffer to be known at compile-time, we have to remove the option of passing it to mmu_init() at runtime (which I already kinda deprecated before). The existing Tegra chipsets that still used it are switched to instead define it in memlayout in a minimally invasive change. This might not be the best way to design this overall (I think we should probably just throw the tables into SRAM like on all other platforms), but I don't have a Tegra system to test so I'd rather keep this change low impact and leave the major redesign for later. Also inlined some single-use one-liner functions in mmu.c that I felt confused things more than they cleared up, and fixed an (apparently harmless?) issue with forgetting to mask out the XN page attribute bit when casting a table descriptor to a pointer. BRANCH=None BUG=None TEST=Compiled Ryu and Smaug. Booted Oak. Change-Id: Iad71f97f5ec4b1fc981dbc8ff1dc88d96c8ee55a Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/12075 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-11-11armv7: mmu: Make fine grained page tables work across stagesJulius Werner
Among its other restrictions (which are noted in a comment above the function prototype and stay in place), our makeshift fine-grained page table support for ARM32 has the undocumented feature that it relies on a global bookkeeping variable, causing all sorts of fun surprises when you try to use it from multiple stages during the same boot. This patch redesigns the bookkeeping to stay completely inline in the (persistent) TTB which should resolve the issue. (This had not been a problem on any of our platforms for now... I just noticed this because I was trying to solve the same issue on ARM64.) BRANCH=None BUG=None TEST=Booted veyron_jerry. Mapped a second fine-grained memory range from romstage, confirmed that it finds the next free spot and leaves the bootblock table in place. Change-Id: I325866828b4ff251142e1131ce78b571edcc9cf9 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/12074 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-11-07arm64: Remove cpu intialization through device-treeFurquan Shaikh
Since, SMP support is removed for ARM64, there is no need for CPU initialization to be performed via device-tree. Change-Id: I0534e6a93c7dc8659859eac926d17432d10243aa Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: http://review.coreboot.org/11913 Tested-by: build bot (Jenkins) Reviewed-by: Julius Werner <jwerner@chromium.org>
2015-11-07arm64: Remove SMP supportFurquan Shaikh
As ARM Trusted Firmware is the only first class citizen for booting arm64 multi-processor in coreboot remove SMP support. If SoCs want to bring up MP then ATF needs to be ported and integrated. Change-Id: Ife24d53eed9b7a5a5d8c69a64d7a20a55a4163db Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: http://review.coreboot.org/11909 Tested-by: build bot (Jenkins) Reviewed-by: Julius Werner <jwerner@chromium.org>
2015-11-07arm64: remove spin table supportAaron Durbin
As ARM Trusted Firmware is the only first class citizen for booting arm64 multi-processor in coreboot remove spintable support. If SoCs want to bring up MP then ATF needs to be ported and integrated. Change-Id: I1f38b8d8b0952eee50cc64440bfd010b1dd0bff4 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11908 Tested-by: build bot (Jenkins) Reviewed-by: Julius Werner <jwerner@chromium.org>
2015-11-07arm64: remove ARCH_ARM64_CORTEX_A57_POWER_DOWN_SUPPORTAaron Durbin
With the removal of secmon from coreboot there are no power down operations required. As such remove the A57 power down support. Change-Id: I8eebb0ecd87b5e8bb3eaac335d652689d7f57796 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11898 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-07arm64: remove secmonAaron Durbin
It's been decided to only support ARM Trusted Firmware for any EL3 monitor. That means any SoC that requires PSCI needs to add its support for ATF otherwise multi-processor bring up won't work. Change-Id: Ic931dbf5eff8765f4964374910123a197148f0ff Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11897 Tested-by: build bot (Jenkins) Reviewed-by: Julius Werner <jwerner@chromium.org>
2015-11-06AMD Bettong: Enable S4 feature for Windows 7zbao
PMIOxEE is for setting USB3 power rail. Set it to S0, otherwise going into hibernation can not be wake up. Change-Id: I692497bad24d745738d670897e725a568c1db114 Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/11373 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins)
2015-11-04ACPI: Add functions for DMAR I/O-APIC and HPET entriesNico Huber
Refactor acpi_create_dmar_drhd_ds_pci() and add similar functions for I/O-APICs and MSI capable HPETs. We violate the spec [1] here, which talks about 16-bit source-ids spread over start_bus and path entries. Intel actually uses bus/dev/fn identification for those devices too, and so do we. [1] Intel Virtualization Technology for Directed I/O Architecture Specification Document-Number: D51397 Change-Id: I0fce075961762610d44b5552b71e010511871fc2 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: http://review.coreboot.org/12192 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@google.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-11-04ACPI: Make DMAR flags settableNico Huber
Add a parameter to acpi_create_dmar() for the flags field and define flags given by the spec [1]. [1] Intel Virtualization Technology for Directed I/O Architecture Specification Document-Number: D51397 Change-Id: I03ae32f13bb0061bd3b9bef607db175d9b0bc5e1 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: http://review.coreboot.org/12191 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@google.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-11-03arch/x86/bootblock_normal: Fix failure to buildTimothy Pearson
Fix a function call in the normal path using the original function name and arguments in code that was changed in commit 3bfd7cc6 (drivers/pc80: Rework normal / fallback selector code) This commit reworked most of the fallback / normal code, however the normal code paths were not fully tested by Jenkins, so this was missed. Change-Id: Ied66334977272a13b7a7307ff4d9f34eb22040aa Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/12315 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins)
2015-10-31tree: drop last paragraph of GPL copyright headerPatrick Georgi
It encourages users from writing to the FSF without giving an address. Linux also prefers to drop that and their checkpatch.pl (that we imported) looks out for that. This is the result of util/scripts/no-fsf-addresses.sh with no further editing. Change-Id: Ie96faea295fe001911d77dbc51e9a6789558fbd6 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/11888 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-10-31arch/x86: avoid race condition on build.hPatrick Georgi
Change-Id: I15375ac1247b7cc8d80d910a767c7f3e67eb8739 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/11904 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nico Huber <nico.h@gmx.de>
2015-10-30wakeup: Switch back to 32bit mode firstStefan Reinauer
On x86_64 we need to leave long mode before we can switch to 16bit mode. Oh joy! When's my 64bit resume pointer coming? Why didn't this get caught earlier? Seems the Asrock E350M2 didn't do Suspend/Resume? Yes, I know it's Intel syntax. Will be converted to AT&T syntax as soon as the whole thing actually works.. 8) Change-Id: Ic51869cf67d842041f8842cd9964d72a024c335f Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/11106 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-10-17armv7: Word-sized/half-word-sized memory operations for 32/16 bit read/writePaul Kocialkowski
Some registers only allow word-sized or half-word-sized operations and will cause a data fault when accessed with byte-sized operations. However, the compiler may or may not break such an operation into smaller (byte-sized) chunks. Thus, we need to reliably perform word-sized operations for 32 bit read/write and half-word-sized operations for 16 bit read/write. This is particularly the case on the rk3288 SRAM registers, where the watchdog tombstone is stored. Moving to GCC 5.2.0 introduced a change of strategy in the compiler, where a 32 bit read would be broken into byte-sized chunks, which caused a data fault when accessing the watchdog tombstone register. The definitions for byte-sized memory operations are also adapted to stay consistent with the rest. Change-Id: I1fb3fc139e0a813acf9d70f14386a9603c9f9ede Signed-off-by: Paul Kocialkowski <contact@paulk.fr> Reviewed-on: http://review.coreboot.org/11698 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-10-16arch/x86/smbios: Add Crucial DIMM manufacturer IDTimothy Pearson
Change-Id: I975142351c0c033f9dc44670dcf819d296896921 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/11934 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins)
2015-10-16arch/x86/boot/smbios: Add SPD IDs for Kingston and CorsairTimothy Pearson
Change-Id: I6a32b69d3b75d7d086dc7f8ea1e195473399f406 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/11933 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins)
2015-10-14x86: add standalone verstage supportAaron Durbin
To support x86 verstage one needs a working buffer for vboot. That buffer resides in the cache-as-ram region which persists across verstage and romstage. The current assumption is that verstage brings cache-as-ram up and romstage tears cache-as-ram down. The timestamp, cbmem console, and the vboot work buffer are persistent through in both romstage and verstage. The vboot work buffer as well as the cbmem console are permanently destroyed once cache-as-ram is torn down. The timestamp region is migrated. When verstage is enabled the assumption is that _start is the romstage entry point. It's currently expected that the chipset provides the entry point to romstage when verstage is employed. Also, the car_var_*() APIs use direct access when in verstage since its expected verstage does not tear down cache-as-ram. Lastly, supporting files were added to verstage-y such that an x86 verstage will build and link. BUG=chrome-os-partner:44827 BRANCH=None TEST=Built and booted glados using separate verstage. Change-Id: I097aa0b92f3bb95275205a3fd8b21362c67b97aa Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11822 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-10-11vboot: remove remnants of VBOOT_STUBAaron Durbin
For vboot1 there was an rmodule that was loaded and ran to do the firmware verification. That's no longer used so remove the last vestiges of VBOOT_STUB. BUG=chrome-os-partner:44827 BRANCH=None TEST=Built glados. Change-Id: I6b41544874bef4d84d0f548640114285cad3474e Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11817 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-10-08arch/x86/bootblock: Do not include non-code files in bootblock.SAlexandru Gagniuc
Since we now have more freedom in the bootblock linking step it no longer makes sense to use a monolithic bootblock.S. Code segments must still be included as the order in bootblock.S determines code flow. However, non-code flow related assembly stubs don't need to be directly included in bootblock.S Change-Id: I08e86e92d82bd2138194ed42652f268b0764aa54 Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/11792 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-10-08arch/x86: Link walkcbfs.S instead on including it in bootblock.SAlexandru Gagniuc
The code flow doesn't fall through to walkcbfs, as it does in the rest of bootblock.S. Instead, walkcbfs is called (albeit via a jmp). The linker cannot know this when walkcbfs.S is included directly. When we use a CAR bootblock, we lose several hundred bytes because walkcbfs is not garbage-collected, yet it isn't used. This problem is solved by assembling walkcbfs.S separately, and linking it. Change-Id: Ib3a976db09b9ff270b7677cb4f9db80b0b025e22 Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/11785 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-10-08arch/x86/bootblock: Link in object files selected with bootblock-yAlexandru Gagniuc
As part of preparing for systems with non-memory-mapped media, we want to be able to call into C code. This change allows us to link C code directly into the bootblock. The steps of going from bootblock main() to CAR setup to C code will be implemented in subsequent patches. Note that a few files selected with bootblock-y will now be compiled for the bootblock as well, but since we enabled garbage collection, they will not be included in the final binary. Change-Id: I5ca6dcaf176f5469c6a3bb925859399123493bc6 Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/11783 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2015-10-08arch/x86/Makefile.inc: Simplify rule for bootblock.debugAlexandru Gagniuc
The only difference between the ifeq/else/endif guarded rules is the linker flags specific to x86. Add those flags to LDFLAGS_bootblock, and only use one rule for bootblock.debug. Change-Id: I986a93e0418f05fb273512d7efe0573052493332 Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/11782 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-10-07x86/bootblock: Use LDFLAGS_bootblock to enable garbage collectionAlexandru Gagniuc
The x86 bootblock linking is a mess. The bootblock is treated in a very special manner, and never received the update to link-time garbage collection. On newer x86 platforms, the boot media is no longer memory-mapped. That means we need to do a lot more setup in the bootblock. ROMCC is unsuitable for this task, and walkcbfs only works on memory-mapped CBFS. We need to revise the x86 bootflow for this new case. The approach this patch series takes is to perform CAR setup in the bootblock, and load the following stage (either romstage or verstage) from the boot media. This approach is not new, but has been done on our ARM ports for years. Since we will be adding .c files to the bootblock, it is prudent to use link-time garbage collection. This is also consistent to how we do things on other architectures. Unification FTW! Change-Id: I16b78456df56e0053984a9aca9367e2542adfdc9 Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/11781 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-09-30x86: prepare cache-as-ram to allow multiple stagesAaron Durbin
In order to do a verification of romstage on x86 one needs to run verstage which verifies romstage (and the memory init code). However, x86 doesn't have SRAM like every other modern SoC so managing the cache-as-ram region is especially critical. First move all of the "shared" objects to the beginning of the .car.data section. This change then ensures that each stage using car.ld to link has the same consistent view of the addresses of these fixed-sized objects in cache-as-ram. The CAR_GLOBALs can be unique per stage. However, these variables are expected to have a value of zero at the start of each stage. In order to allow a stage to provide those semantics outside of the initial cache-as-arm setup routine add _car_global_start and _car_global_end symbols. Those symbols can be used to clear the CAR_GLOBALs for that stage. Note that the timestamp region can't be moved out similarly to the pre-ram cbmem console because the object storage of the timestamp cache is used *after* cache-as-ram is torn down to indicate if the cache should be used or not. Therefore, that timestamp needs to migrated to ram. A logic change in src/lib/timestamp.c could alleviate this requirement, but that task wasn't tackled in this patch. BUG=chrome-os-partner:44827 BRANCH=None TEST=Built and booted glados. Change-Id: I15e9f6b0c632ee5a2369da0709535d6cb0d94f61 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11740 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-09-30x86: provide common macro for linking early stagesAaron Durbin
In order to support verstage on x86 one needs to link verstage like romstage since it needs all the cache-as-ram goodies. Therefore, provide a macro that one can invoke that provides the necessary recipes for linking that particular stage in such an environment. BUG=chrome-os-partner:44827 BRANCH=None TEST=Built and booted glados. Change-Id: I12f4872df09fff6715829de68fc374e230350c2e Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11739 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-09-29Makefile: Replace the way to test if a string is emptyzbao
The output of command below, # i386-elf-nm build/cbfs/fallback/romstage_null.offenders | \ grep -q "" ; echo $? has different result on MacOS, OS X Mavericks, which outputs 0. On linux, it outputs 1. I assume it is misleading to search an empty string in a empty string. Change it to testing if the string is empty. Change-Id: Ie4b8fe1fb26df092e2985937251a49feadc61eb0 Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/11600 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-09-28arm64: mmu: Prevent CPU prefetch instructions from device memoryJimmy Huang
Set XN bit of block upper attribute to device memory in mmu. CPU may speculatively prefetch instructions from device memory, but the IO subsystem of some implementation may not support this operation. Set this attribute to device memory mmu entries can prevent CPU from prefetching device memory. BRANCH=none BUG=none TEST=build and booted to kernel on oak-rev3 with dcm enabled. Change-Id: I52ac7d7c84220624aaf6a48d64b9110d7afeb293 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 7b01a4157cb046a5e75ea7625060a602e7a63c3c Original-Change-Id: Id535e990a23b6c89123b5a4e64d7ed21eebed607 Original-Signed-off-by: Jimmy Huang <jimmy.huang@mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/302301 Original-Commit-Ready: Yidi Lin <yidi.lin@mediatek.com> Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/11722 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-09-23RISCV: modify arch_prog_run to handle payloads correctly.Ronald G. Minnich
Unlike the other stages, the payload requires virtual memory to be set up and also a privelege level change. Change-Id: Ibbe2a55f7719d917f121a53a17c6d90e6b2ab3d1 Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: http://review.coreboot.org/11699 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2015-09-22coreboot: introduce commonlibAaron Durbin
Instead of reaching into src/include and re-writing code allow for cleaner code sharing within coreboot and its utilities. The additional thing needed at this point is for the utilities to provide a printk() declaration within a <console/console.h> file. That way code which uses printk() can than be mapped properly to verbosity of utility parameters. Change-Id: I9e46a279569733336bc0a018aed96bc924c07cdd Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11592 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-09-16riscv-virtual-memory: move page tables into virtual address spaceThaminda Edirisooriya
If we use a linux payload/any payload that wants to manage virtual memory, and the payload is a supervisor (thus requiring virtual addressing before being started), we need to make sure that the page table is mapped into the virtual address space. Move the start address of the tables so the payload can manage virtual memory. Change-Id: I1d99e46f38a38a163fb1c7c517b1abca80cde0dc Signed-off-by: Thaminda Edirisooriya <thaminda@google.com> Reviewed-on: http://review.coreboot.org/11621 Tested-by: build bot (Jenkins)
2015-09-16riscv-memlayout: fix existing memlayout issues, add sbi interfaceThaminda Edirisooriya
Existing memlayout code placed sections in overlapping areas, and would overwrite the payload if it was large enough. Update memlayout.ld in src/mainboard/emulation/spike-riscv to represent the spike emulator, and add sbi interface which now has room into src/arch/riscv/bootblock.S. Add utility code to qemu-riscv, but emulator itself has yet to be updated to new ISA and as such should not be used. Update Makefile to include all the files necessary for sbi interface. Clean up unused include in src/arch/riscv/include/atomic.h and whitespace in src/mainboard/emulation/spike-riscv/memlayout.ld Fixed whitespace issues in spike_util.c Change-Id: Id97fe75e45ac1361005bec6d421756ee3f98a508 Signed-off-by: Thaminda Edirisooriya <thaminda@google.com> Reviewed-on: http://review.coreboot.org/11370 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-09-16x86: remove double link step for romstageAaron Durbin
Now that cbfstool supports XIP for romstage utilize it. This removes the double link steps with the cbfstool locate and add-stage sandwich. BUG=chrome-os-partner:44827 BRANCH=None TEST=Built and booted on glados. Change-Id: I1ec555f523a94dd4b15fe8186cbe530520c622c0 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11670 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-09-15riscv-trap-handling: Add functionality, prevent stack corruptionThaminda Edirisooriya
Trap handling code was bugged in that it loaded in the wrong stack pointer, overwriting the space the processor uses to talk to its host for doing device requests. Fix this issue, as well as add support for handling misaligned loads the same way we handle misaligned stores. Change-Id: I68ba3a114b7167b3212bb0bed181a7595f0b97d8 Signed-off-by: Thaminda Edirisooriya <thaminda@google.com> Reviewed-on: http://review.coreboot.org/11620 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-09-10riscv-trap-handling: Add implementation for trap calls in riscvThaminda Edirisooriya
RISCV requires the bios/bootloader to set up an interface by which it can get information about memory, talk to host devices, etc. Put implementation for spike in src/mainboard/emulation/spike-riscv/spike_util.c, and src/arch/riscv/trap_handler.c Change-Id: Ie1d5f361595e48fa6cc1fac25485ad623ecdc717 Signed-off-by: Thaminda Edirisooriya <thaminda@google.com> Reviewed-on: http://review.coreboot.org/11368 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-09-10riscv-virtual-memory: Add virtual memory setupThaminda Edirisooriya
Execution in supervisor level code in RISCV requires early setup of virtual memory. Add initialization calls in src/arch/riscv/virtual_memory.c to implement the required page table setup, and helper functions to use when jumping to the payload correctly in riscv. Change-Id: I46e080e0ee8dc13277d567dcd4bf0f61a4507b76 Signed-off-by: Thaminda Edirisooriya <thaminda@google.com> Reviewed-on: http://review.coreboot.org/11369 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-09-09x86: link ramstage the same way regardless of RELOCATABLE_RAMSTAGEAaron Durbin
Previously there were 2 paths in linking ramstage. One was used for RELOCATABLE_RAMSTAGE while the other was fixed location. Now that rmodtool can handle multiple secitons for a single proram segment there's no need for linking ramstage using lib/rmodule.ld. That also means true rmodules don't have symbols required for ramstage purposes so fix memlayout.h. Lastly add default rules for creating rmod files from the known file names and locations. BUG=chrome-os-partner:44827 BRANCH=None TEST=Built rambi. Inspected ramstage.debug as well as rmodules created during the build. Change-Id: I98d249036c27cb4847512ab8bca5ea7b02ce04bd Signed-off-by: Aaron Durbin <adubin@chromium.org> Reviewed-on: http://review.coreboot.org/11524 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-09-09linking: add and use LDFLAGS_commonAaron Durbin
Add an LDFLAGS_common variable and use that for each stage during linking within all the architectures. All the architectures support gc-sections, and as such they should be linking in the same way. BUG=chrome-os-partner:44827 BRANCH=None TEST=Built rambi and analyzed the relocatable ramstage. Change-Id: I41fbded54055455889b297b9e8738db4dda0aad0 Signed-off-by: Aaron Durbin <adubin@chromium.org> Reviewed-on: http://review.coreboot.org/11522 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Julius Werner <jwerner@chromium.org>
2015-09-09x86: link romstage and ramstage with 1 fileAaron Durbin
To reduce file clutter merge romstage.ld and ramstage.ld into a single memlayout.ld. The naming is consistent with other architectures and chipsets for their linker script names. The cache-as-ram linking rules are put into a separate file such that other rules can be applied for future verstage support. BUG=chrome-os-partner:44827 BRANCH=None TEST=Built rambi and dmp/vortex86ex. Change-Id: I1e8982a6a28027566ddd42a71b7e24e2397e68d2 Signed-off-by: Aaron Durbin <adubin@chromium.org> Reviewed-on: http://review.coreboot.org/11521 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-09-09rmodule: use program.ld for linkingAaron Durbin
Bring rmodule linking into the common linking method. The __rmodule_entry symbol was removed while using a more common _start symbol. The rmodtool will honor the entry point found within the ELF header. Add ENV_RMODULE so that one can distinguish the environment when generating linker scripts for rmodules. Lastly, directly use program.ld for the rmodule.ld linker script. BUG=chrome-os-partner:44827 BRANCH=None TEST=Built rambi and analyzed the relocatable ramstage, sipi_vector, and smm rmodules. Change-Id: Iaa499eb229d8171272add9ee6d27cff75e7534ac Signed-off-by: Aaron Durbin <adubin@chromium.org> Reviewed-on: http://review.coreboot.org/11517 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-09-09x86: link romstage like the other architecturesAaron Durbin
All the other architectures are using the memlayout for linking romstage. Use that same method on x86 as well for consistency. BUG=chrome-os-partner:44827 BRANCH=None TEST=Built a myriad of boards. Analyzed readelf output. Change-Id: I016666c4b01410df112e588c2949e3fc64540c2e Signed-off-by: Aaron Durbin <adubin@chromium.org> Reviewed-on: http://review.coreboot.org/11510 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-09-09x86: link ramstage like the other architecturesAaron Durbin
All the other architectures are using the memlayout for linking ramstage. The last piece to align x86 is to use arch/header.ld and the macros within memlayout.h to automaticaly generate the necessary linker script. BUG=chrome-os-partner:44827 BRANCH=None TEST=Built a myriad of boards. Analyzed readelf output. Change-Id: I012c9b88c178b43bf6a6dde0bab821e066728139 Signed-off-by: Aaron Durbin <adubin@chromium.org> Reviewed-on: http://review.coreboot.org/11508 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-09-09linking: lay the groundwork for a unified linking approachAaron Durbin
Though coreboot started as x86 only, the current approach to x86 linking is out of the norm with respect to other architectures. To start alleviating that the way ramstage is linked is partially unified. A new file, program.ld, was added to provide a common way to link stages by deferring to per-stage architectural overrides. The previous ramstage.ld is no longer required. Note that this change doesn't handle RELOCATABLE_RAMSTAGE because that is handled by rmodule.ld. Future convergence can be achieved, but for the time being that's being left out. BUG=chrome-os-partner:44827 BRANCH=None TEST=Built a myriad of boards. Change-Id: I5d689bfa7e0e9aff3a148178515ef241b5f70661 Signed-off-by: Aaron Durbin <adubin@chromium.org> Reviewed-on: http://review.coreboot.org/11507 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Julius Werner <jwerner@chromium.org>
2015-09-09x86: provide minimum alignment for romstageAaron Durbin
The current way the XIP address of romstage is calculated is by doing a 'cbfstool locate' using a bin file of romstage linked at address 0. That address is then used for re-linking romstage at the address spit out by cbfstool. Currently, the linker actually sets minimum alignment on the text sections as 32 bytes, but it doesn't actually honor that value. Instead, provide a minimum alignment for romstage so as not to fight the linker. BUG=chrome-os-partner:44827 BRANCH=None TEST=Built asus/kfsn4-dre. Confirmed ROMSTAGE_BASE == gdtptr. Change-Id: Id6ec65d257df9ede78c720b0d7d4b56acfbb3f15 Signed-off-by: Aaron Durbin <adubin@chromium.org> Reviewed-on: http://review.coreboot.org/11588 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-09-09x86: remove unused sections from romstage.ldAaron Durbin
Now that the only source of ELF sections for romstage are from directly included .inc files or ROMCC generated inc files the subsection globs can be removed. i.e. Remove .rom.data.* and .rom.text.* listings. Lastly, put the .rom.data section directly after the .rom.text. They are by definition read-only and they are generated from the same place. BUG=chrome-os-partner:44827 BRANCH=None TEST=Spot checked !ROMCC and ROMCC boards. Confirmed only .rom.text .rom.data sections exist. Change-Id: Id17cf95c943103de006c5f3f21a625838ab49929 Signed-off-by: Aaron Durbin <adubin@chromium.org> Reviewed-on: http://review.coreboot.org/11505 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-09-09x86: add romstage.S to bind program flow and orderingAaron Durbin
The build system was previously determining the flow of the romstage code by the order of files added to the crt0s make variable. Those files were then concatenated together, and the resulting file was added to the build dependencies for romstage proper. Now romstage.S is added that can be built using the default object file rules. The generated romstage.inc is pulled in by way of an #include in the newly added romstage.S. BUG=chrome-os-partner:44827 BRANCH=None TEST=Built vortex, rambi, and some asus boards. compared readelf -e output. Change-Id: Ib1168f9541eaf96651c52d03dc0f60e2489a77bd Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11504 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-09-09x86: don't create MAINBOARDDIR/romstage.inc for !ROMCC boardsAaron Durbin
Previously, the x86 romstage build process was unconditionally creating a romstage.inc and adding it to crt0s. This step is inherently not necessary in the !ROMCC case becaue the romstage.inc was created by the compiler outputting assembler. That means MAINBOARDDIR/romstage.c is truly a C environment that requires some sort of assembler stub to call into (cache_as_ram.inc from the chipset dirs). Therefore, remove this processing. The result is that MAINBOARDDIR/romstage.c can use the normal build steps in creating an object and linking. The layout of romstage.elf will change but that's only from a symbol perspective. BUG=chrome-os-partner:44827 BRANCH=None TEST=Built multitude of boards. Compared readelf -e output. Change-Id: I9b8079caaaa55e3ae20d3db4c9b8be04cdc41ab7 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11503 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-09-09x86: bootblock: remove linking and program flow from build systemAaron Durbin
The build system was previously determining the flow and linking scripts bootblock code by the order of files added to the bootblock_inc bootblock-y variables.Those files were then concatenated together and built by a myriad of make rules. Now bootblock.S and bootblock.ld is added so that bootblock can be built and linked using the default build rules. CHIPSET_BOOTBLOCK_INCLUDE is introduced in order to allow the chipset code to place include files in the path of the bootblock program -- a replacement for the chipset_bootblock_inc make variable. BUG=chrome-os-partner:44827 BRANCH=None TEST=Built vortex, rambi, and some asus boards. Change-Id: Ida4571cbe6eed65e77ade98b8d9ad056353c53f9 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11495 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-09-07Drop "See file CREDITS..." commentStefan Reinauer
coreboot has no CREDITS file. Change-Id: Iaa4686979ba1385b00ad1dbb6ea91e58f5014384 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/11514 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-09-05symbols: add '_' to pci_drivers and cpu_drivers symbolsAaron Durbin
In order to prepare for more unification of the linker scripts prefix pci_drivers, epci_drivers, cpu_drivers, and ecpu_drivers with an underscore. BUG=chrome-os-partner:44827 BRANCH=None TEST=Built different boards includes ones w/ and w/o relocatable ramstage. Change-Id: I8918b38db3b754332e8d8506b424f3c6b3e06af8 Signed-off-by: Aaron Durbin <adubin@chromium.org> Reviewed-on: http://review.coreboot.org/11506 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-09-04x86: remove cpu_incs as romstage Make variableAaron Durbin
When building up which files to include in romstage there were both 'cpu_incs' and 'cpu_incs-y' which were used to generate crt0.S. Remove the former to settle on cpu_incs-y as the way to be included. BUG=chrome-os-partner:44827 BRANCH=None TEST=Built rambi. No include file changes. Change-Id: I8dc0631f8253c21c670f2f02928225ed5b869ce6 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11494 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-08-31timestamp: add tick frequency to exported tableAaron Durbin
Add the timestamp tick frequency within the timestamp table so the cbmem utility doesn't try to figure it out on its own. Those paths still exist for x86 systems which don't provide tsc_freq_mhz(). All other non-x86 systems use the monotonic timer which has a 1us granularity or 1MHz. One of the main reasons is that Linux is reporting /sys/devices/system/cpu/cpu0/cpufreq/cpuinfo_max_freq as the true turbo frequency on turbo enables machines. This change also fixes the p-state values honored in cpufreq for turbo machines in that turbo p-pstates were reported as 100MHz greater than nominal. BUG=chrome-os-partner:44669 BRANCH=firmware-strago-7287.B TEST=Built and booted on glados. Confirmed table frequency honored. Change-Id: I763fe2d9a7b01d0ef5556e5abff36032062f5801 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11470 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-08-31armv7/arm64: remove timestamp.cAaron Durbin
The src/lib/timestamp.c already has an implementation using timer_monotonic_get() for timestamp_get(). Use that instead of duplicating the logic. BUG=chrome-os-partner:44669 BRANCH=None TEST=None Change-Id: If17be86143f217445bd64d67ceee4355fa482d39 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11468 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-08-28arm64: xcompile: Add support for A53 erratum 843419Julius Werner
This patch adds support to enable a linker workaround to a hardware erratum on some early Cortex-A53 revisions. Since the linker option was added very recently, we use xcompile to test whether the toolchain supports it first. It is also guarded by a Kconfig since only a few ARM64 SoCs will need this and it incurs a performance penalty. BRANCH=none BUG=none TEST=Turned it on or off for Smaug and confirmed that it (dis)appeared in verbose make output accordingly. Change-Id: I01c9642d3cf489134645f0db6f79f1c788ddb00d Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Original-Commit-Id: 57128785760c4dfa32d6e6d764756443a9323cb7 Original-Change-Id: Ia5dd124f484e38460d75fb864304e7e8b18d16b7 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/294745 Original-Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/11403 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2015-08-28arm64: Fix 'verstage-objs: command not found' errorYidi Lin
Fix following compilation error. LINK cbfs/fallback/verstage.debug /bin/sh: verstage-objs: command not found /usr/x86_64-pc-linux-gnu/aarch64-cros-linux-gnu/binutils-bin/2.24/ld.bfd.real: warning: cannot find entry symbol stage_entry; defaulting to 00000000000d7000 BRANCH=chromeos-2015.07 BUG=none TEST=emerge-oak coreboot Change-Id: I30e4c43625b2d1d076f24e8c2639ce951839661b Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Original-Commit-Id: 2a8936cdf34d315f580819df682335b2998f044f Original-Change-Id: I9afd57a5a868a348dff2c66cad0a8a09cdb2e911 Original-Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/292557 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/11402 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-08-28arm64: declare do_dcsw_op as functionJimmy Huang
do_dcsw_op is coded as a label, it's possible that linker will place do_dcsw_op on unaligned address. To avoid this situation, we declare do_dcsw_op as a function. Also explicitly set the 2nd argument of ENTRY_WITH_ALIGN(name, bits) to 2. do_dcsw_op: cbz x3, exit c103d: b40003e3 cbz x3, c10b9 <exit> mov x10, xzr c1041: aa1f03ea mov x10, xzr adr x14, dcsw_loop_table // compute inner loop address BRANCH=none BUG=none TEST=build and check do_dcsw_op in elf file Change-Id: Ieb5f4188d6126ac9f6ddb0bfcc67452f79de94ad Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Original-Commit-Id: 4ee26b76089fab82cf4fb9b21c9f15b29e57b453 Original-Change-Id: Id331e8ecab7ea8782e97c10b13e8810955747a51 Original-Signed-off-by: Jimmy Huang <jimmy.huang@mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/293660 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Original-Commit-Queue: Yidi Lin <yidi.lin@mediatek.com> Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com> Reviewed-on: http://review.coreboot.org/11395 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-08-26riscv-trap-handling: Add preliminary trap handling for riscvThaminda Edirisooriya
RISCV requires a trap handler at the machine stage to deal with misaligned loads/stores, as well as to deal with calls that a linux payload will make in its setup. Put required assembly for jumping into and out of a trap here to be set up by the bootblock in a later commit. Change-Id: Ibf6b18e477aaa1c415a31dbeffa50a2470a7ab2e Signed-off-by: Thaminda Edirisooriya <thaminda@google.com> Reviewed-on: http://review.coreboot.org/11367 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins)
2015-08-25x86: Get rid of empty loadable segment warningMartin Roth
When the check for global symbols in romstage happens, if everything is good, a warning appears, telling us that the segment is empty. While the empty segment is good, the warning is distracting: "BFD: build/cbfs/fallback/romstage_null.debug: warning: Empty loadable segment detected, is this intentional ?" This change hides that particular warning, but shouldn't hide any other output from objcopy. Change-Id: If22489280712d02a61c3ee5e0cb2a53db87d6082 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: http://review.coreboot.org/11302 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins)
2015-08-14acpi: 64bit fixesStefan Reinauer
Change-Id: I5d0c95af7d35115b5ac4141489caceef4ee1c8bb Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/11088 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-08-13x86: parameterize asl_template for CBFS inclusionAaron Durbin
The asl_template previously unconditionally included dsdt.aml. However, COMPILE_IN_DSDT=y results in the dsdt.aml being linked directly into ramstage. Thus the information is duplicated. The inclusion of this file unconditionally throws some errors as certain assets need to be included in CBFS. However, as there isn't fine-grained ordering control in how files are added fixed resource requirements for other assets collide result in failure to build. To remedy both things, provide a 2nd argument to asl_template which defaults to 'y' for CBFS addition. In the COMPILE_IN_DSDT=y case pass 'n' so that dsdt.aml is no longer added. BUG=chrome-os-partner:43419 BRANCH=None TEST=For glados: Built with COMPILE_IN_DSDT=y. dsdt.aml not included. Built with COMPILE_IN_DSDT=n. dsdt.aml was included. Original-Change-Id: I4767e5be2915c1732251fe415017f30314c5efc9 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/289840 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Change-Id: Id1828627ba0a034eb05b2fe23be76e19f3040444 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11166 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins)
2015-08-13amd: raminit sysinfo offset fixAaron Durbin
The sysinfo object within the k8 ram init is used to communicate progess/status from all the nodes in the system. However, the code was assuming where the sysinfo object lived in cache-as-ram. The layout of cache-as-ram is dynamic so one needs to do the lookup of the correct address at runtime. The way the amd code is compiled by #include'ing .c files makes the solution a little more complex in that some cache-as-ram support code needed to be refactored. Change-Id: I6500fa7b005dc082c4c0b3382ee2c3a138d9ac31 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/10961 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-08-09riscv-spike: support for Spike emulation of riscvThaminda Edirisooriya
Spike support: QEMU RISCV is broken, and the maintainers at Berkeley are working on it, but at the moment spike is the only way to test on riscv. Add support for spike console output for debugging. Privileged ISA: Update to privileged ISA in RISCV (machine, supervisor, hypervisor, user modes) broke exisitng RISCV asm, and bootblock.S was updated to match the new spec. Clean old assembly [pg: things build with gcc 4.9 now, but don't expect them to work. Hardcoding register names into the assembler language may not be the smartest idea of the RISCV folks.] Change-Id: Ie2c109d3c26712c207512f74f28ce1a925e6e181 Signed-off-by: Thaminda Edirisooriya <thaminda@google.com> Reviewed-on: http://review.coreboot.org/11078 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-08-09acpi: Align FACS to 64 bytesPatrick Georgi
The spec states (5.2.10): "The BIOS aligns the FACS on a 64-byte boundary anywhere within the system's memory address space." Change-Id: Ie9415e505525dbdd418028d4954018c829921a18 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Found-by: fwts 15.08 Reviewed-on: http://review.coreboot.org/11141 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-08-04x86: Make sure boot device is mapped below 4GStefan Reinauer
On x86-64 the current way of calculating the base address of the boot device (SPI flash) gets an unwanted sign extension, making it live somewhere at the end of 64bit address space. Enforce rom_base to be at the upper end of the 4G address space. Change-Id: Ia81e82094d3c51f6c10e02b4b0df2f3e1519d39e Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/11121 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2015-07-29arm, arm64, mips: Add rough static stack size checks with -Wstack-usageJulius Werner
We've seen an increasing need to reduce stack sizes more and more for space reasons, and it's always guesswork because no one has a good idea how little is too litte. We now have boards with 3K and 2K stacks, and old pieces of common code often allocate large temporary buffers that would lead to very dangerous and hard to detect bugs when someone eventually tries to use them on one of those. This patch tries improve this situation at least a bit by declaring 2K as the minimum stack size all of coreboot code should work with. It checks all function frames with -Wstack-usage=1536 to make sure we don't allocate more than 1.5K in a single buffer. This is of course not a perfect test, but it should catch the most common situation of declaring a single, large buffer in some close-to-leaf function (with the assumption that 0.5K is hopefully enough for all the "normal" functions above that). Change one example where we were a bit overzealous and put a 1K buffer into BSS back to stack allocation, since it actually conforms to this new assumption and frees up another kilobyte of that highly sought-after verstage space. Not touching x86 with any of this since it's lack of __PRE_RAM__ BSS often requires it to allocate way more on the stack than would usually be considered sane. BRANCH=veyron BUG=None TEST=Compiled Cosmos, Daisy, Falco, Blaze, Pit, Storm, Urara and Pinky, made sure they still build as well as before and don't show any stack usage warnings. Change-Id: Idc53d33bd8487bbef49d3ecd751914b0308006ec Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 8e5931066575e256dfc2295c3dab7f0e1b65417f Original-Change-Id: I30bd9c2c77e0e0623df89b9e5bb43ed29506be98 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/236978 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9729 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>