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2019-10-20src: Remove unused 'include <string.h>'Elyes HAOUAS
Change-Id: I2a94c3b6282e9915fd2b8136b124740c8a7b774c Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36082 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-10-08arch/x86: Don't allow separate verstage to boot from romcc bootblockArthur Heymans
CONFIG_VBOOT_SEPARATE_VERSTAGE has a dependency on C_ENVIRONMENT_BOOTBLOCK so Kconfig already guards against this. Change-Id: I8f963a27f9023fd4c6ebc418059d57e00e4dfb4c Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35824 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-04arch/x86/acpi: Add SSDT for QEMUPatrick Rudolph
Add a SSDT on qemu and place BOOT0000 inside it to allow testing the google firmware kernel module in qemu. Tested on Qemu Q35. Change-Id: Ibd1b2c2f4fc3db9ae8f338b0d53b2d00ea2c4190 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35382 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HIMANSHU SAHDEV <sahdev.himan@gmail.com> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2019-10-01cpu/intel/common: Move intel_ht_sibling() to common folderPatrick Rudolph
Make intel_ht_sibling() available on all platforms. Will be used in MP init to only write "Core" MSRs from one thread on HyperThreading enabled platforms, to prevent race conditions and resulting #GP if MSRs are written twice or are already locked. Change-Id: I5d000b34ba4c6536dc866fbaf106b78e905e3e35 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35619 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-09-30arch/x86: Fix __ROMCC__ automatic prerequisitiesKyösti Mälkki
While the list of prerequisities is not created with romcc, we need to simulate it since different set of header files will is used. Change-Id: Ib799c872b5280e2035126f9660e04e51acc4b1a8 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35601 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-28cpu,device/: Remove some __SIMPLE_DEVICE__ and __ROMCC__ useKyösti Mälkki
Change-Id: I62d7450c8e83eec7bf4ad5d0709269a132fd0499 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35649 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-09-28arch/arm,mips: Use generic PCI MMCONFKyösti Mälkki
We need the stub header file. If PCI was implemented, assume generic MMIO mapped configuration space would work here. Change-Id: Ia731e5c5a6725fe22ab8b0398cafa1127ed90891 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35648 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-09-26arch/: Replace __BOOTBLOCK__ with ENV_BOOTBLOCKKyösti Mälkki
Change-Id: I294a3fd7be57b505cd209f7c2718a05770786c51 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35599 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-09-14arch/x86: Replace some __PRE_RAM__ useKyösti Mälkki
Change-Id: I4d8db430f8cd0bf0f161fc5cef052f153e59e2bc Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35390 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-14arch/x86: Remove acpi_fail_wakeup() and cbmem_fail_resume()Kyösti Mälkki
Unused since commit d46b8d5. Change-Id: If0f1e0381dd7698f842dc1288ff222a4d5d4783c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35389 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-14arm64: Uprev Arm TF and adjust to BL31 parameter changesJulius Werner
This patch uprevs the Arm Trusted Firmware submodule to the new upstream master (commit 42cdeb930). Arm Trusted Firmware unified a bunch of stuff related to BL31 handoff parameters across platforms which involved changing a few names around. This patch syncs coreboot back up with that. They also made header changes that now allow us to directly include all the headers we need (in a safer and cleaner way than before), so we can get rid of some structure definitions that were duplicated. Since the version of entry point info parameters we have been using has been deprecated in Trusted Firmware, this patch switches to the new version 2 parameter format. NOTE: This may or may not stop Cavium from booting with the current pinned Trusted Firmware blob. Cavium maintainers are still evaluating whether to fix that later or drop the platform entirely. Tested on GOOGLE_KEVIN (rk3399). Change-Id: I0ed32bce5585ce191736f0ff2e5a94a9d2b2cc28 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34676 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2019-09-13timestamps: Remove TIMESTAMP_CACHE_IN_BSSKyösti Mälkki
This was implemented for LATE_CBMEM_INIT support which has already been deprecated. Change-Id: I39225ba675bc3389e051e15b400a905431969715 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35375 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-13arch/x86/bootblock_crt0.S: Leverage eax in protected mode entryHimanshu Sahdev aka CunningLearner
Leverage already used eax register in bootblock_protected_mode_entry. Avoid another register ebx just for preserving eax value as it is not needed and is not used at all after moving the value into mm0. Allow EBX to be preserved for other usage. Change-Id: Ia668b78f2f97cf026692f1fe63ff8a382a162474 Signed-off-by: Himanshu Sahdev <himanshusah@hcl.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35292 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-11arch/x86: Cache the TSEG region at the top of ramSubrata Banik
This patch adds new API for enabling caching for the TSEG region and setting up required MTRR for next stage. BUG=b:140008206 TEST=Build and boot CML-Hatch. Change-Id: I59432c02e04af1b931d77de3f6652b0327ca82bb Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34995 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-09-11arch/x86: Restrict use of _car_global[start|end]Kyösti Mälkki
Restrict the use of symbol names _car_global_[start|end] to be used exclusively with CAR_GLOBAL_MIGRATION=y. They just alias the start and end of .bss section in CAR. Change-Id: I36c858a4f181516d4c61f9fd1d5005c7d2c06057 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35034 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2019-09-11arch/x86: Drop _car_relocatable_data symbolsKyösti Mälkki
These have become aliases to _car_global_[start|end]. Change-Id: Ibdcaaafdc0e4c6df4a795474903768230d41680d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35033 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2019-09-11arch/x86: Move ehci_dbg_info outside _car_relocatable_dataKyösti Mälkki
As code already used CBMEM hooks to switch from CAR to CBMEM it was never necessary to have the structure declared inside _car_relocatable_data. Switch to use car_[get|set]_ptr is mostly for consistency, but should also enable use of usbdebug with FSP1.0 romstage. Change-Id: I636251085d84e52a71a1d5d27d795bb94a07422d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35288 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-09-11timestamps: Improve collection for ENV_ROMSTAGE_OR_BEFOREKyösti Mälkki
Keep track of the active timestamp table location using a CAR_GLOBAL variable. Done this way, the entire table can be located outside _car_relocatable_data and we only switch the pointer to CBMEM and copy the data before CAR gets torn down. Fix comments about requirements of timestamp_init() usage. Remove timestamp_cache from postcar and ramstage, as CBMEM is available early on. Change-Id: I87370f62db23318069b6fd56ba0d1171d619cb8a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35032 Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-10AUTHORS: Move src/arch/x86 copyrights into AUTHORS fileMartin Roth
As discussed on the mailing list and voted upon, the coreboot project is going to move the majority of copyrights out of the headers and into an AUTHORS file. This will happen a bit at a time, as we'll be unifying license headers at the same time. Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: Ifd4329905847d9dd06de67b9a443c8ee50c0e7a7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/35177 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-09-09arch/x86: Refactor CAR_GLOBAL quirk for FSP1.0Kyösti Mälkki
These platforms return to romstage from FSP only after already having torn CAR down. A copy of the entire CAR region is available and discoverable via HOB. Previously, CBMEM console detected on-the-fly that CAR migration had happened and relocated cbmem_console_p accoringlin with car_sync_var(). However, if the CAR_GLOBAL pointing to another object inside CAR is a relative offset instead, we have a more generic solution that can be used with timestamps code as well. Change-Id: Ica877b47e68d56189e9d998b5630019d4328a419 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35140 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-06superio/common: Add ssdtgen for generic SuperIOsPatrick Rudolph
Add a generic SuperIO ACPI generator, dropping the need to include additional code in DSDT for SuperIO. It generates a device HID based on the decoded I/O range. Tested on Supermicro X11SSH-TF using AST2400. The SSDT contains no errors and all devices are present. Possible TODOs: * Add "enter config" and "exit config" bytes * Generate support methods to enter and exit config mode * Generate support methods to query, change or disable current resource settings on specific LDNs Change-Id: I2716ae0580d68e5d4fcc484cb1648a2cdc1f4ca0 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33033 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-09-02soc/intel/common/timer: Make TSC frequency calculation dynamicallySubrata Banik
tsc_freq_mhz() had a static table of Intel CPU families and crystal clock, but it is possible to calculate the crystal clock speed dynamically, and this is preferred over hardcoded table. On SKL/KBL/CML CPUID.15h.ecx = nominal core crystal clock = 0 Hz hence we had to use static table to calculate crystal clock. Recommendation is to make use of CPUID.16h where crystal clock frequency was not reported by CPUID.15h to calculate the crystal clock. BUG=b:139798422, b:129839774 TEST=Able to build and boot KBL/CML/ICL. Change-Id: If660a4b8d12e54b39252bce62bcc0ffcc967f5da Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35148 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: V Sowmya <v.sowmya@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-02arch/ppc64: move misc.c to qemu-power8 as timer.cMarty E. Plummer
Its entirely no-op and is getting in the way of real hardware timers for power9/talos ii. Change-Id: I2d21d4ac3d1a7d3f099ed6ec4faf10079b1ee1d1 Signed-off-by: Marty E. Plummer <hanetzer@startmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35082 Reviewed-by: Timothy Pearson <tpearson@raptorengineering.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-31arch/x86: Remove WB attribute from 0..CACHE_TMP_RAMTOPKyösti Mälkki
Platforms using postcar are with RELOCATABLE_RAMSTAGE=y. They don't benefit from having low-memory set as writeback-cacheable. This also fixes regression from CB:34893 that caused some random hangs with more recent intel SoCs in ramstage. BUG=b:140250314 Change-Id: Ia66910a6c85286f5c05823b87d48edc7e4ad9541 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35161 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-08-30arm64: Rename arm_tf.c/h to bl31.c/hJulius Werner
This patch renames arm_tf.c and arm_tf.h to bl31.c and bl31.h, respectively. That name is closer to the terminology used in most functions related to Trusted Firmware, and it removes the annoying auto-completion clash between arm64/arm_tf.c and arm64/armv8. Change-Id: I2741e2bce9d079b1025f82ecb3bb78a02fe39ed5 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34677 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2019-08-29arch/arm64: Make ARM64 stages select ARCH_ARM64Arthur Heymans
Also don't define the default as this result in spurious lines in the .config. The only difference in config.h is on boards with the Nvidia tegra210 SOC that now select ARCH_ARM64, because its ramstage runs in that mode. The resulting binary is identical however. Change-Id: Iaa9cd902281e51f823717f6ea4c72e5736fefb31 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31315 Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-29arch/arm: Make ARM stages select ARCH_ARMArthur Heymans
This removes the need to select ARCH_ARM in SOC Kconfig Also don't define the default as this result in spurious lines in the .config. Change-Id: I1ed4a71599641db606510e5304b9f0acf9b7eb88 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31313 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-29arch/x86: Fix clearing .bss sectionKyösti Mälkki
Using stosl clears 4 bytes at a time. Change-Id: Ie54fcfcb7e5a2a5a88d988476aa69b2a163e919c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35139 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2019-08-29arch/x86: remove weak car_stage_entry() symbolAaron Durbin
Many (if not all) platforms have moved to using consistent boot flow constructs where a weak car_stage_entry() is no longer necessary to avoid the complexity of handling the numerous and different boot flow combinations. The weak symbol is just causing issues so remove it. Change-Id: I7e7897c0609aac8eef96a08bb789374b2403956d Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35135 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-28arch/x86/postcar: unexpose postcar_commit_mtrrs() symbolAaron Durbin
postcar_commit_mtrrs() isn't used outside the postcar_loader compilation unit. Make it static to reduce API surface area. Additionally the return value was not being utilized. Modify the return type to be void to align with the current usage. Change-Id: If07f34467941d00de731489867e485cfff80ea63 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35130 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-08-28AUTHORS: Move src/arch/ppc64 copyrights into AUTHORS fileMartin Roth
As discussed on the mailing list and voted upon, the coreboot project is going to move the majority of copyrights out of the headers and into an AUTHORS file. This will happen a bit at a time, as we'll be unifying license headers at the same time. Additional changes in this patch: - Move descriptions below the license header Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: I51d5b1f01ff47ed752761116e3f32cb9e168584f Reviewed-on: https://review.coreboot.org/c/coreboot/+/34637 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-27AUTHORS: Move src/arch/mips copyrights into AUTHORS fileMartin Roth
As discussed on the mailing list and voted upon, the coreboot project is going to move the majority of copyrights out of the headers and into an AUTHORS file. This will happen a bit at a time, as we'll be unifying license headers at the same time. Additional changes in this patch: - Remove comments saying that a file is based on another file from the coreboot project. Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: If61689db67c58f0d66ab96ca749bfcd589935ce2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/34607 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-26x86: Introduce RESET_VECTOR_IN_RAM optionMartin Roth
Create a new Kconfig symbol that allows an x86 device to begin execution when its reset vector is in DRAM and not at the traditional 0xfffffff0. The implementation will follow later, this is just to setup various ENV_xxx definitions correctly for the build environment. Change-Id: I098ecf8bf200550db1e15f178f7661c1ac516dc5 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35004 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-08-26arch/x86: Simplify <arch/early_variables.h>Kyösti Mälkki
This enables the use of .bss section for ENV_BOOTBLOCK and ENV_VERSTAGE even with CAR_GLOBAL_MIGRATION=y. In practice, boards with CAR_GLOBAL_MIGRATION=y currently build with romcc-bootblock so they will not be using .bss. Change-Id: Ie9dc14f3e528d3e4f48304f4d7de50df448a8af6 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35016 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-08-26soc/intel: Use common romstage codeKyösti Mälkki
This provides stack guards with checking and common entry into postcar. The code in cpu/intel/car/romstage.c is candidate for becoming architectural so function prototype is moved to <arch/romstage.h>. Change-Id: I4c5a9789e7cf3f7f49a4a33e21dac894320a9639 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34893 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-26arch/non-x86: Use ENV_ROMSTAGE_OR_BEFOREKyösti Mälkki
Change-Id: I9dbf0fc14516f766fd164c7308906456f2865e89 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34982 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-26Move and rename ARCH_STAGE_HAS_xxx_SECTION rulesKyösti Mälkki
Currently only x86 requires special handling here, for simplicity avoid introducing <arch/rules.h> and deal with this directly in <rules.h>. For consistency prefixes are changed from ARCH_ to ENV_. Change-Id: I95a56dbad3482202f6cc03043589bebfb13c39af Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35014 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-08-26AUTHORS: Move src/arch/arm64 copyrights into AUTHORS fileMartin Roth
As discussed on the mailing list and voted upon, the coreboot project is going to move the majority of copyrights out of the headers and into an AUTHORS file. This will happen a bit at a time, as we'll be unifying license headers at the same time. Additional changes in this patch: - Make sure files say that they're part of the coreboot project - Move descriptions below the license header Note that the file include/arch/acpi.h is a fantastic example of why moving to the authors file is needed. Excluding the guard statements, it has 8 lines of copyrights for 3 function declarations. Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: I334baab2b4311eb1bd9ce3f67f49a68e8b73630c Reviewed-on: https://review.coreboot.org/c/coreboot/+/34606 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-26AUTHORS: Move src/arch/arm copyrights into AUTHORS fileMartin Roth
As discussed on the mailing list and voted upon, the coreboot project is going to move the majority of copyrights out of the headers and into an AUTHORS file. This will happen a bit at a time, as we'll be unifying license headers at the same time. Additional changes in this patch: - Make sure files say that they're part of the coreboot project - Move descriptions below the license header - Fix some spacing Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: Id5f26a73f0df366651c076a94975bce1fb321b70 Reviewed-on: https://review.coreboot.org/c/coreboot/+/34605 Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-26lib: ramdetect: Register exception handlers for ARMv8Asami Doi
Register exception handlers to avoid a Synchronous External Abort that is raised when you try to access a non-memory address on ARMv8. An exception handler can jump over the faulting instruction. This is the feature only for QEMU/AArch64. Signed-off-by: Asami Doi <d0iasm.pub@gmail.com> Change-Id: I09a306ca307ba4027d9758c3debc2e7c844c66b8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/34774 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2019-08-23arch/x86/acpi: Add acpi_device_hidPatrick Rudolph
Allow a driver to return device specific _HID, which will be consumed by acpigen in order to generate proper SSDTs. Change-Id: Ibb79eb00c008a3c3cdc12ad2a48b88a055a9216f Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35006 Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-22ACPI S3: Depend on RELOCATABLE_RAMSTAGEKyösti Mälkki
With RELOCATABLE_RAMSTAGE, S3 resume path only uses memory that is reserved from OS. So there is no need for low memory backup and recovery. Change-Id: If7f83711685ac445abf4cd1aa6b66c3391e0e554 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/26834 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-08-22ACPI S3: Drop ACPI_HUGE_LOWMEM_BACKUPKyösti Mälkki
ACPI S3 resume path can only modify low memory where the non-relocatable ramstage resides, there is no need to maintain a bigger backup copy. Change-Id: Ifae41b51b359010ec02269c674936a87bd15623b Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/15476 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-08-22arch/x86: Add <arch/romstage.h>Kyösti Mälkki
Start with moving all postcar_frame related function declarations here from <arch/cpu.h>. Change-Id: I9aeef07f9009e44cc08927c85fe1862edf5c70dc Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34911 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-21AMD fam10: Remove HAVE_ACPI_RESUME supportKyösti Mälkki
Change-Id: I62bbba8cfe515b3cae413582ff8d062a20e6741b Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/15474 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-08-20src: Remove variable length arraysJacob Garber
Variable length arrays were a feature added in C99 that allows the length of an array to be determined at runtime. Eg. int sum(size_t n) { int arr[n]; ... } This adds a small amount of runtime overhead, but is also very dangerous, since it allows use of an unlimited amount of stack memory, potentially leading to stack overflow. This is only worsened in coreboot, which often has very little stack space to begin with. Citing concerns like this, all instances of VLA's were recently removed from the Linux kernel. In the immortal words of Linus Torvalds [0], AND USING VLA'S IS ACTIVELY STUPID! It generates much more code, and much _slower_ code (and more fragile code), than just using a fixed key size would have done. [...] Anyway, some of these are definitely easy to just fix, and using VLA's is actively bad not just for security worries, but simply because VLA's are a really horribly bad idea in general in the kernel. This patch follows suit and zaps all VLA's in coreboot. Some of the existing VLA's are accidental ones, and all but one can be replaced with small fixed-size buffers. The single tricky exception is in the SPI controller interface, which will require a rewrite of old drivers to remove [1]. [0] https://lkml.org/lkml/2018/3/7/621 [1] https://ticket.coreboot.org/issues/217 Change-Id: I7d9d1ddadbf1cee5f695165bbe3f0effb7bd32b9 Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33821 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-08-20arch/non-x86: Remove use of __PRE_RAM__Kyösti Mälkki
Change-Id: Id8918f40572497b068509b5d5a490de0435ad50b Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34921 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-08-15arch/x86: Add postcar_frame_common_mtrrs()Kyösti Mälkki
As most platforms will share the subset of enabling both low RAM WB and high ROM WP MTRRs, provide them with a single function. Add possibility for the platform to skip these if required. Change-Id: Id1f8b7682035e654231f6133a42909a36e3e15a1 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34809 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-13cpu/x86: Move some SMM function declarationsKyösti Mälkki
Change-Id: I9a4e57f8fd032f2824eab0e5b59d635710e3e24b Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34822 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-08-11arch/x86: Flip option NO_CAR_GLOBAL_MIGRATIONKyösti Mälkki
It is easier to track CAR_GLOBAL_MIGRATION which is the approach to be deprecated with the next release. This change enforces new policy; POSTCAR_STAGE=y is not allowed together with CAR_GLOBAL_MIGRATION=y. Change-Id: I0dbad6a14e68bf566ac0f151dc8ea259e5ae2250 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34804 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-08-08arch/riscv: Enable FIT supportJonathan Neuschäfer
Tested on qemu-riscv. Depends on OpenSBI integration and proper memory detection in qemu. Boots into Linux until initrd should be loaded. Tested on SiFive/unleashed: Boots into Linux until earlycon terminates. Change-Id: I5ebc6cc2cc9e328f36d70fba13555386bb8c29d6 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/30292 Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-06arch/x86/acpi.c: Change TPM2 ACPI Table to support CRBChristian Walter
Change the TPM2 ACPI Table to support CRB Interface when selected. Change-Id: Ide3af348fd4676f2d04e1d0b9ad83f9124e09dcc Signed-off-by: Christian Walter <christian.walter@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34333 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2019-08-03smbios: Make SMBIOS type 3 enclosure type settable at runtimeMathew King
smbios.h had already declared smbios_mainboard_enclosure_type so this change defines it. It can be overridden in a mainboard so the enclosure type can be set at runtime. We have a mainboard that will be used in different enclosures and we are planning on using a single BIOS image for all of the enclosures so it will need to be set dynamically based on sku. BUG=b:138745917 TEST=Built arcada firmware and verified via dmidecode that enclosure type is correctly set to "Convertible", then temporarily added a smbios_mainboard_enclosure_type to arcadas board file returning 0x20 and verified with dmidecode that the enclosure type is "Detachable" Change-Id: Iba6e582640989f5cb7e6613813e7b033760a977c Signed-off-by: Mathew King <mathewk@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34646 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-08-03riscv: add support for OpenSBIXiang Wang
Call OpenSBI in M-Mode and use it to set up SBI and to lockdown the platform. It will also jump to the specified payload when done. This behaviour is similar to BL31 on aarch31. The payload is 41KiB in size on qemu. Tested on qemu-riscv: Required to boot a kernel as OpenSBI's instruction emulation feature is required on that virtual machine. Tested on SiFive/unleashed: The earlycon is working. No console after regular serial driver should take over, which might be related to kernel config. Change-Id: I2a178595bd2aa2e1f114cbc69e8eadd46955b54d Signed-off-by: Xiang Wang <merle@hardenedlinux.org> Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32394 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2019-08-02src/arch/x86/acpi: Constify struct device instancesAamir Bohra
Constify the struct device arguments in below APIs: > acpi_device_name > acpi_device_path_fill > acpi_device_path > acpi_write_dbg2_pci_uart > acpi_device_scope > acpi_device_path_join The APIs do not seem to modify the argument and are using device argument as reference to device only. Change-Id: Ic2ce045f17efa288eb41503795723d0ad5ec78bd Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34625 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-28riscv: Remove unused headersPatrick Rudolph
Change-Id: I4cd03e043e1bc2795b98d6ec2f88efa5b50d872b Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34141 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-07-26arch/ppc64: Make PPC64 stages select ARCH_PPC64Arthur Heymans
Also don't define the default as this result in spurious lines in the .config. This also cleans up an unused Kconfig file. In the generated config.h CPU_QEMU_POWER8 is gone as expected and ARCH_RAMSTAGE_PPC64 moves a few lines, but the value stays the same. Change-Id: I70b64e49e1ce07b8f30d9bbc493272bdfb3bb0bf Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31314 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-07-17lib: Remove the BOOTBLOCK_CUSTOM compile guardAsami Doi
This CL allows that everyone can use main() in lib/bootblock.c even if you select CONFIG_BOOTBLOCK_CUSTOM. I also rename main functions used in some soc/ to avoid the collision with the main function defined at lib/bootblock.c. Change-Id: I0575c9d1ce9dea9facfcc86760dff4deee9c1e29 Signed-off-by: Asami Doi <d0iasm.pub@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34250 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-13cpu/x86: Move smm_lock() prototypeKyösti Mälkki
The function implementations are in local platform scopes. Change-Id: I7a3025398b15fe6d2c5a13cdb65f3e62a49c0bc6 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34151 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-12arch, include, soc: Use common stdint.hJacob Garber
There are only minimal differences between the architecture specific stdint.h implementations, so let's tidy them up and merge them together into a single file. In particular, - Use 'unsigned long' for uintptr_t. This was already the case for x86 and riscv, while arm and mips used 'unsigned int', and arm64 and ppc64 used 'unsigned long long'. This change allows using a single integer type for uintptr_t across all architectures, and brings it into consistency with the rest of the code base, which generally uses 'unsigned long' for memory addresses anyway. This change required fixing several assumptions about integer types in the arm code. - Use _Bool as the boolean type. This is a specialized boolean type that was introduced in C99, and is preferrable over hacking booleans using integers. romcc sadly does not support _Bool, so for that we stick with the old uint8_t. - Drop the least and fast integer types. They aren't used anywhere in the code base and are an unnecessary maintenance burden. Using the standard fixed width types is essentially always better anyway. - Drop the UINT64_C() macro. It also isn't used anywhere and doesn't provide anything that a (uint64_t) cast doesn't. - Implement the rest of the MIN and MAX numerical limits. - Use static assertions to check that the integer widths are correct. Change-Id: I6b52f37793151041b7bdee9ec3708bfad69617b2 Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34075 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-07-12device/pci: Replace use of dev_find_slot() for IRQsKyösti Mälkki
Change-Id: I48c0de73338430282ce1a4442bbeb7c867dc174c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34079 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-07-10arch/cpu/x86: Update AMD detectionMarshall Dawson
AMD Picasso, and later, will not use CPU_AMD_AGESA or CPU_AMD_PI. Those two symbols indicate an Arch2008 system. Add SOC_AMD_COMMON to cause cpu_is_amd() to return TRUE on Picasso. This removes an error message of "Unknown CPU". The patch also assumes AMD Family 10h and non-AGESA Family 15h devices were seeing the "Unknown CPU" message. No functionality has been verified on these devices. Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Change-Id: I3357606c37082f3587ff91924bf7a0e0f8af9625 Reviewed-on: https://review.coreboot.org/c/coreboot/+/34146 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-09arch/x86: Avoid HAVE_SMI_HANDLER conditional with smm-classKyösti Mälkki
Build of the entire smm-class is skipped if we have HAVE_SMI_HANDLER=n. Change-Id: I10b4300ddd18b1673c404b45fd9642488ab3186c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34125 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Lance Zhao <lance.zhao@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-08src/arch/x86/acpigen: Compare dev_states_count to size_tElyes HAOUAS
Spotted out using -Wconversion gcc warning option. Change-Id: Ib882cfa6d429fbfcab2b8132280182b427d510aa Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33803 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-07arch/mips: Make MIPS specific options depend on ARCH_MIPSArthur Heymans
Also don't define the default as this result in spurious lines in the .config. TEST: The generated config.h remain exactly the same for all boards. Change-Id: I7f35a5a9dcbc7b25b7806056e2b8e822fa94e428 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31312 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Martin Roth <martinroth@google.com>
2019-07-07arch/x86: Use ssize_t to store lengthJacob Garber
size_t is the wrong type to store the return value of acpi_device_path_fill(), since any negative error values will be converted to a very large unsigned integer and potentially cause buffer overflow. Change-Id: Ia8ed62ecfac8eaa18a61545bd203b3c7a7cd9ca5 Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Found-by: Coverity CID 1402095 Reviewed-on: https://review.coreboot.org/c/coreboot/+/33962 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-07-07arch/x86: Clean up PIRQ_ROUTEKyösti Mälkki
This code is currently only used by via/epia-m850, it is also somewhat buggy. Change-Id: I140e15d584d3f60f7824bcb71ce63724c11e3f46 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34078 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-04arch/x86: Adjust size of postcar stackKyösti Mälkki
With VBOOT=y && VBOOT_MEASURED_BOOT=y message digest will be allocated from the stack and 1 KiB reserve used with the recent platforms was no longer sufficient. The comment of LZMA scratchpad consuming stack was obsolete for postcar, so these can be reduced to same 4 KiB. Change-Id: Iba1fb5bfad6946f316feac2d8c998a782142a56a Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33775 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2019-07-02arch/x86: Fix spelling error in BERT commentMarshall Dawson
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Change-Id: I57c0bcfbe0d96aac106f771e8efb3bd471302c25 Reviewed-on: https://review.coreboot.org/c/coreboot/+/33965 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-02arch/riscv: Make RISCV specific options depend on ARCH_RISCVArthur Heymans
Also don't define the default as this results in spurious lines in the .config. The only difference in the generated config.h is that for most board ARCH_RISCV_M goes from 1 to 0. This should not matter. Change-Id: I3e8c1cc5696d621e243696a3b5e34f62ab69a688 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31311 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-02arch/x86: Fix cpu_cpuid_extended_level() return typeElyes HAOUAS
`cpuid_eax()` returns an unsigned integer. Change-Id: Iebb6501130bc9ae333d45ae9d2e10c918245a6d1 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33814 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-07-02device/pci_rom: Fix redundant pci_rom_probe() callsKyösti Mälkki
For the PCI_VENDOR_ID_ATI case, we can rely on pci_rom_acpi_fill_vfct() to make the call if necessary. For hardware other than ATI, pci_rom_probe() was already called from pci_rom_ssdt() and pci_dev_init(), so PCI_ROM_ADDRESS BAR is already enabled, if requested so. Change-Id: I0ea893a9ac7ba480840ebf5570d8fe0d9e20938f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33909 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Mike Banon <mikebdp2@gmail.com>
2019-07-02security/memory: Clear memory in ramstagePatrick Rudolph
* Add architecture independend way of clearing all DRAM * Implemented in ramstage as MTRRs need to be set to speed up clearing. Takes up to 15 seconds per GiB otherwise. * Use memset_pae on x86 * Add quirks for FSP1.0 Tested on P8H61M-Pro: * Clears 4GiB in less than 1 second Tested on wedge100s: * Clears 8GiB in 2 seconds Change-Id: Idaadb8fb438e5b95557c0f65a14534e8762fde20 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31550 Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-28arch/riscv/mcall: Drop debug codePatrick Rudolph
The printk has no effect as console_init() hasn't been called. Also drop unused variables and headers. Change-Id: I5bf5a8822c69bbcc3de1de460d19585b8330649f Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33786 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Philipp Hug <philipp@hug.cx>
2019-06-23riscv: workaround selfboot putting the coreboot table into prog_entry_argXiang Wang
On RISC-V the argument to a payload is always the hartid and a pointer to a FDT. selfboot sets the coreboot tables as an argument, work around this here. Change-Id: If6929897c7f12d8acb079eeebaef512ae506ca8b Signed-off-by: Xiang Wang <wxjstz@126.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31477 Reviewed-by: ron minnich <rminnich@gmail.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Philipp Hug <philipp@hug.cx> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-23riscv: use mret to invoke M-mode payload and disable interruptsXiang Wang
Fixes a logic error that sets MPIE, but didn't use mret to return to the payload. This left MIE set to an undefined value. Now all modes are handled the same way: - Trap vector base address point to the payload - Disable Interrupt - Return to payload using mret TEST=Run an M-mode payload Change-Id: Iaab595f916949c57104ec00f8b06ea047fe76bba Signed-off-by: Xiang Wang <wxjstz@126.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33462 Reviewed-by: Philipp Hug <philipp@hug.cx> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-23riscv: Fix MENTRY_FRAME_SIZE to fit different machine lengthsXiang Wang
Change-Id: Iabe390963bcbeb9ec6016faa8312d101431942da Signed-off-by: Xiang Wang <wxjstz@126.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31976 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Hug <philipp@hug.cx>
2019-06-21arch: Add missing #include <commonlib/helpers.h>Elyes HAOUAS
ALIGN((a), b) and ALIGN_UP(a, b) needs 'helpers.h' Change-Id: I029c7c5cbb19c7e69997b3d84f929cb61e8e2b23 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33657 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-06-21arch/x86/acpi: use ALIGN_UP instead of ALIGNFelix Held
The ALIGN_UP macro is basically an alias of the ALIGN macro; with this change it's more obvious in which direction the alignment happens. Change-Id: I6f1b9f9bbcafeb85a6ef5c10ce4b57edc0740e72 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33627 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Lance Zhao <lance.zhao@gmail.com>
2019-06-21arch/arm/cpu: use ALIGN_UP instead of ALIGN for better readabilityFelix Held
Change-Id: Id0e281ece0a647721c18402029cd6980f75d5908 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33631 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2019-06-21arch/x86: use ALIGN_UP instead of ALIGN for better readabilityFelix Held
This patch contains the rest of the fixes for this subtree; having one change for every area would create an unnecessary amouint of patches. Change-Id: Id92c11d58693292d58cba323c8468db858becfb5 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33630 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-21arch/x86/tables: use ALIGN_UP instead of ALIGN for better readabilityFelix Held
Change-Id: Idfb814abee87d52d0f5970ec0cd291f738631320 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33629 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-21arch-x86/smbios: use ALIGN_UP instead of ALIGN for better readabilityFelix Held
ALIGN_UP is an alias for ALIGN. Change-Id: Ie723ebe80f8f627021151413cb43adce6c88a0dc Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33628 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-21fit: Refactor config node handlingJulius Werner
This patch makes some minor refactoring to the way the FIT parser handles config nodes. A lot of this code was written in the dawn age of depthcharge when its device tree library wasn't as well-stocked yet, so some of it can be rewritten nicer with more high-level primitives. There's no point in storing both the string name and the actual FDT node of a FIT image node separately, since the latter also contains the former, so remove that. Also eliminate code for the case of not having an FDT (which makes no sense), and move some more FDT validity/compat checking into fit_update_compat() (mostly in anticipation of later changes). This patch was adapted from depthcharge's http://crosreview.com/1553456 with a couple of modifications specific to coreboot's custom FIT loading code. Change-Id: Ia79e0fd0e1159c4aca64c453b82a0379b133350d Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32870 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-21arch/x86/cpu: Add define and strings for HygonJinke Fan
Chengdu Haiguang IC Design Co., Ltd (Hygon) is a Joint Venture between AMD and Haiguang Information Technology Co.,Ltd., aims at providing high performance x86 processor for China server market. Its first generation processor codename is Dhyana, which originates from AMD technology and shares most of the architecture with AMD's family 17h, but with different CPU Vendor ID ("HygonGenuine") /Family series number (Family 18h). More details can be found on: http://lkml.kernel.org/r/5ce86123a7b9dad925ac583d88d2f921040e859b.1538583282.git.puwen@hygon.cn Change-Id: I8af8b0f0675f978ac07522029696e43651a3153f Signed-off-by: Jinke Fan <fanjinke@hygon.cn> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32876 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Lance Zhao <lance.zhao@gmail.com> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-21arch/x86/rdrand.c: Remove unneeded 'else'Elyes HAOUAS
'else' is not needed after a 'break' or 'return'. Change-Id: Ib7bdefb0027a35de42f6a665b98f9e5a2791061f Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33331 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Vlado Cibic Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-06-19src/arch/x86/smbios: Change SMBIOS Version to 2.8Christian Walter
Change the SMBIOS Version from 2.7 to 2.8. Necessary changes were already pushed in https://review.coreboot.org/c/coreboot/+/33031 Change-Id: I237cdee7d43e814397b958e4cf941bf58949088d Signed-off-by: Christian Walter <christian.walter@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33564 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2019-06-19acpi: Add SPMI tablePatrick Rudolph
Add the SPMI table as defined in the IPMI spec v2: https://www.intel.com/content/dam/www/public/us/en/documents/product-briefs/ipmi-second-gen-interface-spec-v2-rev1-1.pdf Tested on Wedge100s. Change-Id: Idff5134ce4c124f7e76acb0080da404b0c0dfffe Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33487 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-17arm64: make comment match codeMarty E. Plummer
Change-Id: I37b8d5715cb6a32d4853e77098094cd5cffb9a4c Signed-off-by: Marty E. Plummer <hanetzer@startmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33486 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-06-173rdparty/blobs: Update submodule, SNB improvementsArthur Heymans
The sandybridge systemagent-r6 blob is modified: - To be more flexible about the location of the stack w.r.t. the heap - Place the MRC pool right below the MRC_VAR region - to work with the same DCACHE_RAM_BASE from the native raminit (could make the CAR linker symbols easily compatible if desired) This allows CAR setup compatibility between mrc.bin and native bootpath and also allows for BIOS/memory mappeds region larger than 8MB. This changes the semantics of CONFIG_DACHE_RAM_MRC_VAR_SIZE to also include the pool on top of MRC_VAR region. TESTED on T520 (boots and resumes from S3 with mrc.bin). Change-Id: I17d240656575b69a24718d90e4f2d2b7339d05a7 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33228 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-15arch/x86/Kconfig: hide the "Bootblock behaviour" option on non-romccArthur Heymans
Selecting which cbfs prefix to load is only implemented with the romcc bootblock. Change-Id: I09523b94605f00ab15b5f0ea3986ac08e3a6afc6 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33341 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-06-15arch/x86/Kconfig: Hide the prefix option on all but BOOTBLOCK_NORMALArthur Heymans
Change-Id: Icf5e8fa18bea1cdfb85b8a4999d8fccea94d16b9 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33324 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-06-13stage_cache: Make empty inline function if CONFIG_NO_STAGE_CACHE enableSubrata Banik
This patch removes CONFIG_NO_STAGE_CACHE check from caller function and add empty inline function incase CONFIG_NO_STAGE_CACHE is enable. Change-Id: I8e10ef2d261f9b204cecbeae6f65fda037753534 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33394 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-06-09acpigen: Add support for IndexFieldPatrick Rudolph
Add support for generating IndexField, which is similar to Field. Change-Id: If66a627e64953696b0b68488256bd5c141e4c205 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33032 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-06Makefile.inc: Compile smm files independent ARCH_RAMSTAGE_X86_32/64Subrata Banik
This patch makes smm related files compile independent of ramstage getting compiled. If user selects RAMPAYLOAD to boot without ramstage, there will be need for smm code to get compiled independently. Change-Id: I17a3eb80a4d5ef86e0319357c01b6bf5b90ef15b Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33115 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-06src/soc/intel/common/smbios: Add addtional infos to dimm_infoChristian Walter
Add ECC Support and VDD Voltage to dimm_info struct. Now Bus Width and ECCSupport will be propagated correctly in SMBIOS Type 17 Entry. Change-Id: Ic6f0d4b223f1490ec7aa71a6105603635b514021 Signed-off-by: Christian Walter <christian.walter@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33031 Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-05src/arch/x86: Prevent attack on null pointer dereferenceJohn Zhao
Clang Static Analyzer version 8.0.0 detects null pointer argument in call to memory copy function. Add sanity check for pointer header to prevent null pointer dereference. TEST=Built and boot up to kernel. Change-Id: I7027b7cae3009a5481048bfa0536a6cbd9bef683 Signed-off-by: John Zhao <john.zhao@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33051 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lance Zhao <lance.zhao@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-06-04arch/riscv/Kconfig: Make correct default value for CONFIG_ARCH_RISCV_MSubrata Banik
Change-Id: Ib9329904060cab48d527de1b1ccdab5b6fe71b99 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33144 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-02Makefile.inc: Remove unnecessary CONFIG dependencySubrata Banik
This patch removes unnecessary kconfig depencies as below 1. CONFIG_ARCH_RAMSTAGE_X86_32 2. CONFIG_RELOCATABLE_RAMSTAGE Include required files as is without specify kconfig option. Change-Id: Ic9d1a95e80178775dd78e756f97f6da13a24dc95 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33113 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: ron minnich <rminnich@gmail.com>
2019-05-29src/{include,arch,cpu,lib}: Add missing 'include <types.h>'Elyes HAOUAS
<types.h> is supposed to provide <stdint.h> and <stddef.h>. So when <types.h> is included, <stdint.h> and/or <stddef.h> is removed. Change-Id: I57aead27806e307b9827fc7ee2cd663f12ee6e5e Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31892 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
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