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2016-09-12src/arch: Improve code formattingElyes HAOUAS
Change-Id: Ic1ca6c2e1cd06800d7eb2d00ac0b328987d022ef Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16434 Tested-by: build bot (Jenkins) Reviewed-by: Omar Pakker
2016-09-12arch/arm: Add armv7-r configurationHakim Giydan
This change adds armv7-r support for all stages. armv7-r is an ARM processor based on the Cortex-R series. Currently, there is support for armv7-a and armv7-m and armv7-a files has been modfied to accommodate armv7-r by adding ENV_ARMV7_A, ENV_ARMV7_R and ENV_ARMV7_M constants to src/include/rules.h. armv7-r exceptions support will added in a later time. Change-Id: If94415d07fd6bd96c43d087374f609a2211f1885 Signed-off-by: Hakim Giydan <hgiydan@marvell.com> Reviewed-on: https://review.coreboot.org/15335 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-12arch/x86: Utilize additional MTRRs in postcar_frame_add_mtrrRizwan Qureshi
In the current implementation of postcar_frame_add_mtrr, if provided size is bigger than the base address alignment, the alignment is considered as size and covered by the MTRRs ignoring the specified size. In this case the callee has to make sure that the provided size should be smaller or equal to the base address alignment boundary. To simplify this, utilize additonal MTRRs to cover the entire size specified. We reuse the code from cpu/x86/mtrr/mtrr.c. Change-Id: Ie2e88b596f43692169c7d4440b18498a72fcba11 Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/16509 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-12arch/x86: Always compile postcar library in romstageRizwan Qureshi
postcar_loader.c has a useful library of funtions for setting up stack and MTRRs. Make it available in romstage irrespective of CONFIG_POSTCAR_STAGE for use in stack setup after Dram init. The final step of moving the used and max MTRRs on to stack is moved to a new function, that can be used outside of postcar phase. Change-Id: I322b12577d74268d03fe42a9744648763693cddd Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/16331 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-07include/arch/acpi.h: change IVRS efr field to iommu_feature_infoMartin Roth
The field that was previously named 'efr' is actually the iommu feature info field. The efr field is a 64-bit field that is only present in type 11h or type 40h headers that follows the iommu feature info field. Change-Id: I62c158a258d43bf1912fedd63cc31b80321a27c6 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/16508 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-09-07x86/acpi.c: use #define for IVRS revision fieldMartin Roth
The revision field was correct, but the comment was wrong. The revision 1 means that the IVRS table only uses fixed length device entries. Update the field to use the IVRS revision #define. Change-Id: I4c030b31e3e3f0a402dac36ab69f43d99e131c22 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/16507 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-09-07arch/x86/include: Add #defines for IVRS tablesMartin Roth
I/O Virtualization Reporting Structure (IVRS) definitions from: AMD I/O Virtualization Technology (IOMMU) Specification 48882—Rev 2.62—February 2015 Change-Id: I4809856eb922cbd9de4a2707cee78dba603af528 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/16506 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-09-04arch/acpi.h: add #if guard to handle the absence of device_t typeAntonello Dettori
Avoid the inclusion of a function declaration if the argument type device_t is not defined. This was not a problem until now because the old declaration of device_t and the new one overlapped. Change-Id: I05a6ef1bf65bf47f3c6933073ae2d26992348813 Signed-off-by: Antonello Dettori <dev@dettori.io> Reviewed-on: https://review.coreboot.org/16404 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-08-29arch/riscv: Add missing "break;"Jonathan Neuschäfer
Change-Id: Iea3f12a5a7eb37586f5424db2d7a84c4319492f8 Reported-by: Coverity (1361947) Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/16335 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2016-08-28src/arch: Add required space before opening parenthesis '('Elyes HAOUAS
Change-Id: I8a44a58506d7cf5ebc9fe7ac4f2b46f9544ba61a Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16287 Tested-by: build bot (Jenkins) Reviewed-by: Omar Pakker Reviewed-by: Martin Roth <martinroth@google.com>
2016-08-28src/arch: Capitalize CPU and ACPIElyes HAOUAS
Change-Id: I37dfa853c3dbe93a52f6c37941b17717e22f6430 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16277 Reviewed-by: Omar Pakker Tested-by: build bot (Jenkins)
2016-08-23arch/riscv: Add functions to read/write memory on behalf of supervisor/user modeJonathan Neuschäfer
Normally machine-mode code operates completely within physical address space. When emulating less privileged memory accesses (e.g. when the hardware doesn't support unaligned read/write), it is useful to access memory through the MMU (and with virtual addresses); this patch implements this functionality using the MPRV bit. Change-Id: Ic3b3301f348769faf3ee3ef2a78935dfbcbd15fd Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/16260 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2016-08-23arch/riscv: Map the kernel space into RAM (2GiB+)Jonathan Neuschäfer
Change-Id: I273e9d20e02f0333f28e0fc2adcc7940578ea93e Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/16263 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2016-08-23arch/riscv: Implement the SBI againJonathan Neuschäfer
Not all SBI calls are implemented, but it's enough to see a couple dozen lines of Linux boot output. It should also be noted that the SBI is still in flux: https://groups.google.com/a/groups.riscv.org/forum/#!topic/sw-dev/6oNhlW0OFKM Change-Id: I80e4fe508336d6428ca7136bc388fbc3cda4f1e4 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/16119 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2016-08-23arch/riscv: Enable U-mode/S-mode counters (stime, etc.)Jonathan Neuschäfer
Change-Id: Ie62f60b2e237fa4921384e3894569ae29639f563 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/16262 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2016-08-23arch/riscv: Fix unaligned memory access emulationJonathan Neuschäfer
Change-Id: I06c6493355f25f3780f75e345c517b434912696f Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/16261 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2016-08-23arch/riscv: Delegate exceptions to supervisor mode if appropriateJonathan Neuschäfer
Change-Id: I1c8127412af0f9acc5b5520dc324ac145e59a4bd Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/16160 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-08-23arch/riscv: Print the page table structure after constructionJonathan Neuschäfer
A new Kconfig option, DEBUG_PRINT_PAGE_TABLES, is added to control this behaviour. It is currently only available on RISC-V, but other architectures can use it, too, should the need arise. Change-Id: I52a863d8bc814ab3ed3a1f141d0a77edc6e4044d Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/16015 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-08-23arch/arm & arm64: Remove unnecessary whitespace before "\n"Elyes HAOUAS
Change-Id: Ibec78b25c0f330fc8517654761803e8abf203060 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16282 Tested-by: build bot (Jenkins) Reviewed-by: Omar Pakker Reviewed-by: Martin Roth <martinroth@google.com>
2016-08-15arch/riscv: Improve and refactor trap handling diagnosticsJonathan Neuschäfer
Change-Id: I57032f958c88ea83a420e93b459df4f620799d84 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/16016 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2016-08-15arch/riscv: Set the stack pointer upon trap entryJonathan Neuschäfer
Change-Id: I52fae62bc6cf775179963720fbcfaa9e07f6a717 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/16017 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2016-08-11arch/riscv: Fix the page table setup codeJonathan Neuschäfer
In particular: - Fix the condition of the loop that fills the mid-level page table - Adhere to the format of sptbr Change-Id: I575093445edfdf5a8f54b0f8622ff0e89f77ccec Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/16120 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2016-08-11arch/riscv: Update encoding.h and dependent filesJonathan Neuschäfer
I copied it from commit e10d2def7d of spike and made sure the copyright header is still there. Change-Id: Ie8b56cd2f4855b97d36a112a195866f4ff0feec5 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/15832 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-08-06acpi: Generate object for coreboot table regionDuncan Laurie
Generate an object to describe the coreboot table region in ACPI with the HID "CORE0000" so it can be used by kernel drivers. To keep track of the "CORE" HID usage add them to an enum and add a function to generate the HID in AML: Name (_HID, "CORExxxx") BUG=chromium:589817 BRANCH=none TEST=build and boot on chell, dump SSDT to verify contents: Device (CTBL) { Name (_HID, "CORE0000") // _HID: Hardware ID Name (_UID, Zero) // _UID: Unique ID Method (_STA, 0, NotSerialized) // _STA: Status { Return (0x0F) } Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings { Memory32Fixed (ReadOnly, 0x7AB84000, // Address Base 0x00008000, // Address Length ) }) } Change-Id: I2c681c1fee02d52b8df2e72f6f6f0b76fa9592fb Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/16056 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-08-04src/arch/riscv/id.S: Don't hardcode the stringsJonathan Neuschäfer
Change-Id: Ide87c45806c5e58775c77e7f780efb4cf81a70c9 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/16014 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2016-08-03ACPI: Add code to create root port entry in DMAR tableWerner Zeh
PCI root ports with "Address Translation Service" capability can be reported in DMAR table in the ATSR scope to let the OS know how to handle these devices the right way when VT-d is used. Add code to create an entry for a PCI root port using the type "SCOPE_PCI_SUB". Change-Id: Ie2c46db7292d9f1637ffe2e9cfaf6619372ddf13 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/15912 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-08-03ACPI: Add code to include ATSR structure in DMAR tableWerner Zeh
DMAR tables can contain so called "Address Translation Service Reporting" (ATSR) structure. It is applicable for platforms that support Device-TLBs and describe PCI root ports that have this ability. Add code to create this ATSR structure. In addition, a function to fix up the size of the ATSR structure is added as this is a new type and using the function acpi_dmar_drhd_fixup() can lead to confusion. Change-Id: Idc3f6025f597048151f0fd5ea6be04843041e1ab Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/15911 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-08-02arch/riscv: Add include/arch/barrier.hJonathan Neuschäfer
mb() is used in src/arch/riscv/ and src/mainboard/emulation/*-riscv/. It is currently provided by atomic.h, but I think it fits better into barrier.h. The "fence" instruction represents a full memory fence, as opposed to variants such as "fence r, rw" which represent a partial fence. An operating system might want to use precisely the right fence, but coreboot doesn't need this level of performance at the cost of simplicity. Change-Id: I8d33ef32ad31e8fda38f6a5183210e7bd6c65815 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/15830 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2016-08-01Remove non-ascii & unprintable charactersMartin Roth
These non-ascii & unprintable characters aren't needed. Change-Id: I129f729f66d6a692de729d76971f7deb7a19c254 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/15977 Tested-by: build bot (Jenkins) Reviewed-by: Omar Pakker Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-08-01arch/x86: Enable postcar consoleLee Leahy
Add a Kconfig value to enable the console during postcar. Add a call to console_init at the beginning of the postcar stage in exit_car.S. TEST=Build and run on Galileo Gen2 Change-Id: I66e2ec83344129ede2c7d6e5627c8062e28f50ad Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/16001 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-08-01arch/x86: Display MTRRs after MTRR update in postcarLee Leahy
Display the MTRRs after they have been updated during the postcar stage. TEST=Build and run on Galileo Gen2 Change-Id: I1532250cacd363c1eeaf72edc6cb9e9268a11375 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/15991 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-31src/arch: Capitalize CPU, RAM and ROMElyes HAOUAS
Change-Id: Ia6ac94a93b48037a392a9aec2cd19cd80369173f Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/15953 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2016-07-28arch/riscv: Refactor bootblock.SJonathan Neuschäfer
A few things are currently missing: - The trap handler doesn't set the stack pointer, which can easily result in trap loops or memory corruptions. - The SBI trampolin page (as described in version 1.9 of the RISC-V Privileged Architecture Specification), has been removed for now. Change-Id: Id89c859fab354501c94a0e82d349349c29fa4cc6 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/15591 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2016-07-28arch/riscv: Only initialize virtual memory if it's availableJonathan Neuschäfer
And do the detection just before the initialization. Change-Id: I9a52430262f799baa298dc4f4ea459880abe250e Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/15831 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2016-07-28arch/riscv: Remove spinlock code from atomic.hJonathan Neuschäfer
These functions are not used anywhere. Change-Id: Ica1f4650e8774dd796be0aff00054f3698087816 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/15829 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2016-07-27arch/x86: Add bootblock and postcar support for SOC MTRR accessLee Leahy
Quark does not support the rdmsr and wrmsr instructions. Use SOC specific routines to configure the MTRRs on Quark based platforms. Add cpu_common.c as a build dependency to provide access to the routine cpu_phys_address_size. TEST=Build and run on Galileo Gen2 Change-Id: I43b7067c66c5c55b42097937e862078adf17fb19 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/15846 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-26arch/x86: Generate a map file for the postcar stageLee Leahy
Place a map file for the postcar stage and place it into build/cbfs/fallback. TEST=Build and run on Galileo Gen2 Change-Id: I349c06e3c610db5b3f2511083208db27110c34d0 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/15845 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-26arch/x86: Organize ramstage to match other stagesLee Leahy
Move the ramstage files to the beginning of the section. Eliminate duplicate conditionals. TEST=Build and run on Galileo Gen2 Change-Id: I461a5b78a76bd0d2643b85973fd0a70bc5e89581 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/15892 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-26arch/x86: Move romstage files into romstage sectionLee Leahy
Move the romstage files into the romstage section of the file. Eliminate duplicate conditional statements. TEST=None Change-Id: Ie2d65cef3797a2c091c0cd76b147b30a765332ad Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/15891 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-07-26arch/x86: Move postcar stage commands into placeLee Leahy
Move the postcar commands to in between romstage and ramstage. Add the stage header. TEST=Build and run on Galileo Gen2 Change-Id: I530da6afd8ccbcea217995ddd27066df6d45de22 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/15844 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-19arch/riscv: Enable unaligned load handlingJonathan Neuschäfer
Change-Id: If1c63971335a6e2963e01352acfa4bd0c1d86bc2 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/15590 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-07-18arch/riscv: Remove enter_supervisorJonathan Neuschäfer
This function is unused since coreboot starts payloads in machine mode, and it uses the obsolete eret instruction. Change-Id: I98d7d0de5a3959821c21a0ba4319efb610fdefde Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/15729 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2016-07-18arch/riscv: Change all eret instructions to .word 0x30200073 (mret)Jonathan Neuschäfer
Using the opcode directly is necessary for the transition to the GCC 6.1.0 based toolchain, because the old toolchain only supports eret and the new toolchain only supports mret. Change-Id: I17e14d4793ae5259f7ce3ce0211cbb27305506cc Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/15290 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2016-07-17acpi: Change API called to write the name for ACPI_DP_TYPE_CHILDHarsha Priya
The API called to write the name of the child table in the dp entry (type ACPI_DP_TYPE_CHILD) was not including the quotes, e.g., it was DAAD and not "DAAD". Thus, the kernel driver did not get the right information from SSDT. Change the API to acpigen_write_string() to fix the issue. Signed-off-by: Harsha Priya <harshapriya.n@intel.com> Change-Id: Id33ad29e637bf1fe6b02e8a4b0fd9e220e8984e7 Reviewed-on: https://review.coreboot.org/15724 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-15arch/x86: provide common Intel ACPI hardware definitionsAaron Durbin
In the ACPI specification the PM1 register locations are well defined, but the sleep type values are hardware specific. That said, the Intel chipsets have been consistent with the values they use. Therefore, provide those hardware definitions as well a helper function for translating the hardware values to the more high level ACPI sleep values. BUG=chrome-os-partner:54977 Change-Id: Iaeda082e362de5d440256d05e6885b3388ffbe43 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15666 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins)
2016-07-15arch/x86: provide common ACPI_Sx constantsAaron Durbin
Instead of open coding the literal values provide more semantic symbol to be used. This will allow for aligning chipset code with this as well to reduce duplication. BUG=chrome-os-partner:54977 Change-Id: I022bf1eb258f7244f2e5aa2fb72b7b82e1900a5c Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15663 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-07-14spike-riscv: Look for the CBFS in RAMJonathan Neuschäfer
Change-Id: I98927a70adc45d9aca916bd985932b94287921de Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/15285 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins)
2016-07-14arch/riscv: Unconditionally start payloads in machine modeJonathan Neuschäfer
Ron Minnich writes: "we'll change cbfstool to put a header on the payload to jump to supervisor if that is desired. The principal here is that payloads are always started in machine mode, but we want to set the page tables up for them." Change-Id: I5cbfc90afd3febab33835935f08005136a3f47e9 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/15510 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2016-07-08acpi: Change device properties to work as a treeDuncan Laurie
There is a second ACPI _DSD document from the UEFI Forum that details how _DSD style tables can be nested, creating a tree of similarly formatted tables. This document is linked from acpi_device.h. In order to support this the device property interface needs to be more flexible and build up a tree of properties to write all entries at once instead of writing each entry as it is generated. In the end this is a more flexible solution that can support drivers that need child tables like the DA7219 codec, while only requiring minor changes to the existing drivers that use the device property interface. This was tested on reef (apollolake) and chell (skylake) boards to ensure that there was no change in the generated SSDT AML. Change-Id: Ia22e3a5fd3982ffa7c324bee1a8d190d49f853dd Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/15537 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-07acpigen_write_package: Return pointer to package element counterDuncan Laurie
Have acpigen_write_package() return a pointer to the package element counter so it can be used for dynamic package generation where needed. Change-Id: Id7f6dd03511069211ba3ee3eb29a6ca1742de847 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/15536 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-02acpi_device: Have acpi_device_scope() use a separate bufferDuncan Laurie
Have the different acpi_device_ path functions use a different static buffer so they can be called interchangeably. Change-Id: I270a80f66880861d5847bd586a16a73f8f1e2511 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/15521 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-07-02gpio: Add support for translating gpio_t into ACPI pinDuncan Laurie
Add a function for an SOC to define that will allow it to map the SOC-specific gpio_t value into an appropriate ACPI pin. The exact behavior depends on the GPIO implementation in the SOC, but it can be used to provide a pin number that is relative to the community or bank that a GPIO resides in. Change-Id: Icb97ccf7d6a9034877614d49166bc9e4fe659bcf Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/15512 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-28riscv/bootblock.S: Register machine-mode, not supervisor-mode trap handlerJonathan Neuschäfer
Change-Id: Ic42d8490cc02a3907e2989435aab786f7c0f39c9 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/15287 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2016-06-28arch/riscv: Show fault PC and load address on load access faultsJonathan Neuschäfer
Change-Id: Ib0535bf25ce25550cc17f64177f804a70aa13fb3 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/15286 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2016-06-28arch/riscv: Move _start to the beginning of the bootblockJonathan Neuschäfer
The different entry points (0x100, 0x140, ...), which were defined in the RISC-V Privileged Specification 1.7, aren't used anymore. Instead the Spike bootrom jumps at the start of our image, and traps are handled through mtvec. Change-Id: I865adec5e7a752a25bac93a45654ac06e27d5a8e Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/15283 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2016-06-24region: Add writeat and eraseat supportAntonello Dettori
Implement writeat and eraseat support into the region_device_ops struct. Change-Id: Iac2cf32e523d2f19ee9e5feefe1fba8c68982f3d Signed-off-by: Antonello Dettori <dev@dettori.io> Reviewed-on: https://review.coreboot.org/15318 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-06-24arch/x86/smbios: Correct manufacturer IDElyes HAOUAS
Correct standard manufacturer's identification code. Change-Id: I273711e121a61a91176c15cd4cab75420f1f5a39 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/15271 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-06-22ACPI S3: Add common recovery codeKyösti Mälkki
There is nothing to backup with RELOCATABLE_RAMSTAGE. Change-Id: I780a71e48d23e202fb0e9c70e34420066fa0e5b5 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/15243 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-22ACPI S3: Fix prohibited wakeupKyösti Mälkki
No boards affected, resume is always allowed when enabled in the build. Change-Id: I1816557da8201af9e137c389b57852ec20390b6a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/15275 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-22ACPI S3: Split support for HAVE_ACPI_RESUMEKyösti Mälkki
Some of the support functions will be built for romstage once HIGH_MEMORY_SAVE is removed. Change-Id: I43ed9067cf6b2152a354088c1dcb02d374eb6efe Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/15242 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-22ACPI S3: Move SMP trampoline recoveryKyösti Mälkki
No need to make low memory backup unless we are on S3 resume path. Hide those details from ACPI. Change-Id: Ic08b6d70c7895b094afdb3c77e020ff37ad632a1 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/15241 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-22Ignore RAMTOP for MTRRsKyösti Mälkki
Without RELOCATABLE_RAMSTAGE have WB cache large enough to cover the greatest ramstage needs, as there is no benefit of trying to accurately match the actual need. Choose this to be bottom 16MiB. With RELOCATABLE_RAMSTAGE write-back cache of low ram is only useful for bottom 1MiB of RAM as a small part of this gets used during SMP initialisation before proper MTRR setup. Change-Id: Icd5f8461f81ed0e671130f1142641a48d1304f30 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/15249 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-21riscv-spike: Move coreboot to 0x80000000 (2GiB)Jonathan Neuschäfer
This is where the RAM is (now), on RISC-V. We need to put coreboot.rom in RAM because Spike (at the moment) only supports loading code into the RAM, not into the boot ROM. Change-Id: I6c9b7cffe5fa414825491ee4ac0d2dad59a2d75c Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/15149 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-20ACPI S3: Cleanup RSDP referenceKyösti Mälkki
Variable name shadows parameter name used on other functions, and it can be local anyway after function removal. Change-Id: I3164b15b33d877fef139f48ab2091e60e3124c3b Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/15240 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-06-20arch/x86/smbios: Add DRAM manufacturerPatrick Rudolph
Add Ramaxel DRAM manufacturer id. Tested on Lenovo T520 and DDR3-1600 DIMM (RMT3170eb86e9w16). The manufacturer name shows up in dmidecode. Change-Id: I14cdc82c09f0f990e2ba18083748d11d79e53874 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/15183 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Alexander Couzens <lynxis@fe80.eu> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-06-17Move definitions of HIGH_MEMORY_SAVEKyösti Mälkki
This is more of ACPI S3 resume and x86 definition than CBMEM. Change-Id: Iffbfb2e30ab5ea0b736e5626f51c86c7452f3129 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/15190 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-06-17Define RAMTOP for x86 onlyKyösti Mälkki
This Kconfig is deprecated, new platforms need to locate ramstage stack in CBMEM instead. Change-Id: I20ece297302321337cc2ce17fdef0c55242a4fc3 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/15189 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-06-12arch/riscv: Compile with -mcmodel=medanyJonathan Neuschäfer
In the default (medlow) code model, pointers are loaded with a lui, addi instruction sequence: lui a0, 0xNNNNN addi a0, a0, 0xNNN Since lui sign-extends bits 32-63 from bit 31 on RV64, lui/addi can't load pointers just above 0x80000000, where RISC-V's RAM now lives. The medany code model gets around this restriction by loading pointers trough auipc and addi: auipc a0, 0xNNNNN addi a0, a0, 0xNNN This way, any pointer within the current pc ±2G can be loaded, which is by far sufficient for coreboot. Change-Id: I77350d9218a687284c1337d987765553cf915a22 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/15148 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2016-06-12arch/riscv: Add misc.c to bootblock/romstage to get udelay()Jonathan Neuschäfer
The uart8250mem driver needs it. Change-Id: I09e6a17cedf8a4045f008f5a0d225055d745e8db Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/15147 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2016-06-12arch/riscv: copy read/write8/16/32 from x86Jonathan Neuschäfer
Change-Id: I12de8f82499074f0fbbc1c09210b00c6a9614c1b Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/15146 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-06-12arch/riscv/trap_util.S: Use "li" pseudo-instruction to load a constantJonathan Neuschäfer
Change-Id: I9759771fa6fc708d7d97509c5f5e0cefb8ab4c96 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/14962 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2016-06-11arch/x86: Support "weak" BIST and timestamp save routinesLee Leahy
Not all x86 architectures support the mm register set. The default routine that saves BIST in mm0 and a "weak" routine that saves the TSC value in mm2:mm1. Select the Kconfig value BOOTBLOCK_SAVE_BIST_AND_TIMESTAMP to provide a replacement routine to save the BIST and timestamp values. TEST=Build and run on Amenia and Galileo Gen2. Change-Id: I8119e74664ac3522c011767d424d441cd62545ce Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/15126 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-11arch/x86: Add debug spinloops in assembly_entry.SLee Leahy
Use Kconfig values to enable debug spinloops in assembly_entry.S. This makes it easy to debug the assembly code. TEST=Build and run on Galileo Gen2 Change-Id: Ic56bf2260b8e3181403623961874c9289f3ca945 Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/15135 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-11arch/x86: Add debug spinloopLee Leahy
Conditionally add a debug spinloop to enable easy connection of JTAG debuggers. TEST=Build and run on Galileo Gen2 with a JTAG debugger. Change-Id: I7a21f9e6bfb10912d06ce48447c61202553630d0 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/15127 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-09mainboard: Support ROM_SIZE > 16 MiBLee Leahy
Support ROM_SIZE greater than 16 MiB. Work around SMBIOS rom size limitation of 16 MiB by specifying 16 MiB as the ROM size. TEST=Build and run on neoncity Change-Id: I3f464599cd8a1b6482db8b9deab03126c8b92128 Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/15108 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-06-09arch/x86: Enable SSE in bootblock_crt0.SLee Leahy
Don't write reserved bits in the Quark platform. Follow the previous boot behavior and just enable SSE. TEST=Build and run on Galileo Gen2 Change-Id: Ib3143eff02b2610b595bd666c10d70e43103ccda Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/15128 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-02SMBIOS: Implement SKU fieldKyösti Mälkki
Leave it for the platform to fill in the string. Change-Id: I7b4fe585f8d1efc8c9743f0d8b38de1f98124aab Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/14996 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@googlemail.com>
2016-05-28acpi_device: Add support for writing ACPI Device PropertiesDuncan Laurie
The recent ACPI specification extensions have formally defined a method for describing device information with a key=value format that is modeled after the Devicetree/DTS format using a special crafted object named _DSD with a specific UUID for this format. There are three defined Device Property types: Integers, Strings, and References. It is also possible to have arrays of these properties under one key=value pair. Strings and References are both represented as character arrays but result in different generated ACPI OpCodes. Various helpers are provided for writing the Device Property header (to fill in the object name and UUID) and footer (to fill in the property count and device length values) as well as for writing the different Device Property types. A specific helper is provided for writing the defined GPIO binding Device Property that is used to allow GPIOs to be referred to by name rather than resource index. This is all documented in the _DSD Device Properties UUID document: http://uefi.org/sites/default/files/resources/_DSD-device-properties-UUID.pdf This will be used by device drivers to provide device properties that are consumed by the operating system. Devicetree bindings are often described in the linux kernel at Documentation/devicetree/bindings/ A sample driver here has an input GPIO that it needs to describe to the kernel driver: chip.h: struct drivers_generic_sample_config { struct acpi_gpio mode_gpio; }; sample.c: static void acpi_fill_ssdt_generator(struct device *dev) { struct drivers_generic_sample_config *config = dev->chip_info; const char *path = acpi_device_path(dev); ... acpi_device_write_gpio(&config->mode_gpio); ... acpi_dp_write_header(); acpi_dp_write_gpio("mode-gpio", path, 0, 0, 0); acpi_dp_write_footer(); ... } devicetree.cb: device pci 1f.0 on chip drivers/generic/sample register "mode_gpio" = "ACPI_GPIO_INPUT(GPP_B1)" device generic 0 on end end end SSDT.dsl: Name (_CRS, ResourceTemplate () { GpioIo (Exclusive, PullDefault, 0, 0, IoRestrictionInputOnly, "\\_SB.PCI0.GPIO", 0, ResourceConsumer) { 25 } }) Name (_DSD, Package () { ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), Package () { Package () {"mode-gpio", Package () { \_SB.PCI0.LPCB, 0, 0, 1 }} } }) Change-Id: I93ffd09e59d05c09e38693e221a87085469be3ad Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/14937 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-05-28acpi_device: Add support for writing ACPI SPI descriptorsDuncan Laurie
Add required definitions to describe an ACPI SPI bus and a method to write the SpiSerialBus() descriptor to the SSDT. This will be used by device drivers to describe their SPI resources to the OS. SPI devices are not currently enumerated in the devicetree but can be enumerated by device drivers directly. generic.c: void acpi_fill_ssdt_generator(struct device *dev) { struct acpi_spi spi = { .device_select = dev->path->generic.device.id, .device_select_polarity = SPI_POLARITY_LOW, .spi_wire_mode = SPI_4_WIRE_MODE, .speed = 1000 * 1000; /* 1 mHz */ .data_bit_length = 8, .clock_phase = SPI_CLOCK_PHASE_FIRST, .clock_polarity = SPI_POLARITY_LOW, .resource = acpi_device_path(dev->bus->dev) }; ... acpi_device_write_spi(&spi); ... } devicetree.cb: device pci 1e.2 on chip drivers/spi/generic device generic 0 on end end end SSDT.dsl: SpiSerialBus (0, PolarityLow, FourWireMode, 8, ControllerInitiated, 1000000, ClockPolarityLow, ClockPhaseFirst, "\\_SB.PCI0.SPI0", 0, ResourceConsumer) Change-Id: I0ef83dc111ac6c19d68872ab64e1e5e3a7756cae Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/14936 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-05-28acpi_device: Add support for writing ACPI I2C descriptorsDuncan Laurie
Add required definitions to describe an ACPI I2C bus and a method to write the I2cSerialBus() descriptor to the SSDT. This will be used by device drivers to describe their I2C resources to the OS. The devicetree i2c device can supply the address and 7 or 10 bit mode as well as indicate the GPIO controller device, and the bus speed can be fixed or configured by the driver. chip.h: struct drivers_i2c_generic_config { enum i2c_speed bus_speed; }; generic.c: void acpi_fill_ssdt_generator(struct device *dev) { struct drivers_i2c_generic_config *config = dev->chip_info; struct acpi_i2c i2c = { .address = dev->path->i2c.device, .mode_10bit = dev->path.i2c.mode_10bit, .speed = config->bus_speed ? : I2C_SPEED_FAST, .resource = acpi_device_path(dev->bus->dev) }; ... acpi_device_write_i2c(&i2c); ... } devicetree.cb: device pci 15.0 on chip drivers/i2c/generic device i2c 10.0 on end end end SSDT.dsl: I2cSerialBus (0x10, ControllerInitiated, 400000, AddressingMode7Bit, "\\_SB.PCI0.I2C0", 0, ResourceConsumer) Change-Id: I598401ac81a92c72f19da0271af1e218580a6c49 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/14935 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-05-28acpi_device: Add support for writing ACPI GPIO descriptorsDuncan Laurie
Add definitions to describe GPIOs in generated ACPI objects and a method to write a GpioIo() or GpioInt() descriptor to the SSDT. ACPI GPIOs have many possible configuration options and a structure is created to describe it accurately in ACPI terms. There are many shared descriptor fields between GpioIo() and GpioInt() so the same function can write both types. GpioInt shares many properties with ACPI Interrupts and the same types are re-used here where possible. One addition is that GpioInt can be configured to trigger on both low and high edge transitions. One descriptor can describe multiple GPIO pins (limited to 8 in this implementation) that all share configuration and controller and are used by the same device scope. Accurately referring to the GPIO controller that this pin is connected to requires the SoC/board to implement a function handler for acpi_gpio_path(), or for the caller to provide this directly as a string in the acpi_gpio->reference variable. This will get used by device drivers to describe their resources in the SSDT. Here is a sample for a Maxim 98357A I2S codec which has a GPIO for power and channel selection called "sdmode". chip.h: struct drivers_generic_max98357a_config { struct acpi_gpio sdmode_gpio; }; max98357a.c: void acpi_fill_ssdt_generator(struct device *dev) { struct drivers_generic_max98357a_config *config = dev->chip_info; ... acpi_device_write_gpio(&config->sdmode_gpio); ... } devicetree.cb: device pci 1f.3 on chip drivers/generic/max98357a register "sdmode_gpio" = "ACPI_GPIO_OUTPUT(GPP_C5)" device generic 0 on end end end SSDT.dsl: GpioIo (Exclusive, PullDefault, 0, 0, IoRestrictionOutputOnly, "\\_SB.PCI0.GPIO", 0, ResourceConsumer, ,) { 53 } Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Change-Id: Ibf5bab9c4bf6f21252373fb013e78f872550b167 Reviewed-on: https://review.coreboot.org/14934 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-05-28acpi_device: Add support for writing ACPI Interrupt descriptorsDuncan Laurie
Add definitions for ACPI device extended interrupts and a method to write an Interrupt() descriptor to the SSDT output stream. Interrupts are often tied together with other resources and some configuration items are shared (though not always compatibly) with other constructs like GPIOs and GPEs. These will get used by device drivers to write _CRS sections for devices into the SSDT. One usage is to include a "struct acpi_irq" inside a config struct for a device so it can be initialized based on settings in devicetree. Example usage: chip.h: struct drivers_i2c_generic_config { struct acpi_irq irq; }; generic.c: void acpi_fill_ssdt_generator(struct device *dev) { struct drivers_i2c_generic_config *config = dev->chip_info; ... acpi_device_write_interrupt(&config->irq); ... } devicetree.cb: device pci 15.0 on chip drivers/i2c/generic register "irq" = "IRQ_EDGE_LOW(GPP_E7_IRQ)" device i2c 10 on end end end SSDT.dsl: Interrupt (ResourceConsumer, Edge, ActiveLow, Exclusive,,,) { 31 } Change-Id: I3b64170cc2ebac178e7a17df479eda7670a42703 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/14933 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-05-27arch/x86: provide verstage support for CONFIG_C_ENVIRONMENT_BOOTBLOCKAaron Durbin
When CONFIG_C_ENVIRONMENT_BOOTBLOCK is employed there's no need for a chipset specific verstage entry point because cache-as-ram has already been initialized. Therefore, provide a default entry point for verstage in that environment. Change-Id: Idd8f45bd58d3e5b251d1e38cca7ae794b8b77a28 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/14971 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
2016-05-24arm64: Add stack dump to exception handlerJulius Werner
Some exceptions (like from calling a NULL function pointer) are easier to narrow down with a dump of the call stack. Let's take a page out of ARM32's book and add that feature to ARM64 as well. Also change the output format to two register columns, to make it easier to fit a whole exception dump on one screen. Applying to both coreboot and libpayload and syncing the output format between both back up. Change-Id: I19768d13d8fa8adb84f0edda2af12f20508eb2db Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/14931 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-05-21device: Add an ACPI device name and path concept to devicesDuncan Laurie
Add a function to "struct device_operations" to return the ACPI name for the device, and helper functions to find this name (either from the device or its parent) and to build a fully qualified ACPI path from the root device. This addition will allow device drivers to generate their ACPI AML in the SSDT at boot, with customization supplied by devicetree.cb, instead of needing custom DSDT ASL for every mainboard. The root device acpi_name is defined as "\\_SB" and is used to start the path when building a fully qualified name. This requires SOC support to provide handlers for returning the ACPI name for devices that it owns, and those names must match the objects declared in the DSDT. The handler can be done either in each device driver or with a global handler for the entire SOC. Simplified example of how this can be used for an i2c device declared in devicetree.cb with: chip soc/intel/skylake # "\_SB" (from root device) device domain 0 on # "PCI0" device pci 19.2 on # "I2C4" chip drivers/i2c/test0 device i2c 1a.0 on end # "TST0" end end end end And basic SSDT generating code in the device driver: acpigen_write_scope(acpi_device_scope(dev)); acpigen_write_device(acpi_device_name(dev)); acpigen_write_string("_HID", "TEST0000"); acpigen_write_byte("_UID", 0); acpigen_pop_len(); /* device */ acpigen_pop_len(); /* scope */ Will produce this ACPI code: Scope (\_SB.PCI0.I2C4) { Device (TST0) { Name (_HID, "TEST0000") Name (_UID, 0) } } Change-Id: Ie149595aeab96266fa5f006e7934339f0119ac54 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/14840 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-05-21acpigen: Add function to generate ToUUID() from a stringDuncan Laurie
acpigen_write_uuid() will generate a ToUUID() 128-bit buffer object for a common universally unique identifier that is passed as a string. The resulting buffer is the UUID in byte format with a specific order of the bytes as described in the ACPI specification: ToUUID (uuid) Compiles to: Buffer (16) { uuid[3], uuid[2], uuid[1], uuid[0], uuid[5], uuid[4], uuid[7], uuid[6], uuid[8], uuid[9], uuid[10], uuid[11], uuid[12], uuid[13], uuid[14], uuid[15] } Change-Id: Ibbeff926883532dd78477aaa2d26ffffb6ef30c0 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/14838 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-05-19arch/x86: Include timestamp.c in all stagesAlexandru Gagniuc
timestamp.c was not included in bootblock and postcar. This means that these two stages would use the weak implementation in lib/timestamp.c instead of the arch-specific implementation based on rdtsc. This resulted in using timer_monotonic_get() which resets the timestamps from 0. timer_monotonic_get() only provides per-stage incrementing semantics on x86 because lapic implementation has counting down values. A globally incrementing counter like rdtsc provides the semantics like every other non-x86. On the test configuration, the weak implementation of timestamp_get() returned zero, resulting in wrong timestamps coming from the bootblock, while romstage and ramstage used the arch implementation and returned correct timestamps. This is a great example of why weak functions are dangerous, and how easy it is to miss subtle yet strong interactions between subsystems and the coreboot buildsystem. Change-Id: I656f9bd58a6fc179d9dbbc496c5b684ea9288eb5 Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc@intel.com> Reviewed-on: https://review.coreboot.org/14860 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-05-17acpigen: Fix ?: operator confusionJonathan Neuschäfer
strlen(string) was on the "negative" side of the selection operator, the side where string is NULL. Change-Id: Ic421a5406ef788c504e30089daeba61a195457ae Reported-by: Coverity Scan (CID 1355263) Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/14867 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@google.com>
2016-05-16acpigen: Add functions to generate _STA() and _PRW()Duncan Laurie
Add helper functions for generating some common objects: acpigen_write_STA(status) will generate a status method that will indicate the device status as provided: Method (_STA) { Return (status) } Full status byte configuration is possible and macros are provided for the common status bytes used for generated code: ACPI_STATUS_DEVICE_ALL_OFF = 0x0 ACPI_STATUS_DEVICE_ALL_ON = 0xF acpigen_write_PRW() will generate a Power Resoruce for Wake that describes the GPE that will wake a particular device: Name (_PRW, Package (2) { wake, level } Change-Id: I10277f0f3820d272d3975abf34b9a8de577782e5 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/14795 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-05-16acpigen: Add an abstracted integer output methodDuncan Laurie
In order to produce smaller AML and not rely on the caller to size the output type appropriately add a helper function that will output an appropriately sized integer. To complete this also add helper functions for outputting the single OpCode for Zero and One and Ones. And finally add "name" variants of the helpers that will output a complete sequence like "Name (_UID, Zero)". Change-Id: I7ee4bc0a6347d15b8d49df357845a8bc2e517407 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/14794 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-05-16acpigen: Add helper functions for stringsDuncan Laurie
Add helper function to emit a string into the SSDT AML bytestream with a NULL terminator. Also add a helper function to emit the string OpCode followed by the string itself. acpigen_emit_string(string) /* Raw string output */ acpigen_write_string(string) /* OpCode followed by raw string */ Change-Id: I4a3a8728066e0c41d7ad6429fad983e6ae6962fe Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/14793 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-05-16acpigen: Add helpers for word/dword outputDuncan Laurie
Add helpers for writing word and dword values in acpigen and use them throughout the file to clean things up: acpigen_emit_word - write raw word acpigen_emit_dword - write raw dword acpigen_write_word - write word opcode and value Change-Id: Ia758d4dd25d0ae5b31be7d51b33866dddd96a473 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/14792 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-05-10arch/arm64: add FRAMEBUFFER region macros to memlayoutLin Huang
BRANCH=none BUG=chrome-os-partner:51537 TEST=build pass Change-Id: Id3dd3a553370eada1e79708dc71afc2d94d6ce93 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 0949b0d9ec12eff7edb3d7de738833f29507c332 Original-Change-Id: I8052f86d4d846e5d544911c5b9e323285083fb5c Original-Signed-off-by: Lin Huang <hl@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/340024 Original-Commit-Ready: Vadim Bendebury <vbendeb@google.com> Original-Tested-by: Shunqian Zheng <zhengsq@rock-chips.com> Original-Reviewed-by: Vadim Bendebury <vbendeb@google.com> Reviewed-on: https://review.coreboot.org/14747 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-05-09smbios: Add SuperTalent SPD IDTimothy Pearson
Change-Id: I5373be7ab55ac3c4f2e4dd753c6ad8e91712ff7e Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/14738 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-05-09arch/armv7: Fix end index calculation in mmu_config_range_kbVaradarajan Narayanan
BUG=chrome-os-partner:49249 TEST=None. Initial code not sure if it will even compile BRANCH=none Change-Id: Ib0fccfe2d103710c006cb3950c65b11b8d596912 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 9be5f58bb89ec43d4eb264c94c3f745dcade35dd Original-Change-Id: If50efb55d4974dfcab07d3ae6488c2413b505a1f Original-Signed-off-by: Varadarajan Narayanan <varada@codeaurora.org> Original-Reviewed-on: https://chromium-review.googlesource.com/333301 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/14657 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins)
2016-05-03arch/x86: Drop CBFS_BASE_ADDRESSPatrick Georgi
It's unused. Change-Id: I50af2b50d2c5a7a24afe9099c5c01d17ce54a6c9 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/14569 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-05-03build system: remove CBFSTOOL_PRE1_OPTSPatrick Georgi
It isn't used anymore. Change-Id: Ie554d1dd87ae3f55547466e484c0864e55c9d102 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/14567 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-05-02arch/x86/assembly_entry: allow early post CAR stages to use common codeAaron Durbin
The skylake-based Chromebooks use a separate verstage which runs just after bootblock and prior to romstage. The normal path for romstage would be to reload the gdt, however in the previously described scenario has verstage performing that work. Therefore, provide that path under those conditions. The only difference from the C_ENVIRONMENT_BOOTBLOCK scenario is that the stack should not be reloaded since there's no way to know the top of the stack. Change-Id: Ic39ab52a856233d3042ac02a15ae4816ddfe07c7 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/14548 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) Reviewed-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com>
2016-05-02arch/x86/asembly_entry: reorder conditional stage entry macrosAaron Durbin
The path that just clears CAR_GLOBAL variables and jumps to the stage entry point needs another condition for separate verstage just after bootblock. However, the current conditional is a negative conditional so swap the logic around to make it easier to extend. Change-Id: Iab6682498054715a6eaa0476390da6355238b9bc Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/14547 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com>
2016-05-02lib/coreboot_table: use the architecture dependent table sizeAaron Durbin
Utilize the architecture dependent coreboot table size value from <arch/cbconfig.h> Change-Id: I80d51a5caf7c455b0b47c380e1d79cf522502a4c Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/14455 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-17 21:52:16 +0000